mips/pci/fixup-fuloong2e.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (C) 2004 ICT CAS
0004  * Author: Li xiaoyu, ICT CAS
0005  *   lixy@ict.ac.cn
0006  *
0007  * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology
0008  * Author: Fuxin Zhang, zhangfx@lemote.com
0009  */
0010 #include <linux/init.h>
0011 #include <linux/pci.h>
0012
0013 #include <loongson.h>
0014
0015 /* South bridge slot number is set by the pci probe process */
0016 static u8 sb_slot = 5;
0017
0018 int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
0019 {
0020     int irq = 0;
0021
0022     if (slot == sb_slot) {
0023         switch (PCI_FUNC(dev->devfn)) {
0024         case 2:
0025             irq = 10;
0026             break;
0027         case 3:
0028             irq = 11;
0029             break;
0030         case 5:
0031             irq = 9;
0032             break;
0033         }
0034     } else {
0035         irq = LOONGSON_IRQ_BASE + 25 + pin;
0036     }
0037     return irq;
0038
0039 }
0040
0041 /* Do platform specific device initialization at pci_enable_device() time */
0042 int pcibios_plat_dev_init(struct pci_dev *dev)
0043 {
0044     return 0;
0045 }
0046
0047 static void loongson2e_nec_fixup(struct pci_dev *pdev)
0048 {
0049     unsigned int val;
0050
0051     /* Configures port 1, 2, 3, 4 to be validate*/
0052     pci_read_config_dword(pdev, 0xe0, &val);
0053     pci_write_config_dword(pdev, 0xe0, (val & ~7) | 0x4);
0054
0055     /* System clock is 48-MHz Oscillator. */
0056     pci_write_config_dword(pdev, 0xe4, 1 << 5);
0057 }
0058
0059 static void loongson2e_686b_func0_fixup(struct pci_dev *pdev)
0060 {
0061     unsigned char c;
0062
0063     sb_slot = PCI_SLOT(pdev->devfn);
0064
0065     printk(KERN_INFO "via686b fix: ISA bridge\n");
0066
0067     /*  Enable I/O Recovery time */
0068     pci_write_config_byte(pdev, 0x40, 0x08);
0069
0070     /*  Enable ISA refresh */
0071     pci_write_config_byte(pdev, 0x41, 0x01);
0072
0073     /*  disable ISA line buffer */
0074     pci_write_config_byte(pdev, 0x45, 0x00);
0075
0076     /*  Gate INTR, and flush line buffer */
0077     pci_write_config_byte(pdev, 0x46, 0xe0);
0078
0079     /*  Disable PCI Delay Transaction, Enable EISA ports 4D0/4D1. */
0080     /* pci_write_config_byte(pdev, 0x47, 0x20); */
0081
0082     /*
0083      *  enable PCI Delay Transaction, Enable EISA ports 4D0/4D1.
0084      *  enable time-out timer
0085      */
0086     pci_write_config_byte(pdev, 0x47, 0xe6);
0087
0088     /*
0089      * enable level trigger on pci irqs: 9,10,11,13
0090      * important! without this PCI interrupts won't work
0091      */
0092     outb(0x2e, 0x4d1);
0093
0094     /*  512 K PCI Decode */
0095     pci_write_config_byte(pdev, 0x48, 0x01);
0096
0097     /*  Wait for PGNT before grant to ISA Master/DMA */
0098     pci_write_config_byte(pdev, 0x4a, 0x84);
0099
0100     /*
0101      * Plug'n'Play
0102      *
0103      *  Parallel DRQ 3, Floppy DRQ 2 (default)
0104      */
0105     pci_write_config_byte(pdev, 0x50, 0x0e);
0106
0107     /*
0108      * IRQ Routing for Floppy and Parallel port
0109      *
0110      *  IRQ 6 for floppy, IRQ 7 for parallel port
0111      */
0112     pci_write_config_byte(pdev, 0x51, 0x76);
0113
0114     /* IRQ Routing for serial ports (take IRQ 3 and 4) */
0115     pci_write_config_byte(pdev, 0x52, 0x34);
0116
0117     /*  All IRQ's level triggered. */
0118     pci_write_config_byte(pdev, 0x54, 0x00);
0119
0120     /* route PIRQA-D irq */
0121     pci_write_config_byte(pdev, 0x55, 0x90);    /* bit 7-4, PIRQA */
0122     pci_write_config_byte(pdev, 0x56, 0xba);    /* bit 7-4, PIRQC; */
0123                             /* 3-0, PIRQB */
0124     pci_write_config_byte(pdev, 0x57, 0xd0);    /* bit 7-4, PIRQD */
0125
0126     /* enable function 5/6, audio/modem */
0127     pci_read_config_byte(pdev, 0x85, &c);
0128     c &= ~(0x3 << 2);
0129     pci_write_config_byte(pdev, 0x85, c);
0130
0131     printk(KERN_INFO"via686b fix: ISA bridge done\n");
0132 }
0133
0134 static void loongson2e_686b_func1_fixup(struct pci_dev *pdev)
0135 {
0136     printk(KERN_INFO"via686b fix: IDE\n");
0137
0138     /* Modify IDE controller setup */
0139     pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 48);
0140     pci_write_config_byte(pdev, PCI_COMMAND,
0141                   PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
0142                   PCI_COMMAND_MASTER);
0143     pci_write_config_byte(pdev, 0x40, 0x0b);
0144     /* legacy mode */
0145     pci_write_config_byte(pdev, 0x42, 0x09);
0146
0147 #if 1/* play safe, otherwise we may see notebook's usb keyboard lockup */
0148     /* disable read prefetch/write post buffers */
0149     pci_write_config_byte(pdev, 0x41, 0x02);
0150
0151     /* use 3/4 as fifo thresh hold  */
0152     pci_write_config_byte(pdev, 0x43, 0x0a);
0153     pci_write_config_byte(pdev, 0x44, 0x00);
0154
0155     pci_write_config_byte(pdev, 0x45, 0x00);
0156 #else
0157     pci_write_config_byte(pdev, 0x41, 0xc2);
0158     pci_write_config_byte(pdev, 0x43, 0x35);
0159     pci_write_config_byte(pdev, 0x44, 0x1c);
0160
0161     pci_write_config_byte(pdev, 0x45, 0x10);
0162 #endif
0163
0164     printk(KERN_INFO"via686b fix: IDE done\n");
0165 }
0166
0167 static void loongson2e_686b_func2_fixup(struct pci_dev *pdev)
0168 {
0169     /* irq routing */
0170     pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, 10);
0171 }
0172
0173 static void loongson2e_686b_func3_fixup(struct pci_dev *pdev)
0174 {
0175     /* irq routing */
0176     pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, 11);
0177 }
0178
0179 static void loongson2e_686b_func5_fixup(struct pci_dev *pdev)
0180 {
0181     unsigned int val;
0182     unsigned char c;
0183
0184     /* enable IO */
0185     pci_write_config_byte(pdev, PCI_COMMAND,
0186                   PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
0187                   PCI_COMMAND_MASTER);
0188     pci_read_config_dword(pdev, 0x4, &val);
0189     pci_write_config_dword(pdev, 0x4, val | 1);
0190
0191     /* route ac97 IRQ */
0192     pci_write_config_byte(pdev, 0x3c, 9);
0193
0194     pci_read_config_byte(pdev, 0x8, &c);
0195
0196     /* link control: enable link & SGD PCM output */
0197     pci_write_config_byte(pdev, 0x41, 0xcc);
0198
0199     /* disable game port, FM, midi, sb, enable write to reg2c-2f */
0200     pci_write_config_byte(pdev, 0x42, 0x20);
0201
0202     /* we are using Avance logic codec */
0203     pci_write_config_word(pdev, 0x2c, 0x1005);
0204     pci_write_config_word(pdev, 0x2e, 0x4710);
0205     pci_read_config_dword(pdev, 0x2c, &val);
0206
0207     pci_write_config_byte(pdev, 0x42, 0x0);
0208 }
0209
0210 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686,
0211              loongson2e_686b_func0_fixup);
0212 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1,
0213              loongson2e_686b_func1_fixup);
0214 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2,
0215              loongson2e_686b_func2_fixup);
0216 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3,
0217              loongson2e_686b_func3_fixup);
0218 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_5,
0219              loongson2e_686b_func5_fixup);
0220 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_USB,
0221              loongson2e_nec_fixup);