mips/pci/fixup-cobalt.c

0001 /*
0002  * Cobalt Qube/Raq PCI support
0003  *
0004  * This file is subject to the terms and conditions of the GNU General Public
0005  * License.  See the file "COPYING" in the main directory of this archive
0006  * for more details.
0007  *
0008  * Copyright (C) 1995, 1996, 1997, 2002, 2003 by Ralf Baechle
0009  * Copyright (C) 2001, 2002, 2003 by Liam Davies (ldavies@agile.tv)
0010  */
0011 #include <linux/types.h>
0012 #include <linux/pci.h>
0013 #include <linux/kernel.h>
0014 #include <linux/init.h>
0015
0016 #include <asm/io.h>
0017 #include <asm/gt64120.h>
0018
0019 #include <cobalt.h>
0020 #include <irq.h>
0021
0022 /*
0023  * PCI slot numbers
0024  */
0025 #define COBALT_PCICONF_CPU  0x06
0026 #define COBALT_PCICONF_ETH0 0x07
0027 #define COBALT_PCICONF_RAQSCSI  0x08
0028 #define COBALT_PCICONF_VIA  0x09
0029 #define COBALT_PCICONF_PCISLOT  0x0A
0030 #define COBALT_PCICONF_ETH1 0x0C
0031
0032 /*
0033  * The Cobalt board ID information.  The boards have an ID number wired
0034  * into the VIA that is available in the high nibble of register 94.
0035  */
0036 #define VIA_COBALT_BRD_ID_REG  0x94
0037 #define VIA_COBALT_BRD_REG_to_ID(reg)   ((unsigned char)(reg) >> 4)
0038
0039 /*
0040  * Default value of PCI Class Code on GT64111 is PCI_CLASS_MEMORY_OTHER (0x0580)
0041  * instead of PCI_CLASS_BRIDGE_HOST (0x0600). Galileo explained this choice in
0042  * document "GT-64111 System Controller for RC4640, RM523X and VR4300 CPUs",
0043  * section "6.5.3 PCI Autoconfiguration at RESET":
0044  *
0045  *   Some PCs refuse to configure host bridges if they are found plugged into
0046  *   a PCI slot (ask the BIOS vendors why...). The "Memory Controller" Class
0047  *   Code does not cause a problem for these non-compliant BIOSes, so we used
0048  *   this as the default in the GT-64111.
0049  *
0050  * So fix the incorrect default value of PCI Class Code. More details are on:
0051  * https://lore.kernel.org/r/20211102154831.xtrlgrmrizl5eidl@pali/
0052  * https://lore.kernel.org/r/20211102150201.GA11675@alpha.franken.de/
0053  */
0054 static void qube_raq_galileo_early_fixup(struct pci_dev *dev)
0055 {
0056     if (dev->devfn == PCI_DEVFN(0, 0) &&
0057         (dev->class >> 8) == PCI_CLASS_MEMORY_OTHER) {
0058
0059         dev->class = (PCI_CLASS_BRIDGE_HOST << 8) | (dev->class & 0xff);
0060
0061         printk(KERN_INFO "Galileo: fixed bridge class\n");
0062     }
0063 }
0064
0065 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111,
0066      qube_raq_galileo_early_fixup);
0067
0068 static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev)
0069 {
0070     unsigned short cfgword;
0071     unsigned char lt;
0072
0073     /* Enable Bus Mastering and fast back to back. */
0074     pci_read_config_word(dev, PCI_COMMAND, &cfgword);
0075     cfgword |= (PCI_COMMAND_FAST_BACK | PCI_COMMAND_MASTER);
0076     pci_write_config_word(dev, PCI_COMMAND, cfgword);
0077
0078     /* Enable both ide interfaces. ROM only enables primary one.  */
0079     pci_write_config_byte(dev, 0x40, 0xb);
0080
0081     /* Set latency timer to reasonable value. */
0082     pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lt);
0083     if (lt < 64)
0084         pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
0085     pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
0086 }
0087
0088 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1,
0089      qube_raq_via_bmIDE_fixup);
0090
0091 static void qube_raq_galileo_fixup(struct pci_dev *dev)
0092 {
0093     if (dev->devfn != PCI_DEVFN(0, 0))
0094         return;
0095
0096     /* Fix PCI latency-timer and cache-line-size values in Galileo
0097      * host bridge.
0098      */
0099     pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
0100     pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
0101
0102     /*
0103      * The code described by the comment below has been removed
0104      * as it causes bus mastering by the Ethernet controllers
0105      * to break under any kind of network load. We always set
0106      * the retry timeouts to their maximum.
0107      *
0108      * --x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--
0109      *
0110      * On all machines prior to Q2, we had the STOP line disconnected
0111      * from Galileo to VIA on PCI.  The new Galileo does not function
0112      * correctly unless we have it connected.
0113      *
0114      * Therefore we must set the disconnect/retry cycle values to
0115      * something sensible when using the new Galileo.
0116      */
0117
0118     printk(KERN_INFO "Galileo: revision %u\n", dev->revision);
0119
0120 #if 0
0121     if (dev->revision >= 0x10) {
0122         /* New Galileo, assumes PCI stop line to VIA is connected. */
0123         GT_WRITE(GT_PCI0_TOR_OFS, 0x4020);
0124     } else if (dev->revision == 0x1 || dev->revision == 0x2)
0125 #endif
0126     {
0127         signed int timeo;
0128         /* XXX WE MUST DO THIS ELSE GALILEO LOCKS UP! -DaveM */
0129         timeo = GT_READ(GT_PCI0_TOR_OFS);
0130         /* Old Galileo, assumes PCI STOP line to VIA is disconnected. */
0131         GT_WRITE(GT_PCI0_TOR_OFS,
0132             (0xff << 16) |      /* retry count */
0133             (0xff << 8) |       /* timeout 1   */
0134             0xff);          /* timeout 0   */
0135
0136         /* enable PCI retry exceeded interrupt */
0137         GT_WRITE(GT_INTRMASK_OFS, GT_INTR_RETRYCTR0_MSK | GT_READ(GT_INTRMASK_OFS));
0138     }
0139 }
0140
0141 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111,
0142      qube_raq_galileo_fixup);
0143
0144 int cobalt_board_id;
0145
0146 static void qube_raq_via_board_id_fixup(struct pci_dev *dev)
0147 {
0148     u8 id;
0149     int retval;
0150
0151     retval = pci_read_config_byte(dev, VIA_COBALT_BRD_ID_REG, &id);
0152     if (retval) {
0153         panic("Cannot read board ID");
0154         return;
0155     }
0156
0157     cobalt_board_id = VIA_COBALT_BRD_REG_to_ID(id);
0158
0159     printk(KERN_INFO "Cobalt board ID: %d\n", cobalt_board_id);
0160 }
0161
0162 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0,
0163      qube_raq_via_board_id_fixup);
0164
0165 static char irq_tab_qube1[] = {
0166   [COBALT_PCICONF_CPU]     = 0,
0167   [COBALT_PCICONF_ETH0]    = QUBE1_ETH0_IRQ,
0168   [COBALT_PCICONF_RAQSCSI] = SCSI_IRQ,
0169   [COBALT_PCICONF_VIA]     = 0,
0170   [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ,
0171   [COBALT_PCICONF_ETH1]    = 0
0172 };
0173
0174 static char irq_tab_cobalt[] = {
0175   [COBALT_PCICONF_CPU]     = 0,
0176   [COBALT_PCICONF_ETH0]    = ETH0_IRQ,
0177   [COBALT_PCICONF_RAQSCSI] = SCSI_IRQ,
0178   [COBALT_PCICONF_VIA]     = 0,
0179   [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ,
0180   [COBALT_PCICONF_ETH1]    = ETH1_IRQ
0181 };
0182
0183 static char irq_tab_raq2[] = {
0184   [COBALT_PCICONF_CPU]     = 0,
0185   [COBALT_PCICONF_ETH0]    = ETH0_IRQ,
0186   [COBALT_PCICONF_RAQSCSI] = RAQ2_SCSI_IRQ,
0187   [COBALT_PCICONF_VIA]     = 0,
0188   [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ,
0189   [COBALT_PCICONF_ETH1]    = ETH1_IRQ
0190 };
0191
0192 int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
0193 {
0194     if (cobalt_board_id <= COBALT_BRD_ID_QUBE1)
0195         return irq_tab_qube1[slot];
0196
0197     if (cobalt_board_id == COBALT_BRD_ID_RAQ2)
0198         return irq_tab_raq2[slot];
0199
0200     return irq_tab_cobalt[slot];
0201 }
0202
0203 /* Do platform specific device initialization at pci_enable_device() time */
0204 int pcibios_plat_dev_init(struct pci_dev *dev)
0205 {
0206     return 0;
0207 }