mips/mti-malta/malta-time.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Carsten Langgaard, carstenl@mips.com
0004  * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
0005  *
0006  * Setting up the clock on the MIPS boards.
0007  */
0008 #include <linux/types.h>
0009 #include <linux/i8253.h>
0010 #include <linux/init.h>
0011 #include <linux/kernel_stat.h>
0012 #include <linux/libfdt.h>
0013 #include <linux/math64.h>
0014 #include <linux/sched.h>
0015 #include <linux/spinlock.h>
0016 #include <linux/interrupt.h>
0017 #include <linux/timex.h>
0018 #include <linux/mc146818rtc.h>
0019
0020 #include <asm/cpu.h>
0021 #include <asm/mipsregs.h>
0022 #include <asm/mipsmtregs.h>
0023 #include <asm/hardirq.h>
0024 #include <asm/irq.h>
0025 #include <asm/div64.h>
0026 #include <asm/setup.h>
0027 #include <asm/time.h>
0028 #include <asm/mc146818-time.h>
0029 #include <asm/msc01_ic.h>
0030 #include <asm/mips-cps.h>
0031
0032 #include <asm/mips-boards/generic.h>
0033 #include <asm/mips-boards/maltaint.h>
0034
0035 static int mips_cpu_timer_irq;
0036 static int mips_cpu_perf_irq;
0037 extern int cp0_perfcount_irq;
0038
0039 static unsigned int gic_frequency;
0040
0041 static void mips_timer_dispatch(void)
0042 {
0043     do_IRQ(mips_cpu_timer_irq);
0044 }
0045
0046 static void mips_perf_dispatch(void)
0047 {
0048     do_IRQ(mips_cpu_perf_irq);
0049 }
0050
0051 static unsigned int freqround(unsigned int freq, unsigned int amount)
0052 {
0053     freq += amount;
0054     freq -= freq % (amount*2);
0055     return freq;
0056 }
0057
0058 /*
0059  * Estimate CPU and GIC frequencies.
0060  */
0061 static void __init estimate_frequencies(void)
0062 {
0063     unsigned long flags;
0064     unsigned int count, start;
0065     unsigned char secs1, secs2, ctrl;
0066     int secs;
0067     u64 giccount = 0, gicstart = 0;
0068
0069     local_irq_save(flags);
0070
0071     if (mips_gic_present())
0072         clear_gic_config(GIC_CONFIG_COUNTSTOP);
0073
0074     /*
0075      * Read counters exactly on rising edge of update flag.
0076      * This helps get an accurate reading under virtualisation.
0077      */
0078     while (CMOS_READ(RTC_REG_A) & RTC_UIP);
0079     while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
0080     start = read_c0_count();
0081     if (mips_gic_present())
0082         gicstart = read_gic_counter();
0083
0084     /* Wait for falling edge before reading RTC. */
0085     while (CMOS_READ(RTC_REG_A) & RTC_UIP);
0086     secs1 = CMOS_READ(RTC_SECONDS);
0087
0088     /* Read counters again exactly on rising edge of update flag. */
0089     while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
0090     count = read_c0_count();
0091     if (mips_gic_present())
0092         giccount = read_gic_counter();
0093
0094     /* Wait for falling edge before reading RTC again. */
0095     while (CMOS_READ(RTC_REG_A) & RTC_UIP);
0096     secs2 = CMOS_READ(RTC_SECONDS);
0097
0098     ctrl = CMOS_READ(RTC_CONTROL);
0099
0100     local_irq_restore(flags);
0101
0102     if (!(ctrl & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
0103         secs1 = bcd2bin(secs1);
0104         secs2 = bcd2bin(secs2);
0105     }
0106     secs = secs2 - secs1;
0107     if (secs < 1)
0108         secs += 60;
0109
0110     count -= start;
0111     count /= secs;
0112     mips_hpt_frequency = count;
0113
0114     if (mips_gic_present()) {
0115         giccount = div_u64(giccount - gicstart, secs);
0116         gic_frequency = giccount;
0117     }
0118 }
0119
0120 void read_persistent_clock64(struct timespec64 *ts)
0121 {
0122     ts->tv_sec = mc146818_get_cmos_time();
0123     ts->tv_nsec = 0;
0124 }
0125
0126 int get_c0_fdc_int(void)
0127 {
0128     /*
0129      * Some cores claim the FDC is routable through the GIC, but it doesn't
0130      * actually seem to be connected for those Malta bitstreams.
0131      */
0132     switch (current_cpu_type()) {
0133     case CPU_INTERAPTIV:
0134     case CPU_PROAPTIV:
0135         return -1;
0136     }
0137
0138     if (cpu_has_veic)
0139         return -1;
0140     else if (mips_gic_present())
0141         return gic_get_c0_fdc_int();
0142     else if (cp0_fdc_irq >= 0)
0143         return MIPS_CPU_IRQ_BASE + cp0_fdc_irq;
0144     else
0145         return -1;
0146 }
0147
0148 int get_c0_perfcount_int(void)
0149 {
0150     if (cpu_has_veic) {
0151         set_vi_handler(MSC01E_INT_PERFCTR, mips_perf_dispatch);
0152         mips_cpu_perf_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR;
0153     } else if (mips_gic_present()) {
0154         mips_cpu_perf_irq = gic_get_c0_perfcount_int();
0155     } else if (cp0_perfcount_irq >= 0) {
0156         mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
0157     } else {
0158         mips_cpu_perf_irq = -1;
0159     }
0160
0161     return mips_cpu_perf_irq;
0162 }
0163 EXPORT_SYMBOL_GPL(get_c0_perfcount_int);
0164
0165 unsigned int get_c0_compare_int(void)
0166 {
0167     if (cpu_has_veic) {
0168         set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch);
0169         mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;
0170     } else if (mips_gic_present()) {
0171         mips_cpu_timer_irq = gic_get_c0_compare_int();
0172     } else {
0173         mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
0174     }
0175
0176     return mips_cpu_timer_irq;
0177 }
0178
0179 static void __init init_rtc(void)
0180 {
0181     unsigned char freq, ctrl;
0182
0183     /* Set 32KHz time base if not already set */
0184     freq = CMOS_READ(RTC_FREQ_SELECT);
0185     if ((freq & RTC_DIV_CTL) != RTC_REF_CLCK_32KHZ)
0186         CMOS_WRITE(RTC_REF_CLCK_32KHZ, RTC_FREQ_SELECT);
0187
0188     /* Ensure SET bit is clear so RTC can run */
0189     ctrl = CMOS_READ(RTC_CONTROL);
0190     if (ctrl & RTC_SET)
0191         CMOS_WRITE(ctrl & ~RTC_SET, RTC_CONTROL);
0192 }
0193
0194 #ifdef CONFIG_CLKSRC_MIPS_GIC
0195 static u32 gic_frequency_dt;
0196
0197 static struct property gic_frequency_prop = {
0198     .name = "clock-frequency",
0199     .length = sizeof(u32),
0200     .value = &gic_frequency_dt,
0201 };
0202
0203 static void update_gic_frequency_dt(void)
0204 {
0205     struct device_node *node;
0206
0207     gic_frequency_dt = cpu_to_be32(gic_frequency);
0208
0209     node = of_find_compatible_node(NULL, NULL, "mti,gic-timer");
0210     if (!node) {
0211         pr_err("mti,gic-timer device node not found\n");
0212         return;
0213     }
0214
0215     if (of_update_property(node, &gic_frequency_prop) < 0)
0216         pr_err("error updating gic frequency property\n");
0217
0218     of_node_put(node);
0219 }
0220
0221 #endif
0222
0223 void __init plat_time_init(void)
0224 {
0225     unsigned int prid = read_c0_prid() & (PRID_COMP_MASK | PRID_IMP_MASK);
0226     unsigned int freq;
0227
0228     init_rtc();
0229     estimate_frequencies();
0230
0231     freq = mips_hpt_frequency;
0232     if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) &&
0233         (prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
0234         freq *= 2;
0235     freq = freqround(freq, 5000);
0236     printk("CPU frequency %d.%02d MHz\n", freq/1000000,
0237            (freq%1000000)*100/1000000);
0238
0239 #ifdef CONFIG_I8253
0240     /* Only Malta has a PIT. */
0241     setup_pit_timer();
0242 #endif
0243
0244     if (mips_gic_present()) {
0245         freq = freqround(gic_frequency, 5000);
0246         printk("GIC frequency %d.%02d MHz\n", freq/1000000,
0247                (freq%1000000)*100/1000000);
0248 #ifdef CONFIG_CLKSRC_MIPS_GIC
0249         update_gic_frequency_dt();
0250         timer_probe();
0251 #endif
0252     }
0253 }