mips/mti-malta/malta-setup.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Carsten Langgaard, carstenl@mips.com
0004  * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
0005  * Copyright (C) 2008 Dmitri Vorobiev
0006  */
0007 #include <linux/cpu.h>
0008 #include <linux/init.h>
0009 #include <linux/sched.h>
0010 #include <linux/ioport.h>
0011 #include <linux/irq.h>
0012 #include <linux/of_fdt.h>
0013 #include <linux/pci.h>
0014 #include <linux/screen_info.h>
0015 #include <linux/time.h>
0016 #include <linux/dma-map-ops.h> /* for dma_default_coherent */
0017
0018 #include <asm/fw/fw.h>
0019 #include <asm/mips-cps.h>
0020 #include <asm/mips-boards/generic.h>
0021 #include <asm/mips-boards/malta.h>
0022 #include <asm/mips-boards/maltaint.h>
0023 #include <asm/dma.h>
0024 #include <asm/prom.h>
0025 #include <asm/traps.h>
0026 #ifdef CONFIG_VT
0027 #include <linux/console.h>
0028 #endif
0029
0030 #define ROCIT_CONFIG_GEN0       0x1f403000
0031 #define  ROCIT_CONFIG_GEN0_PCI_IOCU BIT(7)
0032
0033 static struct resource standard_io_resources[] = {
0034     {
0035         .name = "dma1",
0036         .start = 0x00,
0037         .end = 0x1f,
0038         .flags = IORESOURCE_IO | IORESOURCE_BUSY
0039     },
0040     {
0041         .name = "timer",
0042         .start = 0x40,
0043         .end = 0x5f,
0044         .flags = IORESOURCE_IO | IORESOURCE_BUSY
0045     },
0046     {
0047         .name = "keyboard",
0048         .start = 0x60,
0049         .end = 0x6f,
0050         .flags = IORESOURCE_IO | IORESOURCE_BUSY
0051     },
0052     {
0053         .name = "dma page reg",
0054         .start = 0x80,
0055         .end = 0x8f,
0056         .flags = IORESOURCE_IO | IORESOURCE_BUSY
0057     },
0058     {
0059         .name = "dma2",
0060         .start = 0xc0,
0061         .end = 0xdf,
0062         .flags = IORESOURCE_IO | IORESOURCE_BUSY
0063     },
0064 };
0065
0066 const char *get_system_type(void)
0067 {
0068     return "MIPS Malta";
0069 }
0070
0071 #ifdef CONFIG_BLK_DEV_FD
0072 static void __init fd_activate(void)
0073 {
0074     /*
0075      * Activate Floppy Controller in the SMSC FDC37M817 Super I/O
0076      * Controller.
0077      * Done by YAMON 2.00 onwards
0078      */
0079     /* Entering config state. */
0080     SMSC_WRITE(SMSC_CONFIG_ENTER, SMSC_CONFIG_REG);
0081
0082     /* Activate floppy controller. */
0083     SMSC_WRITE(SMSC_CONFIG_DEVNUM, SMSC_CONFIG_REG);
0084     SMSC_WRITE(SMSC_CONFIG_DEVNUM_FLOPPY, SMSC_DATA_REG);
0085     SMSC_WRITE(SMSC_CONFIG_ACTIVATE, SMSC_CONFIG_REG);
0086     SMSC_WRITE(SMSC_CONFIG_ACTIVATE_ENABLE, SMSC_DATA_REG);
0087
0088     /* Exit config state. */
0089     SMSC_WRITE(SMSC_CONFIG_EXIT, SMSC_CONFIG_REG);
0090 }
0091 #endif
0092
0093 static void __init plat_setup_iocoherency(void)
0094 {
0095     u32 cfg;
0096
0097     if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) {
0098         if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) {
0099             BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN;
0100             pr_info("Enabled Bonito CPU coherency\n");
0101             dma_default_coherent = true;
0102         }
0103         if (strstr(fw_getcmdline(), "iobcuncached")) {
0104             BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN;
0105             BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &
0106                 ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
0107                   BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
0108             pr_info("Disabled Bonito IOBC coherency\n");
0109         } else {
0110             BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN;
0111             BONITO_PCIMEMBASECFG |=
0112                 (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
0113                  BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
0114             pr_info("Enabled Bonito IOBC coherency\n");
0115         }
0116     } else if (mips_cps_numiocu(0) != 0) {
0117         /* Nothing special needs to be done to enable coherency */
0118         pr_info("CMP IOCU detected\n");
0119         cfg = __raw_readl((u32 *)CKSEG1ADDR(ROCIT_CONFIG_GEN0));
0120         if (cfg & ROCIT_CONFIG_GEN0_PCI_IOCU)
0121             dma_default_coherent = true;
0122         else
0123             pr_crit("IOCU OPERATION DISABLED BY SWITCH - DEFAULTING TO SW IO COHERENCY\n");
0124     }
0125
0126     if (dma_default_coherent)
0127         pr_info("Hardware DMA cache coherency enabled\n");
0128     else
0129         pr_info("Software DMA cache coherency enabled\n");
0130 }
0131
0132 static void __init pci_clock_check(void)
0133 {
0134     unsigned int __iomem *jmpr_p =
0135         (unsigned int *) ioremap(MALTA_JMPRS_REG, sizeof(unsigned int));
0136     int jmpr = (__raw_readl(jmpr_p) >> 2) & 0x07;
0137     static const int pciclocks[] __initconst = {
0138         33, 20, 25, 30, 12, 16, 37, 10
0139     };
0140     int pciclock = pciclocks[jmpr];
0141     char *optptr, *argptr = fw_getcmdline();
0142
0143     /*
0144      * If user passed a pci_clock= option, don't tack on another one
0145      */
0146     optptr = strstr(argptr, "pci_clock=");
0147     if (optptr && (optptr == argptr || optptr[-1] == ' '))
0148         return;
0149
0150     if (pciclock != 33) {
0151         pr_warn("WARNING: PCI clock is %dMHz, setting pci_clock\n",
0152             pciclock);
0153         argptr += strlen(argptr);
0154         sprintf(argptr, " pci_clock=%d", pciclock);
0155         if (pciclock < 20 || pciclock > 66)
0156             pr_warn("WARNING: IDE timing calculations will be "
0157                     "incorrect\n");
0158     }
0159 }
0160
0161 #if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE)
0162 static void __init screen_info_setup(void)
0163 {
0164     screen_info = (struct screen_info) {
0165         .orig_x = 0,
0166         .orig_y = 25,
0167         .ext_mem_k = 0,
0168         .orig_video_page = 0,
0169         .orig_video_mode = 0,
0170         .orig_video_cols = 80,
0171         .unused2 = 0,
0172         .orig_video_ega_bx = 0,
0173         .unused3 = 0,
0174         .orig_video_lines = 25,
0175         .orig_video_isVGA = VIDEO_TYPE_VGAC,
0176         .orig_video_points = 16
0177     };
0178 }
0179 #endif
0180
0181 static void __init bonito_quirks_setup(void)
0182 {
0183     char *argptr;
0184
0185     argptr = fw_getcmdline();
0186     if (strstr(argptr, "debug")) {
0187         BONITO_BONGENCFG |= BONITO_BONGENCFG_DEBUGMODE;
0188         pr_info("Enabled Bonito debug mode\n");
0189     } else
0190         BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE;
0191 }
0192
0193 void __init *plat_get_fdt(void)
0194 {
0195     return (void *)__dtb_start;
0196 }
0197
0198 void __init plat_mem_setup(void)
0199 {
0200     unsigned int i;
0201     void *fdt = plat_get_fdt();
0202
0203     fdt = malta_dt_shim(fdt);
0204     __dt_setup_arch(fdt);
0205
0206     if (IS_ENABLED(CONFIG_EVA))
0207         /* EVA has already been configured in mach-malta/kernel-init.h */
0208         pr_info("Enhanced Virtual Addressing (EVA) activated\n");
0209
0210     mips_pcibios_init();
0211
0212     /* Request I/O space for devices used on the Malta board. */
0213     for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
0214         request_resource(&ioport_resource, standard_io_resources+i);
0215
0216     /*
0217      * Enable DMA channel 4 (cascade channel) in the PIIX4 south bridge.
0218      */
0219     enable_dma(4);
0220
0221     if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO)
0222         bonito_quirks_setup();
0223
0224     plat_setup_iocoherency();
0225
0226     pci_clock_check();
0227
0228 #ifdef CONFIG_BLK_DEV_FD
0229     fd_activate();
0230 #endif
0231
0232 #if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE)
0233     screen_info_setup();
0234 #endif
0235 }