mips/mm/uasm.c

0001 /*
0002  * This file is subject to the terms and conditions of the GNU General Public
0003  * License.  See the file "COPYING" in the main directory of this archive
0004  * for more details.
0005  *
0006  * A small micro-assembler. It is intentionally kept simple, does only
0007  * support a subset of instructions, and does not try to hide pipeline
0008  * effects like branch delay slots.
0009  *
0010  * Copyright (C) 2004, 2005, 2006, 2008  Thiemo Seufer
0011  * Copyright (C) 2005, 2007  Maciej W. Rozycki
0012  * Copyright (C) 2006  Ralf Baechle (ralf@linux-mips.org)
0013  * Copyright (C) 2012, 2013  MIPS Technologies, Inc.  All rights reserved.
0014  */
0015
0016 enum fields {
0017     RS = 0x001,
0018     RT = 0x002,
0019     RD = 0x004,
0020     RE = 0x008,
0021     SIMM = 0x010,
0022     UIMM = 0x020,
0023     BIMM = 0x040,
0024     JIMM = 0x080,
0025     FUNC = 0x100,
0026     SET = 0x200,
0027     SCIMM = 0x400,
0028     SIMM9 = 0x800,
0029 };
0030
0031 #define OP_MASK     0x3f
0032 #define OP_SH       26
0033 #define RD_MASK     0x1f
0034 #define RD_SH       11
0035 #define RE_MASK     0x1f
0036 #define RE_SH       6
0037 #define IMM_MASK    0xffff
0038 #define IMM_SH      0
0039 #define JIMM_MASK   0x3ffffff
0040 #define JIMM_SH     0
0041 #define FUNC_MASK   0x3f
0042 #define FUNC_SH     0
0043 #define SET_MASK    0x7
0044 #define SET_SH      0
0045 #define SIMM9_SH    7
0046 #define SIMM9_MASK  0x1ff
0047
0048 enum opcode {
0049     insn_addiu, insn_addu, insn_and, insn_andi, insn_bbit0, insn_bbit1,
0050     insn_beq, insn_beql, insn_bgez, insn_bgezl, insn_bgtz, insn_blez,
0051     insn_bltz, insn_bltzl, insn_bne, insn_break, insn_cache, insn_cfc1,
0052     insn_cfcmsa, insn_ctc1, insn_ctcmsa, insn_daddiu, insn_daddu, insn_ddivu,
0053     insn_ddivu_r6, insn_di, insn_dins, insn_dinsm, insn_dinsu, insn_divu,
0054     insn_divu_r6, insn_dmfc0, insn_dmodu, insn_dmtc0, insn_dmultu,
0055     insn_dmulu, insn_drotr, insn_drotr32, insn_dsbh, insn_dshd, insn_dsll,
0056     insn_dsll32, insn_dsllv, insn_dsra, insn_dsra32, insn_dsrav, insn_dsrl,
0057     insn_dsrl32, insn_dsrlv, insn_dsubu, insn_eret, insn_ext, insn_ins,
0058     insn_j, insn_jal, insn_jalr, insn_jr, insn_lb, insn_lbu, insn_ld,
0059     insn_lddir, insn_ldpte, insn_ldx, insn_lh, insn_lhu, insn_ll, insn_lld,
0060     insn_lui, insn_lw, insn_lwu, insn_lwx, insn_mfc0, insn_mfhc0, insn_mfhi,
0061     insn_mflo, insn_modu, insn_movn, insn_movz, insn_mtc0, insn_mthc0,
0062     insn_mthi, insn_mtlo, insn_mul, insn_multu, insn_mulu, insn_muhu, insn_nor,
0063     insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sb, insn_sc,
0064     insn_scd, insn_seleqz, insn_selnez, insn_sd, insn_sh, insn_sll,
0065     insn_sllv, insn_slt, insn_slti, insn_sltiu, insn_sltu, insn_sra,
0066     insn_srav, insn_srl, insn_srlv, insn_subu, insn_sw, insn_sync,
0067     insn_syscall, insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_wait,
0068     insn_wsbh, insn_xor, insn_xori, insn_yield,
0069     insn_invalid /* insn_invalid must be last */
0070 };
0071
0072 struct insn {
0073     u32 match;
0074     enum fields fields;
0075 };
0076
0077 static inline u32 build_rs(u32 arg)
0078 {
0079     WARN(arg & ~RS_MASK, KERN_WARNING "Micro-assembler field overflow\n");
0080
0081     return (arg & RS_MASK) << RS_SH;
0082 }
0083
0084 static inline u32 build_rt(u32 arg)
0085 {
0086     WARN(arg & ~RT_MASK, KERN_WARNING "Micro-assembler field overflow\n");
0087
0088     return (arg & RT_MASK) << RT_SH;
0089 }
0090
0091 static inline u32 build_rd(u32 arg)
0092 {
0093     WARN(arg & ~RD_MASK, KERN_WARNING "Micro-assembler field overflow\n");
0094
0095     return (arg & RD_MASK) << RD_SH;
0096 }
0097
0098 static inline u32 build_re(u32 arg)
0099 {
0100     WARN(arg & ~RE_MASK, KERN_WARNING "Micro-assembler field overflow\n");
0101
0102     return (arg & RE_MASK) << RE_SH;
0103 }
0104
0105 static inline u32 build_simm(s32 arg)
0106 {
0107     WARN(arg > 0x7fff || arg < -0x8000,
0108          KERN_WARNING "Micro-assembler field overflow\n");
0109
0110     return arg & 0xffff;
0111 }
0112
0113 static inline u32 build_uimm(u32 arg)
0114 {
0115     WARN(arg & ~IMM_MASK, KERN_WARNING "Micro-assembler field overflow\n");
0116
0117     return arg & IMM_MASK;
0118 }
0119
0120 static inline u32 build_scimm(u32 arg)
0121 {
0122     WARN(arg & ~SCIMM_MASK,
0123          KERN_WARNING "Micro-assembler field overflow\n");
0124
0125     return (arg & SCIMM_MASK) << SCIMM_SH;
0126 }
0127
0128 static inline u32 build_scimm9(s32 arg)
0129 {
0130     WARN((arg > 0xff || arg < -0x100),
0131            KERN_WARNING "Micro-assembler field overflow\n");
0132
0133     return (arg & SIMM9_MASK) << SIMM9_SH;
0134 }
0135
0136 static inline u32 build_func(u32 arg)
0137 {
0138     WARN(arg & ~FUNC_MASK, KERN_WARNING "Micro-assembler field overflow\n");
0139
0140     return arg & FUNC_MASK;
0141 }
0142
0143 static inline u32 build_set(u32 arg)
0144 {
0145     WARN(arg & ~SET_MASK, KERN_WARNING "Micro-assembler field overflow\n");
0146
0147     return arg & SET_MASK;
0148 }
0149
0150 static void build_insn(u32 **buf, enum opcode opc, ...);
0151
0152 #define I_u1u2u3(op)                    \
0153 Ip_u1u2u3(op)                       \
0154 {                           \
0155     build_insn(buf, insn##op, a, b, c);     \
0156 }                           \
0157 UASM_EXPORT_SYMBOL(uasm_i##op);
0158
0159 #define I_s3s1s2(op)                    \
0160 Ip_s3s1s2(op)                       \
0161 {                           \
0162     build_insn(buf, insn##op, b, c, a);     \
0163 }                           \
0164 UASM_EXPORT_SYMBOL(uasm_i##op);
0165
0166 #define I_u2u1u3(op)                    \
0167 Ip_u2u1u3(op)                       \
0168 {                           \
0169     build_insn(buf, insn##op, b, a, c);     \
0170 }                           \
0171 UASM_EXPORT_SYMBOL(uasm_i##op);
0172
0173 #define I_u3u2u1(op)                    \
0174 Ip_u3u2u1(op)                       \
0175 {                           \
0176     build_insn(buf, insn##op, c, b, a);     \
0177 }                           \
0178 UASM_EXPORT_SYMBOL(uasm_i##op);
0179
0180 #define I_u3u1u2(op)                    \
0181 Ip_u3u1u2(op)                       \
0182 {                           \
0183     build_insn(buf, insn##op, b, c, a);     \
0184 }                           \
0185 UASM_EXPORT_SYMBOL(uasm_i##op);
0186
0187 #define I_u1u2s3(op)                    \
0188 Ip_u1u2s3(op)                       \
0189 {                           \
0190     build_insn(buf, insn##op, a, b, c);     \
0191 }                           \
0192 UASM_EXPORT_SYMBOL(uasm_i##op);
0193
0194 #define I_u2s3u1(op)                    \
0195 Ip_u2s3u1(op)                       \
0196 {                           \
0197     build_insn(buf, insn##op, c, a, b);     \
0198 }                           \
0199 UASM_EXPORT_SYMBOL(uasm_i##op);
0200
0201 #define I_u2u1s3(op)                    \
0202 Ip_u2u1s3(op)                       \
0203 {                           \
0204     build_insn(buf, insn##op, b, a, c);     \
0205 }                           \
0206 UASM_EXPORT_SYMBOL(uasm_i##op);
0207
0208 #define I_u2u1msbu3(op)                 \
0209 Ip_u2u1msbu3(op)                    \
0210 {                           \
0211     build_insn(buf, insn##op, b, a, c+d-1, c);  \
0212 }                           \
0213 UASM_EXPORT_SYMBOL(uasm_i##op);
0214
0215 #define I_u2u1msb32u3(op)               \
0216 Ip_u2u1msbu3(op)                    \
0217 {                           \
0218     build_insn(buf, insn##op, b, a, c+d-33, c); \
0219 }                           \
0220 UASM_EXPORT_SYMBOL(uasm_i##op);
0221
0222 #define I_u2u1msb32msb3(op)             \
0223 Ip_u2u1msbu3(op)                    \
0224 {                           \
0225     build_insn(buf, insn##op, b, a, c+d-33, c-32);  \
0226 }                           \
0227 UASM_EXPORT_SYMBOL(uasm_i##op);
0228
0229 #define I_u2u1msbdu3(op)                \
0230 Ip_u2u1msbu3(op)                    \
0231 {                           \
0232     build_insn(buf, insn##op, b, a, d-1, c);    \
0233 }                           \
0234 UASM_EXPORT_SYMBOL(uasm_i##op);
0235
0236 #define I_u1u2(op)                  \
0237 Ip_u1u2(op)                     \
0238 {                           \
0239     build_insn(buf, insn##op, a, b);        \
0240 }                           \
0241 UASM_EXPORT_SYMBOL(uasm_i##op);
0242
0243 #define I_u2u1(op)                  \
0244 Ip_u1u2(op)                     \
0245 {                           \
0246     build_insn(buf, insn##op, b, a);        \
0247 }                           \
0248 UASM_EXPORT_SYMBOL(uasm_i##op);
0249
0250 #define I_u1s2(op)                  \
0251 Ip_u1s2(op)                     \
0252 {                           \
0253     build_insn(buf, insn##op, a, b);        \
0254 }                           \
0255 UASM_EXPORT_SYMBOL(uasm_i##op);
0256
0257 #define I_u1(op)                    \
0258 Ip_u1(op)                       \
0259 {                           \
0260     build_insn(buf, insn##op, a);           \
0261 }                           \
0262 UASM_EXPORT_SYMBOL(uasm_i##op);
0263
0264 #define I_0(op)                     \
0265 Ip_0(op)                        \
0266 {                           \
0267     build_insn(buf, insn##op);          \
0268 }                           \
0269 UASM_EXPORT_SYMBOL(uasm_i##op);
0270
0271 I_u2u1s3(_addiu)
0272 I_u3u1u2(_addu)
0273 I_u2u1u3(_andi)
0274 I_u3u1u2(_and)
0275 I_u1u2s3(_beq)
0276 I_u1u2s3(_beql)
0277 I_u1s2(_bgez)
0278 I_u1s2(_bgezl)
0279 I_u1s2(_bgtz)
0280 I_u1s2(_blez)
0281 I_u1s2(_bltz)
0282 I_u1s2(_bltzl)
0283 I_u1u2s3(_bne)
0284 I_u1(_break)
0285 I_u2s3u1(_cache)
0286 I_u1u2(_cfc1)
0287 I_u2u1(_cfcmsa)
0288 I_u1u2(_ctc1)
0289 I_u2u1(_ctcmsa)
0290 I_u1u2(_ddivu)
0291 I_u3u1u2(_ddivu_r6)
0292 I_u1u2u3(_dmfc0)
0293 I_u3u1u2(_dmodu)
0294 I_u1u2u3(_dmtc0)
0295 I_u1u2(_dmultu)
0296 I_u3u1u2(_dmulu)
0297 I_u2u1s3(_daddiu)
0298 I_u3u1u2(_daddu)
0299 I_u1(_di);
0300 I_u1u2(_divu)
0301 I_u3u1u2(_divu_r6)
0302 I_u2u1(_dsbh);
0303 I_u2u1(_dshd);
0304 I_u2u1u3(_dsll)
0305 I_u2u1u3(_dsll32)
0306 I_u3u2u1(_dsllv)
0307 I_u2u1u3(_dsra)
0308 I_u2u1u3(_dsra32)
0309 I_u3u2u1(_dsrav)
0310 I_u2u1u3(_dsrl)
0311 I_u2u1u3(_dsrl32)
0312 I_u3u2u1(_dsrlv)
0313 I_u2u1u3(_drotr)
0314 I_u2u1u3(_drotr32)
0315 I_u3u1u2(_dsubu)
0316 I_0(_eret)
0317 I_u2u1msbdu3(_ext)
0318 I_u2u1msbu3(_ins)
0319 I_u1(_j)
0320 I_u1(_jal)
0321 I_u2u1(_jalr)
0322 I_u1(_jr)
0323 I_u2s3u1(_lb)
0324 I_u2s3u1(_lbu)
0325 I_u2s3u1(_ld)
0326 I_u2s3u1(_lh)
0327 I_u2s3u1(_lhu)
0328 I_u2s3u1(_ll)
0329 I_u2s3u1(_lld)
0330 I_u1s2(_lui)
0331 I_u2s3u1(_lw)
0332 I_u2s3u1(_lwu)
0333 I_u1u2u3(_mfc0)
0334 I_u1u2u3(_mfhc0)
0335 I_u3u1u2(_modu)
0336 I_u3u1u2(_movn)
0337 I_u3u1u2(_movz)
0338 I_u1(_mfhi)
0339 I_u1(_mflo)
0340 I_u1u2u3(_mtc0)
0341 I_u1u2u3(_mthc0)
0342 I_u1(_mthi)
0343 I_u1(_mtlo)
0344 I_u3u1u2(_mul)
0345 I_u1u2(_multu)
0346 I_u3u1u2(_mulu)
0347 I_u3u1u2(_muhu)
0348 I_u3u1u2(_nor)
0349 I_u3u1u2(_or)
0350 I_u2u1u3(_ori)
0351 I_0(_rfe)
0352 I_u2s3u1(_sb)
0353 I_u2s3u1(_sc)
0354 I_u2s3u1(_scd)
0355 I_u2s3u1(_sd)
0356 I_u3u1u2(_seleqz)
0357 I_u3u1u2(_selnez)
0358 I_u2s3u1(_sh)
0359 I_u2u1u3(_sll)
0360 I_u3u2u1(_sllv)
0361 I_s3s1s2(_slt)
0362 I_u2u1s3(_slti)
0363 I_u2u1s3(_sltiu)
0364 I_u3u1u2(_sltu)
0365 I_u2u1u3(_sra)
0366 I_u3u2u1(_srav)
0367 I_u2u1u3(_srl)
0368 I_u3u2u1(_srlv)
0369 I_u2u1u3(_rotr)
0370 I_u3u1u2(_subu)
0371 I_u2s3u1(_sw)
0372 I_u1(_sync)
0373 I_0(_tlbp)
0374 I_0(_tlbr)
0375 I_0(_tlbwi)
0376 I_0(_tlbwr)
0377 I_u1(_wait);
0378 I_u2u1(_wsbh)
0379 I_u3u1u2(_xor)
0380 I_u2u1u3(_xori)
0381 I_u2u1(_yield)
0382 I_u2u1msbu3(_dins);
0383 I_u2u1msb32u3(_dinsm);
0384 I_u2u1msb32msb3(_dinsu);
0385 I_u1(_syscall);
0386 I_u1u2s3(_bbit0);
0387 I_u1u2s3(_bbit1);
0388 I_u3u1u2(_lwx)
0389 I_u3u1u2(_ldx)
0390 I_u1u2(_ldpte)
0391 I_u2u1u3(_lddir)
0392
0393 #ifdef CONFIG_CPU_CAVIUM_OCTEON
0394 #include <asm/octeon/octeon.h>
0395 void uasm_i_pref(u32 **buf, unsigned int a, signed int b,
0396                 unsigned int c)
0397 {
0398     if (OCTEON_IS_MODEL(OCTEON_CN6XXX) && a <= 24 && a != 5)
0399         /*
0400          * As per erratum Core-14449, replace prefetches 0-4,
0401          * 6-24 with 'pref 28'.
0402          */
0403         build_insn(buf, insn_pref, c, 28, b);
0404     else
0405         build_insn(buf, insn_pref, c, a, b);
0406 }
0407 UASM_EXPORT_SYMBOL(uasm_i_pref);
0408 #else
0409 I_u2s3u1(_pref)
0410 #endif
0411
0412 /* Handle labels. */
0413 void uasm_build_label(struct uasm_label **lab, u32 *addr, int lid)
0414 {
0415     (*lab)->addr = addr;
0416     (*lab)->lab = lid;
0417     (*lab)++;
0418 }
0419 UASM_EXPORT_SYMBOL(uasm_build_label);
0420
0421 int uasm_in_compat_space_p(long addr)
0422 {
0423     /* Is this address in 32bit compat space? */
0424     return addr == (int)addr;
0425 }
0426 UASM_EXPORT_SYMBOL(uasm_in_compat_space_p);
0427
0428 static int uasm_rel_highest(long val)
0429 {
0430 #ifdef CONFIG_64BIT
0431     return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000;
0432 #else
0433     return 0;
0434 #endif
0435 }
0436
0437 static int uasm_rel_higher(long val)
0438 {
0439 #ifdef CONFIG_64BIT
0440     return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000;
0441 #else
0442     return 0;
0443 #endif
0444 }
0445
0446 int uasm_rel_hi(long val)
0447 {
0448     return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000;
0449 }
0450 UASM_EXPORT_SYMBOL(uasm_rel_hi);
0451
0452 int uasm_rel_lo(long val)
0453 {
0454     return ((val & 0xffff) ^ 0x8000) - 0x8000;
0455 }
0456 UASM_EXPORT_SYMBOL(uasm_rel_lo);
0457
0458 void UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr)
0459 {
0460     if (!uasm_in_compat_space_p(addr)) {
0461         uasm_i_lui(buf, rs, uasm_rel_highest(addr));
0462         if (uasm_rel_higher(addr))
0463             uasm_i_daddiu(buf, rs, rs, uasm_rel_higher(addr));
0464         if (uasm_rel_hi(addr)) {
0465             uasm_i_dsll(buf, rs, rs, 16);
0466             uasm_i_daddiu(buf, rs, rs,
0467                     uasm_rel_hi(addr));
0468             uasm_i_dsll(buf, rs, rs, 16);
0469         } else
0470             uasm_i_dsll32(buf, rs, rs, 0);
0471     } else
0472         uasm_i_lui(buf, rs, uasm_rel_hi(addr));
0473 }
0474 UASM_EXPORT_SYMBOL(UASM_i_LA_mostly);
0475
0476 void UASM_i_LA(u32 **buf, unsigned int rs, long addr)
0477 {
0478     UASM_i_LA_mostly(buf, rs, addr);
0479     if (uasm_rel_lo(addr)) {
0480         if (!uasm_in_compat_space_p(addr))
0481             uasm_i_daddiu(buf, rs, rs,
0482                     uasm_rel_lo(addr));
0483         else
0484             uasm_i_addiu(buf, rs, rs,
0485                     uasm_rel_lo(addr));
0486     }
0487 }
0488 UASM_EXPORT_SYMBOL(UASM_i_LA);
0489
0490 /* Handle relocations. */
0491 void uasm_r_mips_pc16(struct uasm_reloc **rel, u32 *addr, int lid)
0492 {
0493     (*rel)->addr = addr;
0494     (*rel)->type = R_MIPS_PC16;
0495     (*rel)->lab = lid;
0496     (*rel)++;
0497 }
0498 UASM_EXPORT_SYMBOL(uasm_r_mips_pc16);
0499
0500 static inline void __resolve_relocs(struct uasm_reloc *rel,
0501                     struct uasm_label *lab);
0502
0503 void uasm_resolve_relocs(struct uasm_reloc *rel,
0504                   struct uasm_label *lab)
0505 {
0506     struct uasm_label *l;
0507
0508     for (; rel->lab != UASM_LABEL_INVALID; rel++)
0509         for (l = lab; l->lab != UASM_LABEL_INVALID; l++)
0510             if (rel->lab == l->lab)
0511                 __resolve_relocs(rel, l);
0512 }
0513 UASM_EXPORT_SYMBOL(uasm_resolve_relocs);
0514
0515 void uasm_move_relocs(struct uasm_reloc *rel, u32 *first, u32 *end,
0516                    long off)
0517 {
0518     for (; rel->lab != UASM_LABEL_INVALID; rel++)
0519         if (rel->addr >= first && rel->addr < end)
0520             rel->addr += off;
0521 }
0522 UASM_EXPORT_SYMBOL(uasm_move_relocs);
0523
0524 void uasm_move_labels(struct uasm_label *lab, u32 *first, u32 *end,
0525                    long off)
0526 {
0527     for (; lab->lab != UASM_LABEL_INVALID; lab++)
0528         if (lab->addr >= first && lab->addr < end)
0529             lab->addr += off;
0530 }
0531 UASM_EXPORT_SYMBOL(uasm_move_labels);
0532
0533 void uasm_copy_handler(struct uasm_reloc *rel, struct uasm_label *lab,
0534                 u32 *first, u32 *end, u32 *target)
0535 {
0536     long off = (long)(target - first);
0537
0538     memcpy(target, first, (end - first) * sizeof(u32));
0539
0540     uasm_move_relocs(rel, first, end, off);
0541     uasm_move_labels(lab, first, end, off);
0542 }
0543 UASM_EXPORT_SYMBOL(uasm_copy_handler);
0544
0545 int uasm_insn_has_bdelay(struct uasm_reloc *rel, u32 *addr)
0546 {
0547     for (; rel->lab != UASM_LABEL_INVALID; rel++) {
0548         if (rel->addr == addr
0549             && (rel->type == R_MIPS_PC16
0550             || rel->type == R_MIPS_26))
0551             return 1;
0552     }
0553
0554     return 0;
0555 }
0556 UASM_EXPORT_SYMBOL(uasm_insn_has_bdelay);
0557
0558 /* Convenience functions for labeled branches. */
0559 void uasm_il_bltz(u32 **p, struct uasm_reloc **r, unsigned int reg,
0560                int lid)
0561 {
0562     uasm_r_mips_pc16(r, *p, lid);
0563     uasm_i_bltz(p, reg, 0);
0564 }
0565 UASM_EXPORT_SYMBOL(uasm_il_bltz);
0566
0567 void uasm_il_b(u32 **p, struct uasm_reloc **r, int lid)
0568 {
0569     uasm_r_mips_pc16(r, *p, lid);
0570     uasm_i_b(p, 0);
0571 }
0572 UASM_EXPORT_SYMBOL(uasm_il_b);
0573
0574 void uasm_il_beq(u32 **p, struct uasm_reloc **r, unsigned int r1,
0575               unsigned int r2, int lid)
0576 {
0577     uasm_r_mips_pc16(r, *p, lid);
0578     uasm_i_beq(p, r1, r2, 0);
0579 }
0580 UASM_EXPORT_SYMBOL(uasm_il_beq);
0581
0582 void uasm_il_beqz(u32 **p, struct uasm_reloc **r, unsigned int reg,
0583                int lid)
0584 {
0585     uasm_r_mips_pc16(r, *p, lid);
0586     uasm_i_beqz(p, reg, 0);
0587 }
0588 UASM_EXPORT_SYMBOL(uasm_il_beqz);
0589
0590 void uasm_il_beqzl(u32 **p, struct uasm_reloc **r, unsigned int reg,
0591                 int lid)
0592 {
0593     uasm_r_mips_pc16(r, *p, lid);
0594     uasm_i_beqzl(p, reg, 0);
0595 }
0596 UASM_EXPORT_SYMBOL(uasm_il_beqzl);
0597
0598 void uasm_il_bne(u32 **p, struct uasm_reloc **r, unsigned int reg1,
0599               unsigned int reg2, int lid)
0600 {
0601     uasm_r_mips_pc16(r, *p, lid);
0602     uasm_i_bne(p, reg1, reg2, 0);
0603 }
0604 UASM_EXPORT_SYMBOL(uasm_il_bne);
0605
0606 void uasm_il_bnez(u32 **p, struct uasm_reloc **r, unsigned int reg,
0607                int lid)
0608 {
0609     uasm_r_mips_pc16(r, *p, lid);
0610     uasm_i_bnez(p, reg, 0);
0611 }
0612 UASM_EXPORT_SYMBOL(uasm_il_bnez);
0613
0614 void uasm_il_bgezl(u32 **p, struct uasm_reloc **r, unsigned int reg,
0615                 int lid)
0616 {
0617     uasm_r_mips_pc16(r, *p, lid);
0618     uasm_i_bgezl(p, reg, 0);
0619 }
0620 UASM_EXPORT_SYMBOL(uasm_il_bgezl);
0621
0622 void uasm_il_bgez(u32 **p, struct uasm_reloc **r, unsigned int reg,
0623                int lid)
0624 {
0625     uasm_r_mips_pc16(r, *p, lid);
0626     uasm_i_bgez(p, reg, 0);
0627 }
0628 UASM_EXPORT_SYMBOL(uasm_il_bgez);
0629
0630 void uasm_il_bbit0(u32 **p, struct uasm_reloc **r, unsigned int reg,
0631                 unsigned int bit, int lid)
0632 {
0633     uasm_r_mips_pc16(r, *p, lid);
0634     uasm_i_bbit0(p, reg, bit, 0);
0635 }
0636 UASM_EXPORT_SYMBOL(uasm_il_bbit0);
0637
0638 void uasm_il_bbit1(u32 **p, struct uasm_reloc **r, unsigned int reg,
0639                 unsigned int bit, int lid)
0640 {
0641     uasm_r_mips_pc16(r, *p, lid);
0642     uasm_i_bbit1(p, reg, bit, 0);
0643 }
0644 UASM_EXPORT_SYMBOL(uasm_il_bbit1);