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0001 /*
0002  * This file is subject to the terms and conditions of the GNU General Public
0003  * License.  See the file "COPYING" in the main directory of this archive
0004  * for more details.
0005  *
0006  * A small micro-assembler. It is intentionally kept simple, does only
0007  * support a subset of instructions, and does not try to hide pipeline
0008  * effects like branch delay slots.
0009  *
0010  * Copyright (C) 2004, 2005, 2006, 2008  Thiemo Seufer
0011  * Copyright (C) 2005, 2007  Maciej W. Rozycki
0012  * Copyright (C) 2006  Ralf Baechle (ralf@linux-mips.org)
0013  * Copyright (C) 2012, 2013  MIPS Technologies, Inc.  All rights reserved.
0014  */
0015 
0016 #include <linux/kernel.h>
0017 #include <linux/types.h>
0018 
0019 #include <asm/inst.h>
0020 #include <asm/elf.h>
0021 #include <asm/bugs.h>
0022 #include <asm/uasm.h>
0023 
0024 #define RS_MASK     0x1f
0025 #define RS_SH       21
0026 #define RT_MASK     0x1f
0027 #define RT_SH       16
0028 #define SCIMM_MASK  0xfffff
0029 #define SCIMM_SH    6
0030 
0031 /* This macro sets the non-variable bits of an instruction. */
0032 #define M(a, b, c, d, e, f)                 \
0033     ((a) << OP_SH                       \
0034      | (b) << RS_SH                     \
0035      | (c) << RT_SH                     \
0036      | (d) << RD_SH                     \
0037      | (e) << RE_SH                     \
0038      | (f) << FUNC_SH)
0039 
0040 /* This macro sets the non-variable bits of an R6 instruction. */
0041 #define M6(a, b, c, d, e)                   \
0042     ((a) << OP_SH                       \
0043      | (b) << RS_SH                     \
0044      | (c) << RT_SH                     \
0045      | (d) << SIMM9_SH                  \
0046      | (e) << FUNC_SH)
0047 
0048 #include "uasm.c"
0049 
0050 static const struct insn insn_table[insn_invalid] = {
0051     [insn_addiu]    = {M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
0052     [insn_addu] = {M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD},
0053     [insn_and]  = {M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD},
0054     [insn_andi] = {M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM},
0055     [insn_bbit0]    = {M(lwc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
0056     [insn_bbit1]    = {M(swc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
0057     [insn_beq]  = {M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
0058     [insn_beql] = {M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
0059     [insn_bgez] = {M(bcond_op, 0, bgez_op, 0, 0, 0), RS | BIMM},
0060     [insn_bgezl]    = {M(bcond_op, 0, bgezl_op, 0, 0, 0), RS | BIMM},
0061     [insn_bgtz] = {M(bgtz_op, 0, 0, 0, 0, 0), RS | BIMM},
0062     [insn_blez] = {M(blez_op, 0, 0, 0, 0, 0), RS | BIMM},
0063     [insn_bltz] = {M(bcond_op, 0, bltz_op, 0, 0, 0), RS | BIMM},
0064     [insn_bltzl]    = {M(bcond_op, 0, bltzl_op, 0, 0, 0), RS | BIMM},
0065     [insn_bne]  = {M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
0066     [insn_break]    = {M(spec_op, 0, 0, 0, 0, break_op), SCIMM},
0067 #ifndef CONFIG_CPU_MIPSR6
0068     [insn_cache]    = {M(cache_op, 0, 0, 0, 0, 0),  RS | RT | SIMM},
0069 #else
0070     [insn_cache]    = {M6(spec3_op, 0, 0, 0, cache6_op),  RS | RT | SIMM9},
0071 #endif
0072     [insn_cfc1] = {M(cop1_op, cfc_op, 0, 0, 0, 0), RT | RD},
0073     [insn_cfcmsa]   = {M(msa_op, 0, msa_cfc_op, 0, 0, msa_elm_op), RD | RE},
0074     [insn_ctc1] = {M(cop1_op, ctc_op, 0, 0, 0, 0), RT | RD},
0075     [insn_ctcmsa]   = {M(msa_op, 0, msa_ctc_op, 0, 0, msa_elm_op), RD | RE},
0076     [insn_daddiu]   = {M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
0077     [insn_daddu]    = {M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD},
0078     [insn_ddivu]    = {M(spec_op, 0, 0, 0, 0, ddivu_op), RS | RT},
0079     [insn_ddivu_r6] = {M(spec_op, 0, 0, 0, ddivu_ddivu6_op, ddivu_op),
0080                 RS | RT | RD},
0081     [insn_di]   = {M(cop0_op, mfmc0_op, 0, 12, 0, 0), RT},
0082     [insn_dins] = {M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE},
0083     [insn_dinsm]    = {M(spec3_op, 0, 0, 0, 0, dinsm_op), RS | RT | RD | RE},
0084     [insn_dinsu]    = {M(spec3_op, 0, 0, 0, 0, dinsu_op), RS | RT | RD | RE},
0085     [insn_divu] = {M(spec_op, 0, 0, 0, 0, divu_op), RS | RT},
0086     [insn_divu_r6]  = {M(spec_op, 0, 0, 0, divu_divu6_op, divu_op),
0087                 RS | RT | RD},
0088     [insn_dmfc0]    = {M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET},
0089     [insn_dmodu]    = {M(spec_op, 0, 0, 0, ddivu_dmodu_op, ddivu_op),
0090                 RS | RT | RD},
0091     [insn_dmtc0]    = {M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET},
0092     [insn_dmultu]   = {M(spec_op, 0, 0, 0, 0, dmultu_op), RS | RT},
0093     [insn_dmulu]    = {M(spec_op, 0, 0, 0, dmultu_dmulu_op, dmultu_op),
0094                 RS | RT | RD},
0095     [insn_drotr]    = {M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE},
0096     [insn_drotr32]  = {M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE},
0097     [insn_dsbh] = {M(spec3_op, 0, 0, 0, dsbh_op, dbshfl_op), RT | RD},
0098     [insn_dshd] = {M(spec3_op, 0, 0, 0, dshd_op, dbshfl_op), RT | RD},
0099     [insn_dsll] = {M(spec_op, 0, 0, 0, 0, dsll_op), RT | RD | RE},
0100     [insn_dsll32]   = {M(spec_op, 0, 0, 0, 0, dsll32_op), RT | RD | RE},
0101     [insn_dsllv]    = {M(spec_op, 0, 0, 0, 0, dsllv_op),  RS | RT | RD},
0102     [insn_dsra] = {M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE},
0103     [insn_dsra32]   = {M(spec_op, 0, 0, 0, 0, dsra32_op), RT | RD | RE},
0104     [insn_dsrav]    = {M(spec_op, 0, 0, 0, 0, dsrav_op),  RS | RT | RD},
0105     [insn_dsrl] = {M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE},
0106     [insn_dsrl32]   = {M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE},
0107     [insn_dsrlv]    = {M(spec_op, 0, 0, 0, 0, dsrlv_op),  RS | RT | RD},
0108     [insn_dsubu]    = {M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD},
0109     [insn_eret] = {M(cop0_op, cop_op, 0, 0, 0, eret_op),  0},
0110     [insn_ext]  = {M(spec3_op, 0, 0, 0, 0, ext_op), RS | RT | RD | RE},
0111     [insn_ins]  = {M(spec3_op, 0, 0, 0, 0, ins_op), RS | RT | RD | RE},
0112     [insn_j]    = {M(j_op, 0, 0, 0, 0, 0),  JIMM},
0113     [insn_jal]  = {M(jal_op, 0, 0, 0, 0, 0),    JIMM},
0114     [insn_jalr] = {M(spec_op, 0, 0, 0, 0, jalr_op), RS | RD},
0115 #ifndef CONFIG_CPU_MIPSR6
0116     [insn_jr]   = {M(spec_op, 0, 0, 0, 0, jr_op),  RS},
0117 #else
0118     [insn_jr]   = {M(spec_op, 0, 0, 0, 0, jalr_op),  RS},
0119 #endif
0120     [insn_lb]   = {M(lb_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
0121     [insn_lbu]  = {M(lbu_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
0122     [insn_ld]   = {M(ld_op, 0, 0, 0, 0, 0),  RS | RT | SIMM},
0123     [insn_lddir]    = {M(lwc2_op, 0, 0, 0, lddir_op, mult_op), RS | RT | RD},
0124     [insn_ldpte]    = {M(lwc2_op, 0, 0, 0, ldpte_op, mult_op), RS | RD},
0125     [insn_ldx]  = {M(spec3_op, 0, 0, 0, ldx_op, lx_op), RS | RT | RD},
0126     [insn_lh]   = {M(lh_op, 0, 0, 0, 0, 0),  RS | RT | SIMM},
0127     [insn_lhu]  = {M(lhu_op, 0, 0, 0, 0, 0),  RS | RT | SIMM},
0128 #ifndef CONFIG_CPU_MIPSR6
0129     [insn_ll]   = {M(ll_op, 0, 0, 0, 0, 0),  RS | RT | SIMM},
0130     [insn_lld]  = {M(lld_op, 0, 0, 0, 0, 0),    RS | RT | SIMM},
0131 #else
0132     [insn_ll]   = {M6(spec3_op, 0, 0, 0, ll6_op),  RS | RT | SIMM9},
0133     [insn_lld]  = {M6(spec3_op, 0, 0, 0, lld6_op),  RS | RT | SIMM9},
0134 #endif
0135     [insn_lui]  = {M(lui_op, 0, 0, 0, 0, 0),    RT | SIMM},
0136     [insn_lw]   = {M(lw_op, 0, 0, 0, 0, 0),  RS | RT | SIMM},
0137     [insn_lwu]  = {M(lwu_op, 0, 0, 0, 0, 0),  RS | RT | SIMM},
0138     [insn_lwx]  = {M(spec3_op, 0, 0, 0, lwx_op, lx_op), RS | RT | RD},
0139     [insn_mfc0] = {M(cop0_op, mfc_op, 0, 0, 0, 0),  RT | RD | SET},
0140     [insn_mfhc0]    = {M(cop0_op, mfhc0_op, 0, 0, 0, 0),  RT | RD | SET},
0141     [insn_mfhi] = {M(spec_op, 0, 0, 0, 0, mfhi_op), RD},
0142     [insn_mflo] = {M(spec_op, 0, 0, 0, 0, mflo_op), RD},
0143     [insn_modu] = {M(spec_op, 0, 0, 0, divu_modu_op, divu_op),
0144                 RS | RT | RD},
0145     [insn_movn] = {M(spec_op, 0, 0, 0, 0, movn_op), RS | RT | RD},
0146     [insn_movz] = {M(spec_op, 0, 0, 0, 0, movz_op), RS | RT | RD},
0147     [insn_mtc0] = {M(cop0_op, mtc_op, 0, 0, 0, 0),  RT | RD | SET},
0148     [insn_mthc0]    = {M(cop0_op, mthc0_op, 0, 0, 0, 0),  RT | RD | SET},
0149     [insn_mthi] = {M(spec_op, 0, 0, 0, 0, mthi_op), RS},
0150     [insn_mtlo] = {M(spec_op, 0, 0, 0, 0, mtlo_op), RS},
0151     [insn_mulu] = {M(spec_op, 0, 0, 0, multu_mulu_op, multu_op),
0152                 RS | RT | RD},
0153     [insn_muhu] = {M(spec_op, 0, 0, 0, multu_muhu_op, multu_op),
0154                 RS | RT | RD},
0155 #ifndef CONFIG_CPU_MIPSR6
0156     [insn_mul]  = {M(spec2_op, 0, 0, 0, 0, mul_op), RS | RT | RD},
0157 #else
0158     [insn_mul]  = {M(spec_op, 0, 0, 0, mult_mul_op, mult_op), RS | RT | RD},
0159 #endif
0160     [insn_multu]    = {M(spec_op, 0, 0, 0, 0, multu_op), RS | RT},
0161     [insn_nor]  = {M(spec_op, 0, 0, 0, 0, nor_op),  RS | RT | RD},
0162     [insn_or]   = {M(spec_op, 0, 0, 0, 0, or_op),  RS | RT | RD},
0163     [insn_ori]  = {M(ori_op, 0, 0, 0, 0, 0),    RS | RT | UIMM},
0164 #ifndef CONFIG_CPU_MIPSR6
0165     [insn_pref] = {M(pref_op, 0, 0, 0, 0, 0),  RS | RT | SIMM},
0166 #else
0167     [insn_pref] = {M6(spec3_op, 0, 0, 0, pref6_op),  RS | RT | SIMM9},
0168 #endif
0169     [insn_rfe]  = {M(cop0_op, cop_op, 0, 0, 0, rfe_op),  0},
0170     [insn_rotr] = {M(spec_op, 1, 0, 0, 0, srl_op),  RT | RD | RE},
0171     [insn_sb]   = {M(sb_op, 0, 0, 0, 0, 0),  RS | RT | SIMM},
0172 #ifndef CONFIG_CPU_MIPSR6
0173     [insn_sc]   = {M(sc_op, 0, 0, 0, 0, 0),  RS | RT | SIMM},
0174     [insn_scd]  = {M(scd_op, 0, 0, 0, 0, 0),    RS | RT | SIMM},
0175 #else
0176     [insn_sc]   = {M6(spec3_op, 0, 0, 0, sc6_op),  RS | RT | SIMM9},
0177     [insn_scd]  = {M6(spec3_op, 0, 0, 0, scd6_op),  RS | RT | SIMM9},
0178 #endif
0179     [insn_sd]   = {M(sd_op, 0, 0, 0, 0, 0),  RS | RT | SIMM},
0180     [insn_seleqz]   = {M(spec_op, 0, 0, 0, 0, seleqz_op), RS | RT | RD},
0181     [insn_selnez]   = {M(spec_op, 0, 0, 0, 0, selnez_op), RS | RT | RD},
0182     [insn_sh]   = {M(sh_op, 0, 0, 0, 0, 0),  RS | RT | SIMM},
0183     [insn_sll]  = {M(spec_op, 0, 0, 0, 0, sll_op),  RT | RD | RE},
0184     [insn_sllv] = {M(spec_op, 0, 0, 0, 0, sllv_op),  RS | RT | RD},
0185     [insn_slt]  = {M(spec_op, 0, 0, 0, 0, slt_op),  RS | RT | RD},
0186     [insn_slti] = {M(slti_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
0187     [insn_sltiu]    = {M(sltiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
0188     [insn_sltu] = {M(spec_op, 0, 0, 0, 0, sltu_op), RS | RT | RD},
0189     [insn_sra]  = {M(spec_op, 0, 0, 0, 0, sra_op),  RT | RD | RE},
0190     [insn_srav] = {M(spec_op, 0, 0, 0, 0, srav_op), RS | RT | RD},
0191     [insn_srl]  = {M(spec_op, 0, 0, 0, 0, srl_op),  RT | RD | RE},
0192     [insn_srlv] = {M(spec_op, 0, 0, 0, 0, srlv_op),  RS | RT | RD},
0193     [insn_subu] = {M(spec_op, 0, 0, 0, 0, subu_op), RS | RT | RD},
0194     [insn_sw]   = {M(sw_op, 0, 0, 0, 0, 0),  RS | RT | SIMM},
0195     [insn_sync] = {M(spec_op, 0, 0, 0, 0, sync_op), RE},
0196     [insn_syscall]  = {M(spec_op, 0, 0, 0, 0, syscall_op), SCIMM},
0197     [insn_tlbp] = {M(cop0_op, cop_op, 0, 0, 0, tlbp_op),  0},
0198     [insn_tlbr] = {M(cop0_op, cop_op, 0, 0, 0, tlbr_op),  0},
0199     [insn_tlbwi]    = {M(cop0_op, cop_op, 0, 0, 0, tlbwi_op),  0},
0200     [insn_tlbwr]    = {M(cop0_op, cop_op, 0, 0, 0, tlbwr_op),  0},
0201     [insn_wait] = {M(cop0_op, cop_op, 0, 0, 0, wait_op), SCIMM},
0202     [insn_wsbh] = {M(spec3_op, 0, 0, 0, wsbh_op, bshfl_op), RT | RD},
0203     [insn_xor]  = {M(spec_op, 0, 0, 0, 0, xor_op),  RS | RT | RD},
0204     [insn_xori] = {M(xori_op, 0, 0, 0, 0, 0),  RS | RT | UIMM},
0205     [insn_yield]    = {M(spec3_op, 0, 0, 0, 0, yield_op), RS | RD},
0206 };
0207 
0208 #undef M
0209 
0210 static inline u32 build_bimm(s32 arg)
0211 {
0212     WARN(arg > 0x1ffff || arg < -0x20000,
0213          KERN_WARNING "Micro-assembler field overflow\n");
0214 
0215     WARN(arg & 0x3, KERN_WARNING "Invalid micro-assembler branch target\n");
0216 
0217     return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff);
0218 }
0219 
0220 static inline u32 build_jimm(u32 arg)
0221 {
0222     WARN(arg & ~(JIMM_MASK << 2),
0223          KERN_WARNING "Micro-assembler field overflow\n");
0224 
0225     return (arg >> 2) & JIMM_MASK;
0226 }
0227 
0228 /*
0229  * The order of opcode arguments is implicitly left to right,
0230  * starting with RS and ending with FUNC or IMM.
0231  */
0232 static void build_insn(u32 **buf, enum opcode opc, ...)
0233 {
0234     const struct insn *ip;
0235     va_list ap;
0236     u32 op;
0237 
0238     if (opc < 0 || opc >= insn_invalid ||
0239         (opc == insn_daddiu && r4k_daddiu_bug()) ||
0240         (insn_table[opc].match == 0 && insn_table[opc].fields == 0))
0241         panic("Unsupported Micro-assembler instruction %d", opc);
0242 
0243     ip = &insn_table[opc];
0244 
0245     op = ip->match;
0246     va_start(ap, opc);
0247     if (ip->fields & RS)
0248         op |= build_rs(va_arg(ap, u32));
0249     if (ip->fields & RT)
0250         op |= build_rt(va_arg(ap, u32));
0251     if (ip->fields & RD)
0252         op |= build_rd(va_arg(ap, u32));
0253     if (ip->fields & RE)
0254         op |= build_re(va_arg(ap, u32));
0255     if (ip->fields & SIMM)
0256         op |= build_simm(va_arg(ap, s32));
0257     if (ip->fields & UIMM)
0258         op |= build_uimm(va_arg(ap, u32));
0259     if (ip->fields & BIMM)
0260         op |= build_bimm(va_arg(ap, s32));
0261     if (ip->fields & JIMM)
0262         op |= build_jimm(va_arg(ap, u32));
0263     if (ip->fields & FUNC)
0264         op |= build_func(va_arg(ap, u32));
0265     if (ip->fields & SET)
0266         op |= build_set(va_arg(ap, u32));
0267     if (ip->fields & SCIMM)
0268         op |= build_scimm(va_arg(ap, u32));
0269     if (ip->fields & SIMM9)
0270         op |= build_scimm9(va_arg(ap, u32));
0271     va_end(ap);
0272 
0273     **buf = op;
0274     (*buf)++;
0275 }
0276 
0277 static inline void
0278 __resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab)
0279 {
0280     long laddr = (long)lab->addr;
0281     long raddr = (long)rel->addr;
0282 
0283     switch (rel->type) {
0284     case R_MIPS_PC16:
0285         *rel->addr |= build_bimm(laddr - (raddr + 4));
0286         break;
0287 
0288     default:
0289         panic("Unsupported Micro-assembler relocation %d",
0290               rel->type);
0291     }
0292 }
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