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0001 /*
0002  * This file is subject to the terms and conditions of the GNU General Public
0003  * License.  See the file "COPYING" in the main directory of this archive
0004  * for more details.
0005  *
0006  * A small micro-assembler. It is intentionally kept simple, does only
0007  * support a subset of instructions, and does not try to hide pipeline
0008  * effects like branch delay slots.
0009  *
0010  * Copyright (C) 2004, 2005, 2006, 2008  Thiemo Seufer
0011  * Copyright (C) 2005, 2007  Maciej W. Rozycki
0012  * Copyright (C) 2006  Ralf Baechle (ralf@linux-mips.org)
0013  * Copyright (C) 2012, 2013   MIPS Technologies, Inc.  All rights reserved.
0014  */
0015 
0016 #include <linux/kernel.h>
0017 #include <linux/types.h>
0018 
0019 #include <asm/inst.h>
0020 #include <asm/elf.h>
0021 #include <asm/bugs.h>
0022 #include <asm/uasm.h>
0023 
0024 #define RS_MASK     0x1f
0025 #define RS_SH       16
0026 #define RT_MASK     0x1f
0027 #define RT_SH       21
0028 #define SCIMM_MASK  0x3ff
0029 #define SCIMM_SH    16
0030 
0031 /* This macro sets the non-variable bits of an instruction. */
0032 #define M(a, b, c, d, e, f)                 \
0033     ((a) << OP_SH                       \
0034      | (b) << RT_SH                     \
0035      | (c) << RS_SH                     \
0036      | (d) << RD_SH                     \
0037      | (e) << RE_SH                     \
0038      | (f) << FUNC_SH)
0039 
0040 #include "uasm.c"
0041 
0042 static const struct insn insn_table_MM[insn_invalid] = {
0043     [insn_addu] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_addu32_op), RT | RS | RD},
0044     [insn_addiu]    = {M(mm_addiu32_op, 0, 0, 0, 0, 0), RT | RS | SIMM},
0045     [insn_and]  = {M(mm_pool32a_op, 0, 0, 0, 0, mm_and_op), RT | RS | RD},
0046     [insn_andi] = {M(mm_andi32_op, 0, 0, 0, 0, 0), RT | RS | UIMM},
0047     [insn_beq]  = {M(mm_beq32_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
0048     [insn_beql] = {0, 0},
0049     [insn_bgez] = {M(mm_pool32i_op, mm_bgez_op, 0, 0, 0, 0), RS | BIMM},
0050     [insn_bgezl]    = {0, 0},
0051     [insn_bltz] = {M(mm_pool32i_op, mm_bltz_op, 0, 0, 0, 0), RS | BIMM},
0052     [insn_bltzl]    = {0, 0},
0053     [insn_bne]  = {M(mm_bne32_op, 0, 0, 0, 0, 0), RT | RS | BIMM},
0054     [insn_cache]    = {M(mm_pool32b_op, 0, 0, mm_cache_func, 0, 0), RT | RS | SIMM},
0055     [insn_cfc1] = {M(mm_pool32f_op, 0, 0, 0, mm_cfc1_op, mm_32f_73_op), RT | RS},
0056     [insn_cfcmsa]   = {M(mm_pool32s_op, 0, msa_cfc_op, 0, 0, mm_32s_elm_op), RD | RE},
0057     [insn_ctc1] = {M(mm_pool32f_op, 0, 0, 0, mm_ctc1_op, mm_32f_73_op), RT | RS},
0058     [insn_ctcmsa]   = {M(mm_pool32s_op, 0, msa_ctc_op, 0, 0, mm_32s_elm_op), RD | RE},
0059     [insn_daddu]    = {0, 0},
0060     [insn_daddiu]   = {0, 0},
0061     [insn_di]   = {M(mm_pool32a_op, 0, 0, 0, mm_di_op, mm_pool32axf_op), RS},
0062     [insn_divu] = {M(mm_pool32a_op, 0, 0, 0, mm_divu_op, mm_pool32axf_op), RT | RS},
0063     [insn_dmfc0]    = {0, 0},
0064     [insn_dmtc0]    = {0, 0},
0065     [insn_dsll] = {0, 0},
0066     [insn_dsll32]   = {0, 0},
0067     [insn_dsra] = {0, 0},
0068     [insn_dsrl] = {0, 0},
0069     [insn_dsrl32]   = {0, 0},
0070     [insn_drotr]    = {0, 0},
0071     [insn_drotr32]  = {0, 0},
0072     [insn_dsubu]    = {0, 0},
0073     [insn_eret] = {M(mm_pool32a_op, 0, 0, 0, mm_eret_op, mm_pool32axf_op), 0},
0074     [insn_ins]  = {M(mm_pool32a_op, 0, 0, 0, 0, mm_ins_op), RT | RS | RD | RE},
0075     [insn_ext]  = {M(mm_pool32a_op, 0, 0, 0, 0, mm_ext_op), RT | RS | RD | RE},
0076     [insn_j]    = {M(mm_j32_op, 0, 0, 0, 0, 0), JIMM},
0077     [insn_jal]  = {M(mm_jal32_op, 0, 0, 0, 0, 0), JIMM},
0078     [insn_jalr] = {M(mm_pool32a_op, 0, 0, 0, mm_jalr_op, mm_pool32axf_op), RT | RS},
0079     [insn_jr]   = {M(mm_pool32a_op, 0, 0, 0, mm_jalr_op, mm_pool32axf_op), RS},
0080     [insn_lb]   = {M(mm_lb32_op, 0, 0, 0, 0, 0), RT | RS | SIMM},
0081     [insn_ld]   = {0, 0},
0082     [insn_lh]   = {M(mm_lh32_op, 0, 0, 0, 0, 0), RT | RS | SIMM},
0083     [insn_ll]   = {M(mm_pool32c_op, 0, 0, (mm_ll_func << 1), 0, 0), RS | RT | SIMM},
0084     [insn_lld]  = {0, 0},
0085     [insn_lui]  = {M(mm_pool32i_op, mm_lui_op, 0, 0, 0, 0), RS | SIMM},
0086     [insn_lw]   = {M(mm_lw32_op, 0, 0, 0, 0, 0), RT | RS | SIMM},
0087     [insn_mfc0] = {M(mm_pool32a_op, 0, 0, 0, mm_mfc0_op, mm_pool32axf_op), RT | RS | RD},
0088     [insn_mfhi] = {M(mm_pool32a_op, 0, 0, 0, mm_mfhi32_op, mm_pool32axf_op), RS},
0089     [insn_mflo] = {M(mm_pool32a_op, 0, 0, 0, mm_mflo32_op, mm_pool32axf_op), RS},
0090     [insn_mtc0] = {M(mm_pool32a_op, 0, 0, 0, mm_mtc0_op, mm_pool32axf_op), RT | RS | RD},
0091     [insn_mthi] = {M(mm_pool32a_op, 0, 0, 0, mm_mthi32_op, mm_pool32axf_op), RS},
0092     [insn_mtlo] = {M(mm_pool32a_op, 0, 0, 0, mm_mtlo32_op, mm_pool32axf_op), RS},
0093     [insn_mul]  = {M(mm_pool32a_op, 0, 0, 0, 0, mm_mul_op), RT | RS | RD},
0094     [insn_or]   = {M(mm_pool32a_op, 0, 0, 0, 0, mm_or32_op), RT | RS | RD},
0095     [insn_ori]  = {M(mm_ori32_op, 0, 0, 0, 0, 0), RT | RS | UIMM},
0096     [insn_pref] = {M(mm_pool32c_op, 0, 0, (mm_pref_func << 1), 0, 0), RT | RS | SIMM},
0097     [insn_rfe]  = {0, 0},
0098     [insn_sc]   = {M(mm_pool32c_op, 0, 0, (mm_sc_func << 1), 0, 0), RT | RS | SIMM},
0099     [insn_scd]  = {0, 0},
0100     [insn_sd]   = {0, 0},
0101     [insn_sll]  = {M(mm_pool32a_op, 0, 0, 0, 0, mm_sll32_op), RT | RS | RD},
0102     [insn_sllv] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_sllv32_op), RT | RS | RD},
0103     [insn_slt]  = {M(mm_pool32a_op, 0, 0, 0, 0, mm_slt_op), RT | RS | RD},
0104     [insn_sltiu]    = {M(mm_sltiu32_op, 0, 0, 0, 0, 0), RT | RS | SIMM},
0105     [insn_sltu] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_sltu_op), RT | RS | RD},
0106     [insn_sra]  = {M(mm_pool32a_op, 0, 0, 0, 0, mm_sra_op), RT | RS | RD},
0107     [insn_srav] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_srav_op), RT | RS | RD},
0108     [insn_srl]  = {M(mm_pool32a_op, 0, 0, 0, 0, mm_srl32_op), RT | RS | RD},
0109     [insn_srlv] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_srlv32_op), RT | RS | RD},
0110     [insn_rotr] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_rotr_op), RT | RS | RD},
0111     [insn_subu] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_subu32_op), RT | RS | RD},
0112     [insn_sw]   = {M(mm_sw32_op, 0, 0, 0, 0, 0), RT | RS | SIMM},
0113     [insn_sync] = {M(mm_pool32a_op, 0, 0, 0, mm_sync_op, mm_pool32axf_op), RS},
0114     [insn_tlbp] = {M(mm_pool32a_op, 0, 0, 0, mm_tlbp_op, mm_pool32axf_op), 0},
0115     [insn_tlbr] = {M(mm_pool32a_op, 0, 0, 0, mm_tlbr_op, mm_pool32axf_op), 0},
0116     [insn_tlbwi]    = {M(mm_pool32a_op, 0, 0, 0, mm_tlbwi_op, mm_pool32axf_op), 0},
0117     [insn_tlbwr]    = {M(mm_pool32a_op, 0, 0, 0, mm_tlbwr_op, mm_pool32axf_op), 0},
0118     [insn_wait] = {M(mm_pool32a_op, 0, 0, 0, mm_wait_op, mm_pool32axf_op), SCIMM},
0119     [insn_wsbh] = {M(mm_pool32a_op, 0, 0, 0, mm_wsbh_op, mm_pool32axf_op), RT | RS},
0120     [insn_xor]  = {M(mm_pool32a_op, 0, 0, 0, 0, mm_xor32_op), RT | RS | RD},
0121     [insn_xori] = {M(mm_xori32_op, 0, 0, 0, 0, 0), RT | RS | UIMM},
0122     [insn_dins] = {0, 0},
0123     [insn_dinsm]    = {0, 0},
0124     [insn_syscall]  = {M(mm_pool32a_op, 0, 0, 0, mm_syscall_op, mm_pool32axf_op), SCIMM},
0125     [insn_bbit0]    = {0, 0},
0126     [insn_bbit1]    = {0, 0},
0127     [insn_lwx]  = {0, 0},
0128     [insn_ldx]  = {0, 0},
0129 };
0130 
0131 #undef M
0132 
0133 static inline u32 build_bimm(s32 arg)
0134 {
0135     WARN(arg > 0xffff || arg < -0x10000,
0136          KERN_WARNING "Micro-assembler field overflow\n");
0137 
0138     WARN(arg & 0x3, KERN_WARNING "Invalid micro-assembler branch target\n");
0139 
0140     return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 1) & 0x7fff);
0141 }
0142 
0143 static inline u32 build_jimm(u32 arg)
0144 {
0145 
0146     WARN(arg & ~((JIMM_MASK << 2) | 1),
0147          KERN_WARNING "Micro-assembler field overflow\n");
0148 
0149     return (arg >> 1) & JIMM_MASK;
0150 }
0151 
0152 /*
0153  * The order of opcode arguments is implicitly left to right,
0154  * starting with RS and ending with FUNC or IMM.
0155  */
0156 static void build_insn(u32 **buf, enum opcode opc, ...)
0157 {
0158     const struct insn *ip;
0159     va_list ap;
0160     u32 op;
0161 
0162     if (opc < 0 || opc >= insn_invalid ||
0163         (opc == insn_daddiu && r4k_daddiu_bug()) ||
0164         (insn_table_MM[opc].match == 0 && insn_table_MM[opc].fields == 0))
0165         panic("Unsupported Micro-assembler instruction %d", opc);
0166 
0167     ip = &insn_table_MM[opc];
0168 
0169     op = ip->match;
0170     va_start(ap, opc);
0171     if (ip->fields & RS) {
0172         if (opc == insn_mfc0 || opc == insn_mtc0 ||
0173             opc == insn_cfc1 || opc == insn_ctc1)
0174             op |= build_rt(va_arg(ap, u32));
0175         else
0176             op |= build_rs(va_arg(ap, u32));
0177     }
0178     if (ip->fields & RT) {
0179         if (opc == insn_mfc0 || opc == insn_mtc0 ||
0180             opc == insn_cfc1 || opc == insn_ctc1)
0181             op |= build_rs(va_arg(ap, u32));
0182         else
0183             op |= build_rt(va_arg(ap, u32));
0184     }
0185     if (ip->fields & RD)
0186         op |= build_rd(va_arg(ap, u32));
0187     if (ip->fields & RE)
0188         op |= build_re(va_arg(ap, u32));
0189     if (ip->fields & SIMM)
0190         op |= build_simm(va_arg(ap, s32));
0191     if (ip->fields & UIMM)
0192         op |= build_uimm(va_arg(ap, u32));
0193     if (ip->fields & BIMM)
0194         op |= build_bimm(va_arg(ap, s32));
0195     if (ip->fields & JIMM)
0196         op |= build_jimm(va_arg(ap, u32));
0197     if (ip->fields & FUNC)
0198         op |= build_func(va_arg(ap, u32));
0199     if (ip->fields & SET)
0200         op |= build_set(va_arg(ap, u32));
0201     if (ip->fields & SCIMM)
0202         op |= build_scimm(va_arg(ap, u32));
0203     va_end(ap);
0204 
0205 #ifdef CONFIG_CPU_LITTLE_ENDIAN
0206     **buf = ((op & 0xffff) << 16) | (op >> 16);
0207 #else
0208     **buf = op;
0209 #endif
0210     (*buf)++;
0211 }
0212 
0213 static inline void
0214 __resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab)
0215 {
0216     long laddr = (long)lab->addr;
0217     long raddr = (long)rel->addr;
0218 
0219     switch (rel->type) {
0220     case R_MIPS_PC16:
0221 #ifdef CONFIG_CPU_LITTLE_ENDIAN
0222         *rel->addr |= (build_bimm(laddr - (raddr + 4)) << 16);
0223 #else
0224         *rel->addr |= build_bimm(laddr - (raddr + 4));
0225 #endif
0226         break;
0227 
0228     default:
0229         panic("Unsupported Micro-assembler relocation %d",
0230               rel->type);
0231     }
0232 }
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