mips/mm/cex-oct.S

0001 /*
0002  * This file is subject to the terms and conditions of the GNU General Public
0003  * License.  See the file "COPYING" in the main directory of this archive
0004  * for more details.
0005  *
0006  * Copyright (C) 2006 Cavium Networks
0007  * Cache error handler
0008  */
0009
0010 #include <asm/asm.h>
0011 #include <asm/regdef.h>
0012 #include <asm/mipsregs.h>
0013 #include <asm/stackframe.h>
0014
0015 /*
0016  * Handle cache error. Indicate to the second level handler whether
0017  * the exception is recoverable.
0018  */
0019     LEAF(except_vec2_octeon)
0020
0021     .set    push
0022     .set    mips64r2
0023     .set    noreorder
0024     .set    noat
0025
0026
0027     /* due to an errata we need to read the COP0 CacheErr (Dcache)
0028      * before any cache/DRAM access  */
0029
0030     rdhwr   k0, $0        /* get core_id */
0031     PTR_LA  k1, cache_err_dcache
0032     sll k0, k0, 3
0033     PTR_ADDU k1, k0, k1    /* k1 = &cache_err_dcache[core_id] */
0034
0035     dmfc0   k0, CP0_CACHEERR, 1
0036     sd  k0, (k1)
0037     dmtc0   $0, CP0_CACHEERR, 1
0038
0039     /* check whether this is a nested exception */
0040     mfc0    k1, CP0_STATUS
0041     andi    k1, k1, ST0_EXL
0042     beqz    k1, 1f
0043      nop
0044     j   cache_parity_error_octeon_non_recoverable
0045      nop
0046
0047     /* exception is recoverable */
0048 1:  j   handle_cache_err
0049      nop
0050
0051     .set    pop
0052     END(except_vec2_octeon)
0053
0054  /* We need to jump to handle_cache_err so that the previous handler
0055   * can fit within 0x80 bytes. We also move from 0xFFFFFFFFAXXXXXXX
0056   * space (uncached) to the 0xFFFFFFFF8XXXXXXX space (cached).  */
0057     LEAF(handle_cache_err)
0058     .set    push
0059     .set    noreorder
0060     .set    noat
0061
0062     SAVE_ALL
0063     KMODE
0064     jal cache_parity_error_octeon_recoverable
0065     nop
0066     j   ret_from_exception
0067     nop
0068
0069     .set pop
0070     END(handle_cache_err)