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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (C) 2010, 2011, 2012, Lemote, Inc.
0004  * Author: Chen Huacai, chenhc@lemote.com
0005  */
0006 
0007 #include <irq.h>
0008 #include <linux/init.h>
0009 #include <linux/cpu.h>
0010 #include <linux/sched.h>
0011 #include <linux/sched/hotplug.h>
0012 #include <linux/sched/task_stack.h>
0013 #include <linux/smp.h>
0014 #include <linux/cpufreq.h>
0015 #include <linux/kexec.h>
0016 #include <asm/processor.h>
0017 #include <asm/time.h>
0018 #include <asm/tlbflush.h>
0019 #include <asm/cacheflush.h>
0020 #include <loongson.h>
0021 #include <loongson_regs.h>
0022 #include <workarounds.h>
0023 
0024 #include "smp.h"
0025 
0026 DEFINE_PER_CPU(int, cpu_state);
0027 
0028 #define LS_IPI_IRQ (MIPS_CPU_IRQ_BASE + 6)
0029 
0030 static void *ipi_set0_regs[16];
0031 static void *ipi_clear0_regs[16];
0032 static void *ipi_status0_regs[16];
0033 static void *ipi_en0_regs[16];
0034 static void *ipi_mailbox_buf[16];
0035 static uint32_t core0_c0count[NR_CPUS];
0036 
0037 /* read a 32bit value from ipi register */
0038 #define loongson3_ipi_read32(addr) readl(addr)
0039 /* read a 64bit value from ipi register */
0040 #define loongson3_ipi_read64(addr) readq(addr)
0041 /* write a 32bit value to ipi register */
0042 #define loongson3_ipi_write32(action, addr) \
0043     do {                    \
0044         writel(action, addr);       \
0045         __wbflush();            \
0046     } while (0)
0047 /* write a 64bit value to ipi register */
0048 #define loongson3_ipi_write64(action, addr) \
0049     do {                    \
0050         writeq(action, addr);       \
0051         __wbflush();            \
0052     } while (0)
0053 
0054 static u32 (*ipi_read_clear)(int cpu);
0055 static void (*ipi_write_action)(int cpu, u32 action);
0056 static void (*ipi_write_enable)(int cpu);
0057 static void (*ipi_clear_buf)(int cpu);
0058 static void (*ipi_write_buf)(int cpu, struct task_struct *idle);
0059 
0060 /* send mail via Mail_Send register for 3A4000+ CPU */
0061 static void csr_mail_send(uint64_t data, int cpu, int mailbox)
0062 {
0063     uint64_t val;
0064 
0065     /* send high 32 bits */
0066     val = CSR_MAIL_SEND_BLOCK;
0067     val |= (CSR_MAIL_SEND_BOX_HIGH(mailbox) << CSR_MAIL_SEND_BOX_SHIFT);
0068     val |= (cpu << CSR_MAIL_SEND_CPU_SHIFT);
0069     val |= (data & CSR_MAIL_SEND_H32_MASK);
0070     csr_writeq(val, LOONGSON_CSR_MAIL_SEND);
0071 
0072     /* send low 32 bits */
0073     val = CSR_MAIL_SEND_BLOCK;
0074     val |= (CSR_MAIL_SEND_BOX_LOW(mailbox) << CSR_MAIL_SEND_BOX_SHIFT);
0075     val |= (cpu << CSR_MAIL_SEND_CPU_SHIFT);
0076     val |= (data << CSR_MAIL_SEND_BUF_SHIFT);
0077     csr_writeq(val, LOONGSON_CSR_MAIL_SEND);
0078 };
0079 
0080 static u32 csr_ipi_read_clear(int cpu)
0081 {
0082     u32 action;
0083 
0084     /* Load the ipi register to figure out what we're supposed to do */
0085     action = csr_readl(LOONGSON_CSR_IPI_STATUS);
0086     /* Clear the ipi register to clear the interrupt */
0087     csr_writel(action, LOONGSON_CSR_IPI_CLEAR);
0088 
0089     return action;
0090 }
0091 
0092 static void csr_ipi_write_action(int cpu, u32 action)
0093 {
0094     unsigned int irq = 0;
0095 
0096     while ((irq = ffs(action))) {
0097         uint32_t val = CSR_IPI_SEND_BLOCK;
0098         val |= (irq - 1);
0099         val |= (cpu << CSR_IPI_SEND_CPU_SHIFT);
0100         csr_writel(val, LOONGSON_CSR_IPI_SEND);
0101         action &= ~BIT(irq - 1);
0102     }
0103 }
0104 
0105 static void csr_ipi_write_enable(int cpu)
0106 {
0107     csr_writel(0xffffffff, LOONGSON_CSR_IPI_EN);
0108 }
0109 
0110 static void csr_ipi_clear_buf(int cpu)
0111 {
0112     csr_writeq(0, LOONGSON_CSR_MAIL_BUF0);
0113 }
0114 
0115 static void csr_ipi_write_buf(int cpu, struct task_struct *idle)
0116 {
0117     unsigned long startargs[4];
0118 
0119     /* startargs[] are initial PC, SP and GP for secondary CPU */
0120     startargs[0] = (unsigned long)&smp_bootstrap;
0121     startargs[1] = (unsigned long)__KSTK_TOS(idle);
0122     startargs[2] = (unsigned long)task_thread_info(idle);
0123     startargs[3] = 0;
0124 
0125     pr_debug("CPU#%d, func_pc=%lx, sp=%lx, gp=%lx\n",
0126         cpu, startargs[0], startargs[1], startargs[2]);
0127 
0128     csr_mail_send(startargs[3], cpu_logical_map(cpu), 3);
0129     csr_mail_send(startargs[2], cpu_logical_map(cpu), 2);
0130     csr_mail_send(startargs[1], cpu_logical_map(cpu), 1);
0131     csr_mail_send(startargs[0], cpu_logical_map(cpu), 0);
0132 }
0133 
0134 static u32 legacy_ipi_read_clear(int cpu)
0135 {
0136     u32 action;
0137 
0138     /* Load the ipi register to figure out what we're supposed to do */
0139     action = loongson3_ipi_read32(ipi_status0_regs[cpu_logical_map(cpu)]);
0140     /* Clear the ipi register to clear the interrupt */
0141     loongson3_ipi_write32(action, ipi_clear0_regs[cpu_logical_map(cpu)]);
0142 
0143     return action;
0144 }
0145 
0146 static void legacy_ipi_write_action(int cpu, u32 action)
0147 {
0148     loongson3_ipi_write32((u32)action, ipi_set0_regs[cpu]);
0149 }
0150 
0151 static void legacy_ipi_write_enable(int cpu)
0152 {
0153     loongson3_ipi_write32(0xffffffff, ipi_en0_regs[cpu_logical_map(cpu)]);
0154 }
0155 
0156 static void legacy_ipi_clear_buf(int cpu)
0157 {
0158     loongson3_ipi_write64(0, ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x0);
0159 }
0160 
0161 static void legacy_ipi_write_buf(int cpu, struct task_struct *idle)
0162 {
0163     unsigned long startargs[4];
0164 
0165     /* startargs[] are initial PC, SP and GP for secondary CPU */
0166     startargs[0] = (unsigned long)&smp_bootstrap;
0167     startargs[1] = (unsigned long)__KSTK_TOS(idle);
0168     startargs[2] = (unsigned long)task_thread_info(idle);
0169     startargs[3] = 0;
0170 
0171     pr_debug("CPU#%d, func_pc=%lx, sp=%lx, gp=%lx\n",
0172             cpu, startargs[0], startargs[1], startargs[2]);
0173 
0174     loongson3_ipi_write64(startargs[3],
0175             ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x18);
0176     loongson3_ipi_write64(startargs[2],
0177             ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x10);
0178     loongson3_ipi_write64(startargs[1],
0179             ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x8);
0180     loongson3_ipi_write64(startargs[0],
0181             ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x0);
0182 }
0183 
0184 static void csr_ipi_probe(void)
0185 {
0186     if (cpu_has_csr() && csr_readl(LOONGSON_CSR_FEATURES) & LOONGSON_CSRF_IPI) {
0187         ipi_read_clear = csr_ipi_read_clear;
0188         ipi_write_action = csr_ipi_write_action;
0189         ipi_write_enable = csr_ipi_write_enable;
0190         ipi_clear_buf = csr_ipi_clear_buf;
0191         ipi_write_buf = csr_ipi_write_buf;
0192     } else {
0193         ipi_read_clear = legacy_ipi_read_clear;
0194         ipi_write_action = legacy_ipi_write_action;
0195         ipi_write_enable = legacy_ipi_write_enable;
0196         ipi_clear_buf = legacy_ipi_clear_buf;
0197         ipi_write_buf = legacy_ipi_write_buf;
0198     }
0199 }
0200 
0201 static void ipi_set0_regs_init(void)
0202 {
0203     ipi_set0_regs[0] = (void *)
0204         (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + SET0);
0205     ipi_set0_regs[1] = (void *)
0206         (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + SET0);
0207     ipi_set0_regs[2] = (void *)
0208         (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + SET0);
0209     ipi_set0_regs[3] = (void *)
0210         (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + SET0);
0211     ipi_set0_regs[4] = (void *)
0212         (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + SET0);
0213     ipi_set0_regs[5] = (void *)
0214         (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + SET0);
0215     ipi_set0_regs[6] = (void *)
0216         (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + SET0);
0217     ipi_set0_regs[7] = (void *)
0218         (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + SET0);
0219     ipi_set0_regs[8] = (void *)
0220         (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + SET0);
0221     ipi_set0_regs[9] = (void *)
0222         (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + SET0);
0223     ipi_set0_regs[10] = (void *)
0224         (SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + SET0);
0225     ipi_set0_regs[11] = (void *)
0226         (SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + SET0);
0227     ipi_set0_regs[12] = (void *)
0228         (SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + SET0);
0229     ipi_set0_regs[13] = (void *)
0230         (SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + SET0);
0231     ipi_set0_regs[14] = (void *)
0232         (SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + SET0);
0233     ipi_set0_regs[15] = (void *)
0234         (SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + SET0);
0235 }
0236 
0237 static void ipi_clear0_regs_init(void)
0238 {
0239     ipi_clear0_regs[0] = (void *)
0240         (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + CLEAR0);
0241     ipi_clear0_regs[1] = (void *)
0242         (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + CLEAR0);
0243     ipi_clear0_regs[2] = (void *)
0244         (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + CLEAR0);
0245     ipi_clear0_regs[3] = (void *)
0246         (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + CLEAR0);
0247     ipi_clear0_regs[4] = (void *)
0248         (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + CLEAR0);
0249     ipi_clear0_regs[5] = (void *)
0250         (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + CLEAR0);
0251     ipi_clear0_regs[6] = (void *)
0252         (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + CLEAR0);
0253     ipi_clear0_regs[7] = (void *)
0254         (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + CLEAR0);
0255     ipi_clear0_regs[8] = (void *)
0256         (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + CLEAR0);
0257     ipi_clear0_regs[9] = (void *)
0258         (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + CLEAR0);
0259     ipi_clear0_regs[10] = (void *)
0260         (SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + CLEAR0);
0261     ipi_clear0_regs[11] = (void *)
0262         (SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + CLEAR0);
0263     ipi_clear0_regs[12] = (void *)
0264         (SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + CLEAR0);
0265     ipi_clear0_regs[13] = (void *)
0266         (SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + CLEAR0);
0267     ipi_clear0_regs[14] = (void *)
0268         (SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + CLEAR0);
0269     ipi_clear0_regs[15] = (void *)
0270         (SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + CLEAR0);
0271 }
0272 
0273 static void ipi_status0_regs_init(void)
0274 {
0275     ipi_status0_regs[0] = (void *)
0276         (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + STATUS0);
0277     ipi_status0_regs[1] = (void *)
0278         (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + STATUS0);
0279     ipi_status0_regs[2] = (void *)
0280         (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + STATUS0);
0281     ipi_status0_regs[3] = (void *)
0282         (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + STATUS0);
0283     ipi_status0_regs[4] = (void *)
0284         (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + STATUS0);
0285     ipi_status0_regs[5] = (void *)
0286         (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + STATUS0);
0287     ipi_status0_regs[6] = (void *)
0288         (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + STATUS0);
0289     ipi_status0_regs[7] = (void *)
0290         (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + STATUS0);
0291     ipi_status0_regs[8] = (void *)
0292         (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + STATUS0);
0293     ipi_status0_regs[9] = (void *)
0294         (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + STATUS0);
0295     ipi_status0_regs[10] = (void *)
0296         (SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + STATUS0);
0297     ipi_status0_regs[11] = (void *)
0298         (SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + STATUS0);
0299     ipi_status0_regs[12] = (void *)
0300         (SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + STATUS0);
0301     ipi_status0_regs[13] = (void *)
0302         (SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + STATUS0);
0303     ipi_status0_regs[14] = (void *)
0304         (SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + STATUS0);
0305     ipi_status0_regs[15] = (void *)
0306         (SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + STATUS0);
0307 }
0308 
0309 static void ipi_en0_regs_init(void)
0310 {
0311     ipi_en0_regs[0] = (void *)
0312         (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + EN0);
0313     ipi_en0_regs[1] = (void *)
0314         (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + EN0);
0315     ipi_en0_regs[2] = (void *)
0316         (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + EN0);
0317     ipi_en0_regs[3] = (void *)
0318         (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + EN0);
0319     ipi_en0_regs[4] = (void *)
0320         (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + EN0);
0321     ipi_en0_regs[5] = (void *)
0322         (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + EN0);
0323     ipi_en0_regs[6] = (void *)
0324         (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + EN0);
0325     ipi_en0_regs[7] = (void *)
0326         (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + EN0);
0327     ipi_en0_regs[8] = (void *)
0328         (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + EN0);
0329     ipi_en0_regs[9] = (void *)
0330         (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + EN0);
0331     ipi_en0_regs[10] = (void *)
0332         (SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + EN0);
0333     ipi_en0_regs[11] = (void *)
0334         (SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + EN0);
0335     ipi_en0_regs[12] = (void *)
0336         (SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + EN0);
0337     ipi_en0_regs[13] = (void *)
0338         (SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + EN0);
0339     ipi_en0_regs[14] = (void *)
0340         (SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + EN0);
0341     ipi_en0_regs[15] = (void *)
0342         (SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + EN0);
0343 }
0344 
0345 static void ipi_mailbox_buf_init(void)
0346 {
0347     ipi_mailbox_buf[0] = (void *)
0348         (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + BUF);
0349     ipi_mailbox_buf[1] = (void *)
0350         (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + BUF);
0351     ipi_mailbox_buf[2] = (void *)
0352         (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + BUF);
0353     ipi_mailbox_buf[3] = (void *)
0354         (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + BUF);
0355     ipi_mailbox_buf[4] = (void *)
0356         (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + BUF);
0357     ipi_mailbox_buf[5] = (void *)
0358         (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + BUF);
0359     ipi_mailbox_buf[6] = (void *)
0360         (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + BUF);
0361     ipi_mailbox_buf[7] = (void *)
0362         (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + BUF);
0363     ipi_mailbox_buf[8] = (void *)
0364         (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + BUF);
0365     ipi_mailbox_buf[9] = (void *)
0366         (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + BUF);
0367     ipi_mailbox_buf[10] = (void *)
0368         (SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + BUF);
0369     ipi_mailbox_buf[11] = (void *)
0370         (SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + BUF);
0371     ipi_mailbox_buf[12] = (void *)
0372         (SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + BUF);
0373     ipi_mailbox_buf[13] = (void *)
0374         (SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + BUF);
0375     ipi_mailbox_buf[14] = (void *)
0376         (SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + BUF);
0377     ipi_mailbox_buf[15] = (void *)
0378         (SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + BUF);
0379 }
0380 
0381 /*
0382  * Simple enough, just poke the appropriate ipi register
0383  */
0384 static void loongson3_send_ipi_single(int cpu, unsigned int action)
0385 {
0386     ipi_write_action(cpu_logical_map(cpu), (u32)action);
0387 }
0388 
0389 static void
0390 loongson3_send_ipi_mask(const struct cpumask *mask, unsigned int action)
0391 {
0392     unsigned int i;
0393 
0394     for_each_cpu(i, mask)
0395         ipi_write_action(cpu_logical_map(i), (u32)action);
0396 }
0397 
0398 
0399 static irqreturn_t loongson3_ipi_interrupt(int irq, void *dev_id)
0400 {
0401     int i, cpu = smp_processor_id();
0402     unsigned int action, c0count;
0403 
0404     action = ipi_read_clear(cpu);
0405 
0406     if (action & SMP_RESCHEDULE_YOURSELF)
0407         scheduler_ipi();
0408 
0409     if (action & SMP_CALL_FUNCTION) {
0410         irq_enter();
0411         generic_smp_call_function_interrupt();
0412         irq_exit();
0413     }
0414 
0415     if (action & SMP_ASK_C0COUNT) {
0416         BUG_ON(cpu != 0);
0417         c0count = read_c0_count();
0418         c0count = c0count ? c0count : 1;
0419         for (i = 1; i < nr_cpu_ids; i++)
0420             core0_c0count[i] = c0count;
0421         __wbflush(); /* Let others see the result ASAP */
0422     }
0423 
0424     return IRQ_HANDLED;
0425 }
0426 
0427 #define MAX_LOOPS 800
0428 /*
0429  * SMP init and finish on secondary CPUs
0430  */
0431 static void loongson3_init_secondary(void)
0432 {
0433     int i;
0434     uint32_t initcount;
0435     unsigned int cpu = smp_processor_id();
0436     unsigned int imask = STATUSF_IP7 | STATUSF_IP6 |
0437                  STATUSF_IP3 | STATUSF_IP2;
0438 
0439     /* Set interrupt mask, but don't enable */
0440     change_c0_status(ST0_IM, imask);
0441     ipi_write_enable(cpu);
0442 
0443     per_cpu(cpu_state, cpu) = CPU_ONLINE;
0444     cpu_set_core(&cpu_data[cpu],
0445              cpu_logical_map(cpu) % loongson_sysconf.cores_per_package);
0446     cpu_data[cpu].package =
0447         cpu_logical_map(cpu) / loongson_sysconf.cores_per_package;
0448 
0449     i = 0;
0450     core0_c0count[cpu] = 0;
0451     loongson3_send_ipi_single(0, SMP_ASK_C0COUNT);
0452     while (!core0_c0count[cpu]) {
0453         i++;
0454         cpu_relax();
0455     }
0456 
0457     if (i > MAX_LOOPS)
0458         i = MAX_LOOPS;
0459     if (cpu_data[cpu].package)
0460         initcount = core0_c0count[cpu] + i;
0461     else /* Local access is faster for loops */
0462         initcount = core0_c0count[cpu] + i/2;
0463 
0464     write_c0_count(initcount);
0465 }
0466 
0467 static void loongson3_smp_finish(void)
0468 {
0469     int cpu = smp_processor_id();
0470 
0471     write_c0_compare(read_c0_count() + mips_hpt_frequency/HZ);
0472     local_irq_enable();
0473     ipi_clear_buf(cpu);
0474 
0475     pr_info("CPU#%d finished, CP0_ST=%x\n",
0476             smp_processor_id(), read_c0_status());
0477 }
0478 
0479 static void __init loongson3_smp_setup(void)
0480 {
0481     int i = 0, num = 0; /* i: physical id, num: logical id */
0482 
0483     init_cpu_possible(cpu_none_mask);
0484 
0485     /* For unified kernel, NR_CPUS is the maximum possible value,
0486      * loongson_sysconf.nr_cpus is the really present value
0487      */
0488     while (i < loongson_sysconf.nr_cpus) {
0489         if (loongson_sysconf.reserved_cpus_mask & (1<<i)) {
0490             /* Reserved physical CPU cores */
0491             __cpu_number_map[i] = -1;
0492         } else {
0493             __cpu_number_map[i] = num;
0494             __cpu_logical_map[num] = i;
0495             set_cpu_possible(num, true);
0496             /* Loongson processors are always grouped by 4 */
0497             cpu_set_cluster(&cpu_data[num], i / 4);
0498             num++;
0499         }
0500         i++;
0501     }
0502     pr_info("Detected %i available CPU(s)\n", num);
0503 
0504     while (num < loongson_sysconf.nr_cpus) {
0505         __cpu_logical_map[num] = -1;
0506         num++;
0507     }
0508 
0509     csr_ipi_probe();
0510     ipi_set0_regs_init();
0511     ipi_clear0_regs_init();
0512     ipi_status0_regs_init();
0513     ipi_en0_regs_init();
0514     ipi_mailbox_buf_init();
0515     ipi_write_enable(0);
0516 
0517     cpu_set_core(&cpu_data[0],
0518              cpu_logical_map(0) % loongson_sysconf.cores_per_package);
0519     cpu_data[0].package = cpu_logical_map(0) / loongson_sysconf.cores_per_package;
0520 }
0521 
0522 static void __init loongson3_prepare_cpus(unsigned int max_cpus)
0523 {
0524     if (request_irq(LS_IPI_IRQ, loongson3_ipi_interrupt,
0525             IRQF_PERCPU | IRQF_NO_SUSPEND, "SMP_IPI", NULL))
0526         pr_err("Failed to request IPI IRQ\n");
0527     init_cpu_present(cpu_possible_mask);
0528     per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
0529 }
0530 
0531 /*
0532  * Setup the PC, SP, and GP of a secondary processor and start it runing!
0533  */
0534 static int loongson3_boot_secondary(int cpu, struct task_struct *idle)
0535 {
0536     pr_info("Booting CPU#%d...\n", cpu);
0537 
0538     ipi_write_buf(cpu, idle);
0539 
0540     return 0;
0541 }
0542 
0543 #ifdef CONFIG_HOTPLUG_CPU
0544 
0545 static int loongson3_cpu_disable(void)
0546 {
0547     unsigned long flags;
0548     unsigned int cpu = smp_processor_id();
0549 
0550     set_cpu_online(cpu, false);
0551     calculate_cpu_foreign_map();
0552     local_irq_save(flags);
0553     clear_c0_status(ST0_IM);
0554     local_irq_restore(flags);
0555     local_flush_tlb_all();
0556 
0557     return 0;
0558 }
0559 
0560 
0561 static void loongson3_cpu_die(unsigned int cpu)
0562 {
0563     while (per_cpu(cpu_state, cpu) != CPU_DEAD)
0564         cpu_relax();
0565 
0566     mb();
0567 }
0568 
0569 /* To shutdown a core in Loongson 3, the target core should go to CKSEG1 and
0570  * flush all L1 entries at first. Then, another core (usually Core 0) can
0571  * safely disable the clock of the target core. loongson3_play_dead() is
0572  * called via CKSEG1 (uncached and unmmaped)
0573  */
0574 static void loongson3_type1_play_dead(int *state_addr)
0575 {
0576     register int val;
0577     register long cpuid, core, node, count;
0578     register void *addr, *base, *initfunc;
0579 
0580     __asm__ __volatile__(
0581         "   .set push                     \n"
0582         "   .set noreorder                \n"
0583         "   li %[addr], 0x80000000        \n" /* KSEG0 */
0584         "1: cache 0, 0(%[addr])           \n" /* flush L1 ICache */
0585         "   cache 0, 1(%[addr])           \n"
0586         "   cache 0, 2(%[addr])           \n"
0587         "   cache 0, 3(%[addr])           \n"
0588         "   cache 1, 0(%[addr])           \n" /* flush L1 DCache */
0589         "   cache 1, 1(%[addr])           \n"
0590         "   cache 1, 2(%[addr])           \n"
0591         "   cache 1, 3(%[addr])           \n"
0592         "   addiu %[sets], %[sets], -1    \n"
0593         "   bnez  %[sets], 1b             \n"
0594         "   addiu %[addr], %[addr], 0x20  \n"
0595         "   li    %[val], 0x7             \n" /* *state_addr = CPU_DEAD; */
0596         "   sw    %[val], (%[state_addr]) \n"
0597         "   sync                          \n"
0598         "   cache 21, (%[state_addr])     \n" /* flush entry of *state_addr */
0599         "   .set pop                      \n"
0600         : [addr] "=&r" (addr), [val] "=&r" (val)
0601         : [state_addr] "r" (state_addr),
0602           [sets] "r" (cpu_data[smp_processor_id()].dcache.sets));
0603 
0604     __asm__ __volatile__(
0605         "   .set push                         \n"
0606         "   .set noreorder                    \n"
0607         "   .set mips64                       \n"
0608         "   mfc0  %[cpuid], $15, 1            \n"
0609         "   andi  %[cpuid], 0x3ff             \n"
0610         "   dli   %[base], 0x900000003ff01000 \n"
0611         "   andi  %[core], %[cpuid], 0x3      \n"
0612         "   sll   %[core], 8                  \n" /* get core id */
0613         "   or    %[base], %[base], %[core]   \n"
0614         "   andi  %[node], %[cpuid], 0xc      \n"
0615         "   dsll  %[node], 42                 \n" /* get node id */
0616         "   or    %[base], %[base], %[node]   \n"
0617         "1: li    %[count], 0x100             \n" /* wait for init loop */
0618         "2: bnez  %[count], 2b                \n" /* limit mailbox access */
0619         "   addiu %[count], -1                \n"
0620         "   ld    %[initfunc], 0x20(%[base])  \n" /* get PC via mailbox */
0621         "   beqz  %[initfunc], 1b             \n"
0622         "   nop                               \n"
0623         "   ld    $sp, 0x28(%[base])          \n" /* get SP via mailbox */
0624         "   ld    $gp, 0x30(%[base])          \n" /* get GP via mailbox */
0625         "   ld    $a1, 0x38(%[base])          \n"
0626         "   jr    %[initfunc]                 \n" /* jump to initial PC */
0627         "   nop                               \n"
0628         "   .set pop                          \n"
0629         : [core] "=&r" (core), [node] "=&r" (node),
0630           [base] "=&r" (base), [cpuid] "=&r" (cpuid),
0631           [count] "=&r" (count), [initfunc] "=&r" (initfunc)
0632         : /* No Input */
0633         : "a1");
0634 }
0635 
0636 static void loongson3_type2_play_dead(int *state_addr)
0637 {
0638     register int val;
0639     register long cpuid, core, node, count;
0640     register void *addr, *base, *initfunc;
0641 
0642     __asm__ __volatile__(
0643         "   .set push                     \n"
0644         "   .set noreorder                \n"
0645         "   li %[addr], 0x80000000        \n" /* KSEG0 */
0646         "1: cache 0, 0(%[addr])           \n" /* flush L1 ICache */
0647         "   cache 0, 1(%[addr])           \n"
0648         "   cache 0, 2(%[addr])           \n"
0649         "   cache 0, 3(%[addr])           \n"
0650         "   cache 1, 0(%[addr])           \n" /* flush L1 DCache */
0651         "   cache 1, 1(%[addr])           \n"
0652         "   cache 1, 2(%[addr])           \n"
0653         "   cache 1, 3(%[addr])           \n"
0654         "   addiu %[sets], %[sets], -1    \n"
0655         "   bnez  %[sets], 1b             \n"
0656         "   addiu %[addr], %[addr], 0x20  \n"
0657         "   li    %[val], 0x7             \n" /* *state_addr = CPU_DEAD; */
0658         "   sw    %[val], (%[state_addr]) \n"
0659         "   sync                          \n"
0660         "   cache 21, (%[state_addr])     \n" /* flush entry of *state_addr */
0661         "   .set pop                      \n"
0662         : [addr] "=&r" (addr), [val] "=&r" (val)
0663         : [state_addr] "r" (state_addr),
0664           [sets] "r" (cpu_data[smp_processor_id()].dcache.sets));
0665 
0666     __asm__ __volatile__(
0667         "   .set push                         \n"
0668         "   .set noreorder                    \n"
0669         "   .set mips64                       \n"
0670         "   mfc0  %[cpuid], $15, 1            \n"
0671         "   andi  %[cpuid], 0x3ff             \n"
0672         "   dli   %[base], 0x900000003ff01000 \n"
0673         "   andi  %[core], %[cpuid], 0x3      \n"
0674         "   sll   %[core], 8                  \n" /* get core id */
0675         "   or    %[base], %[base], %[core]   \n"
0676         "   andi  %[node], %[cpuid], 0xc      \n"
0677         "   dsll  %[node], 42                 \n" /* get node id */
0678         "   or    %[base], %[base], %[node]   \n"
0679         "   dsrl  %[node], 30                 \n" /* 15:14 */
0680         "   or    %[base], %[base], %[node]   \n"
0681         "1: li    %[count], 0x100             \n" /* wait for init loop */
0682         "2: bnez  %[count], 2b                \n" /* limit mailbox access */
0683         "   addiu %[count], -1                \n"
0684         "   ld    %[initfunc], 0x20(%[base])  \n" /* get PC via mailbox */
0685         "   beqz  %[initfunc], 1b             \n"
0686         "   nop                               \n"
0687         "   ld    $sp, 0x28(%[base])          \n" /* get SP via mailbox */
0688         "   ld    $gp, 0x30(%[base])          \n" /* get GP via mailbox */
0689         "   ld    $a1, 0x38(%[base])          \n"
0690         "   jr    %[initfunc]                 \n" /* jump to initial PC */
0691         "   nop                               \n"
0692         "   .set pop                          \n"
0693         : [core] "=&r" (core), [node] "=&r" (node),
0694           [base] "=&r" (base), [cpuid] "=&r" (cpuid),
0695           [count] "=&r" (count), [initfunc] "=&r" (initfunc)
0696         : /* No Input */
0697         : "a1");
0698 }
0699 
0700 static void loongson3_type3_play_dead(int *state_addr)
0701 {
0702     register int val;
0703     register long cpuid, core, node, count;
0704     register void *addr, *base, *initfunc;
0705 
0706     __asm__ __volatile__(
0707         "   .set push                     \n"
0708         "   .set noreorder                \n"
0709         "   li %[addr], 0x80000000        \n" /* KSEG0 */
0710         "1: cache 0, 0(%[addr])           \n" /* flush L1 ICache */
0711         "   cache 0, 1(%[addr])           \n"
0712         "   cache 0, 2(%[addr])           \n"
0713         "   cache 0, 3(%[addr])           \n"
0714         "   cache 1, 0(%[addr])           \n" /* flush L1 DCache */
0715         "   cache 1, 1(%[addr])           \n"
0716         "   cache 1, 2(%[addr])           \n"
0717         "   cache 1, 3(%[addr])           \n"
0718         "   addiu %[sets], %[sets], -1    \n"
0719         "   bnez  %[sets], 1b             \n"
0720         "   addiu %[addr], %[addr], 0x40  \n"
0721         "   li %[addr], 0x80000000        \n" /* KSEG0 */
0722         "2: cache 2, 0(%[addr])           \n" /* flush L1 VCache */
0723         "   cache 2, 1(%[addr])           \n"
0724         "   cache 2, 2(%[addr])           \n"
0725         "   cache 2, 3(%[addr])           \n"
0726         "   cache 2, 4(%[addr])           \n"
0727         "   cache 2, 5(%[addr])           \n"
0728         "   cache 2, 6(%[addr])           \n"
0729         "   cache 2, 7(%[addr])           \n"
0730         "   cache 2, 8(%[addr])           \n"
0731         "   cache 2, 9(%[addr])           \n"
0732         "   cache 2, 10(%[addr])          \n"
0733         "   cache 2, 11(%[addr])          \n"
0734         "   cache 2, 12(%[addr])          \n"
0735         "   cache 2, 13(%[addr])          \n"
0736         "   cache 2, 14(%[addr])          \n"
0737         "   cache 2, 15(%[addr])          \n"
0738         "   addiu %[vsets], %[vsets], -1  \n"
0739         "   bnez  %[vsets], 2b            \n"
0740         "   addiu %[addr], %[addr], 0x40  \n"
0741         "   li    %[val], 0x7             \n" /* *state_addr = CPU_DEAD; */
0742         "   sw    %[val], (%[state_addr]) \n"
0743         "   sync                          \n"
0744         "   cache 21, (%[state_addr])     \n" /* flush entry of *state_addr */
0745         "   .set pop                      \n"
0746         : [addr] "=&r" (addr), [val] "=&r" (val)
0747         : [state_addr] "r" (state_addr),
0748           [sets] "r" (cpu_data[smp_processor_id()].dcache.sets),
0749           [vsets] "r" (cpu_data[smp_processor_id()].vcache.sets));
0750 
0751     __asm__ __volatile__(
0752         "   .set push                         \n"
0753         "   .set noreorder                    \n"
0754         "   .set mips64                       \n"
0755         "   mfc0  %[cpuid], $15, 1            \n"
0756         "   andi  %[cpuid], 0x3ff             \n"
0757         "   dli   %[base], 0x900000003ff01000 \n"
0758         "   andi  %[core], %[cpuid], 0x3      \n"
0759         "   sll   %[core], 8                  \n" /* get core id */
0760         "   or    %[base], %[base], %[core]   \n"
0761         "   andi  %[node], %[cpuid], 0xc      \n"
0762         "   dsll  %[node], 42                 \n" /* get node id */
0763         "   or    %[base], %[base], %[node]   \n"
0764         "1: li    %[count], 0x100             \n" /* wait for init loop */
0765         "2: bnez  %[count], 2b                \n" /* limit mailbox access */
0766         "   addiu %[count], -1                \n"
0767         "   lw    %[initfunc], 0x20(%[base])  \n" /* check lower 32-bit as jump indicator */
0768         "   beqz  %[initfunc], 1b             \n"
0769         "   nop                               \n"
0770         "   ld    %[initfunc], 0x20(%[base])  \n" /* get PC (whole 64-bit) via mailbox */
0771         "   ld    $sp, 0x28(%[base])          \n" /* get SP via mailbox */
0772         "   ld    $gp, 0x30(%[base])          \n" /* get GP via mailbox */
0773         "   ld    $a1, 0x38(%[base])          \n"
0774         "   jr    %[initfunc]                 \n" /* jump to initial PC */
0775         "   nop                               \n"
0776         "   .set pop                          \n"
0777         : [core] "=&r" (core), [node] "=&r" (node),
0778           [base] "=&r" (base), [cpuid] "=&r" (cpuid),
0779           [count] "=&r" (count), [initfunc] "=&r" (initfunc)
0780         : /* No Input */
0781         : "a1");
0782 }
0783 
0784 void play_dead(void)
0785 {
0786     int prid_imp, prid_rev, *state_addr;
0787     unsigned int cpu = smp_processor_id();
0788     void (*play_dead_at_ckseg1)(int *);
0789 
0790     idle_task_exit();
0791 
0792     prid_imp = read_c0_prid() & PRID_IMP_MASK;
0793     prid_rev = read_c0_prid() & PRID_REV_MASK;
0794 
0795     if (prid_imp == PRID_IMP_LOONGSON_64G) {
0796         play_dead_at_ckseg1 =
0797             (void *)CKSEG1ADDR((unsigned long)loongson3_type3_play_dead);
0798         goto out;
0799     }
0800 
0801     switch (prid_rev) {
0802     case PRID_REV_LOONGSON3A_R1:
0803     default:
0804         play_dead_at_ckseg1 =
0805             (void *)CKSEG1ADDR((unsigned long)loongson3_type1_play_dead);
0806         break;
0807     case PRID_REV_LOONGSON3B_R1:
0808     case PRID_REV_LOONGSON3B_R2:
0809         play_dead_at_ckseg1 =
0810             (void *)CKSEG1ADDR((unsigned long)loongson3_type2_play_dead);
0811         break;
0812     case PRID_REV_LOONGSON3A_R2_0:
0813     case PRID_REV_LOONGSON3A_R2_1:
0814     case PRID_REV_LOONGSON3A_R3_0:
0815     case PRID_REV_LOONGSON3A_R3_1:
0816         play_dead_at_ckseg1 =
0817             (void *)CKSEG1ADDR((unsigned long)loongson3_type3_play_dead);
0818         break;
0819     }
0820 
0821 out:
0822     state_addr = &per_cpu(cpu_state, cpu);
0823     mb();
0824     play_dead_at_ckseg1(state_addr);
0825 }
0826 
0827 static int loongson3_disable_clock(unsigned int cpu)
0828 {
0829     uint64_t core_id = cpu_core(&cpu_data[cpu]);
0830     uint64_t package_id = cpu_data[cpu].package;
0831 
0832     if ((read_c0_prid() & PRID_REV_MASK) == PRID_REV_LOONGSON3A_R1) {
0833         LOONGSON_CHIPCFG(package_id) &= ~(1 << (12 + core_id));
0834     } else {
0835         if (!(loongson_sysconf.workarounds & WORKAROUND_CPUHOTPLUG))
0836             LOONGSON_FREQCTRL(package_id) &= ~(1 << (core_id * 4 + 3));
0837     }
0838     return 0;
0839 }
0840 
0841 static int loongson3_enable_clock(unsigned int cpu)
0842 {
0843     uint64_t core_id = cpu_core(&cpu_data[cpu]);
0844     uint64_t package_id = cpu_data[cpu].package;
0845 
0846     if ((read_c0_prid() & PRID_REV_MASK) == PRID_REV_LOONGSON3A_R1) {
0847         LOONGSON_CHIPCFG(package_id) |= 1 << (12 + core_id);
0848     } else {
0849         if (!(loongson_sysconf.workarounds & WORKAROUND_CPUHOTPLUG))
0850             LOONGSON_FREQCTRL(package_id) |= 1 << (core_id * 4 + 3);
0851     }
0852     return 0;
0853 }
0854 
0855 static int register_loongson3_notifier(void)
0856 {
0857     return cpuhp_setup_state_nocalls(CPUHP_MIPS_SOC_PREPARE,
0858                      "mips/loongson:prepare",
0859                      loongson3_enable_clock,
0860                      loongson3_disable_clock);
0861 }
0862 early_initcall(register_loongson3_notifier);
0863 
0864 #endif
0865 
0866 const struct plat_smp_ops loongson3_smp_ops = {
0867     .send_ipi_single = loongson3_send_ipi_single,
0868     .send_ipi_mask = loongson3_send_ipi_mask,
0869     .init_secondary = loongson3_init_secondary,
0870     .smp_finish = loongson3_smp_finish,
0871     .boot_secondary = loongson3_boot_secondary,
0872     .smp_setup = loongson3_smp_setup,
0873     .prepare_cpus = loongson3_prepare_cpus,
0874 #ifdef CONFIG_HOTPLUG_CPU
0875     .cpu_disable = loongson3_cpu_disable,
0876     .cpu_die = loongson3_cpu_die,
0877 #endif
0878 #ifdef CONFIG_KEXEC
0879     .kexec_nonboot_cpu = kexec_nonboot_cpu_jump,
0880 #endif
0881 };
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