loongson32/common/time.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (c) 2014 Zhang, Keguang <keguang.zhang@gmail.com>
0004  */
0005
0006 #include <linux/clk.h>
0007 #include <linux/interrupt.h>
0008 #include <linux/sizes.h>
0009 #include <asm/time.h>
0010
0011 #include <loongson1.h>
0012 #include <platform.h>
0013
0014 #ifdef CONFIG_CEVT_CSRC_LS1X
0015
0016 #if defined(CONFIG_TIMER_USE_PWM1)
0017 #define LS1X_TIMER_BASE LS1X_PWM1_BASE
0018 #define LS1X_TIMER_IRQ  LS1X_PWM1_IRQ
0019
0020 #elif defined(CONFIG_TIMER_USE_PWM2)
0021 #define LS1X_TIMER_BASE LS1X_PWM2_BASE
0022 #define LS1X_TIMER_IRQ  LS1X_PWM2_IRQ
0023
0024 #elif defined(CONFIG_TIMER_USE_PWM3)
0025 #define LS1X_TIMER_BASE LS1X_PWM3_BASE
0026 #define LS1X_TIMER_IRQ  LS1X_PWM3_IRQ
0027
0028 #else
0029 #define LS1X_TIMER_BASE LS1X_PWM0_BASE
0030 #define LS1X_TIMER_IRQ  LS1X_PWM0_IRQ
0031 #endif
0032
0033 DEFINE_RAW_SPINLOCK(ls1x_timer_lock);
0034
0035 static void __iomem *timer_reg_base;
0036 static uint32_t ls1x_jiffies_per_tick;
0037
0038 static inline void ls1x_pwmtimer_set_period(uint32_t period)
0039 {
0040     __raw_writel(period, timer_reg_base + PWM_HRC);
0041     __raw_writel(period, timer_reg_base + PWM_LRC);
0042 }
0043
0044 static inline void ls1x_pwmtimer_restart(void)
0045 {
0046     __raw_writel(0x0, timer_reg_base + PWM_CNT);
0047     __raw_writel(INT_EN | CNT_EN, timer_reg_base + PWM_CTRL);
0048 }
0049
0050 void __init ls1x_pwmtimer_init(void)
0051 {
0052     timer_reg_base = ioremap(LS1X_TIMER_BASE, SZ_16);
0053     if (!timer_reg_base)
0054         panic("Failed to remap timer registers");
0055
0056     ls1x_jiffies_per_tick = DIV_ROUND_CLOSEST(mips_hpt_frequency, HZ);
0057
0058     ls1x_pwmtimer_set_period(ls1x_jiffies_per_tick);
0059     ls1x_pwmtimer_restart();
0060 }
0061
0062 static u64 ls1x_clocksource_read(struct clocksource *cs)
0063 {
0064     unsigned long flags;
0065     int count;
0066     u32 jifs;
0067     static int old_count;
0068     static u32 old_jifs;
0069
0070     raw_spin_lock_irqsave(&ls1x_timer_lock, flags);
0071     /*
0072      * Although our caller may have the read side of xtime_lock,
0073      * this is now a seqlock, and we are cheating in this routine
0074      * by having side effects on state that we cannot undo if
0075      * there is a collision on the seqlock and our caller has to
0076      * retry.  (Namely, old_jifs and old_count.)  So we must treat
0077      * jiffies as volatile despite the lock.  We read jiffies
0078      * before latching the timer count to guarantee that although
0079      * the jiffies value might be older than the count (that is,
0080      * the counter may underflow between the last point where
0081      * jiffies was incremented and the point where we latch the
0082      * count), it cannot be newer.
0083      */
0084     jifs = jiffies;
0085     /* read the count */
0086     count = __raw_readl(timer_reg_base + PWM_CNT);
0087
0088     /*
0089      * It's possible for count to appear to go the wrong way for this
0090      * reason:
0091      *
0092      *  The timer counter underflows, but we haven't handled the resulting
0093      *  interrupt and incremented jiffies yet.
0094      *
0095      * Previous attempts to handle these cases intelligently were buggy, so
0096      * we just do the simple thing now.
0097      */
0098     if (count < old_count && jifs == old_jifs)
0099         count = old_count;
0100
0101     old_count = count;
0102     old_jifs = jifs;
0103
0104     raw_spin_unlock_irqrestore(&ls1x_timer_lock, flags);
0105
0106     return (u64) (jifs * ls1x_jiffies_per_tick) + count;
0107 }
0108
0109 static struct clocksource ls1x_clocksource = {
0110     .name       = "ls1x-pwmtimer",
0111     .read       = ls1x_clocksource_read,
0112     .mask       = CLOCKSOURCE_MASK(24),
0113     .flags      = CLOCK_SOURCE_IS_CONTINUOUS,
0114 };
0115
0116 static irqreturn_t ls1x_clockevent_isr(int irq, void *devid)
0117 {
0118     struct clock_event_device *cd = devid;
0119
0120     ls1x_pwmtimer_restart();
0121     cd->event_handler(cd);
0122
0123     return IRQ_HANDLED;
0124 }
0125
0126 static int ls1x_clockevent_set_state_periodic(struct clock_event_device *cd)
0127 {
0128     raw_spin_lock(&ls1x_timer_lock);
0129     ls1x_pwmtimer_set_period(ls1x_jiffies_per_tick);
0130     ls1x_pwmtimer_restart();
0131     __raw_writel(INT_EN | CNT_EN, timer_reg_base + PWM_CTRL);
0132     raw_spin_unlock(&ls1x_timer_lock);
0133
0134     return 0;
0135 }
0136
0137 static int ls1x_clockevent_tick_resume(struct clock_event_device *cd)
0138 {
0139     raw_spin_lock(&ls1x_timer_lock);
0140     __raw_writel(INT_EN | CNT_EN, timer_reg_base + PWM_CTRL);
0141     raw_spin_unlock(&ls1x_timer_lock);
0142
0143     return 0;
0144 }
0145
0146 static int ls1x_clockevent_set_state_shutdown(struct clock_event_device *cd)
0147 {
0148     raw_spin_lock(&ls1x_timer_lock);
0149     __raw_writel(__raw_readl(timer_reg_base + PWM_CTRL) & ~CNT_EN,
0150              timer_reg_base + PWM_CTRL);
0151     raw_spin_unlock(&ls1x_timer_lock);
0152
0153     return 0;
0154 }
0155
0156 static int ls1x_clockevent_set_next(unsigned long evt,
0157                     struct clock_event_device *cd)
0158 {
0159     raw_spin_lock(&ls1x_timer_lock);
0160     ls1x_pwmtimer_set_period(evt);
0161     ls1x_pwmtimer_restart();
0162     raw_spin_unlock(&ls1x_timer_lock);
0163
0164     return 0;
0165 }
0166
0167 static struct clock_event_device ls1x_clockevent = {
0168     .name           = "ls1x-pwmtimer",
0169     .features       = CLOCK_EVT_FEAT_PERIODIC,
0170     .rating         = 300,
0171     .irq            = LS1X_TIMER_IRQ,
0172     .set_next_event     = ls1x_clockevent_set_next,
0173     .set_state_shutdown = ls1x_clockevent_set_state_shutdown,
0174     .set_state_periodic = ls1x_clockevent_set_state_periodic,
0175     .set_state_oneshot  = ls1x_clockevent_set_state_shutdown,
0176     .tick_resume        = ls1x_clockevent_tick_resume,
0177 };
0178
0179 static void __init ls1x_time_init(void)
0180 {
0181     struct clock_event_device *cd = &ls1x_clockevent;
0182     int ret;
0183
0184     if (!mips_hpt_frequency)
0185         panic("Invalid timer clock rate");
0186
0187     ls1x_pwmtimer_init();
0188
0189     clockevent_set_clock(cd, mips_hpt_frequency);
0190     cd->max_delta_ns = clockevent_delta2ns(0xffffff, cd);
0191     cd->max_delta_ticks = 0xffffff;
0192     cd->min_delta_ns = clockevent_delta2ns(0x000300, cd);
0193     cd->min_delta_ticks = 0x000300;
0194     cd->cpumask = cpumask_of(smp_processor_id());
0195     clockevents_register_device(cd);
0196
0197     ls1x_clocksource.rating = 200 + mips_hpt_frequency / 10000000;
0198     ret = clocksource_register_hz(&ls1x_clocksource, mips_hpt_frequency);
0199     if (ret)
0200         panic(KERN_ERR "Failed to register clocksource: %d\n", ret);
0201
0202     if (request_irq(LS1X_TIMER_IRQ, ls1x_clockevent_isr,
0203             IRQF_PERCPU | IRQF_TIMER, "ls1x-pwmtimer",
0204             &ls1x_clockevent))
0205         pr_err("Failed to register ls1x-pwmtimer interrupt\n");
0206 }
0207 #endif /* CONFIG_CEVT_CSRC_LS1X */
0208
0209 void __init plat_time_init(void)
0210 {
0211     struct clk *clk = NULL;
0212
0213     /* initialize LS1X clocks */
0214     ls1x_clk_init();
0215
0216 #ifdef CONFIG_CEVT_CSRC_LS1X
0217     /* setup LS1X PWM timer */
0218     clk = clk_get(NULL, "ls1x-pwmtimer");
0219     if (IS_ERR(clk))
0220         panic("unable to get timer clock, err=%ld", PTR_ERR(clk));
0221
0222     mips_hpt_frequency = clk_get_rate(clk);
0223     ls1x_time_init();
0224 #else
0225     /* setup mips r4k timer */
0226     clk = clk_get(NULL, "cpu_clk");
0227     if (IS_ERR(clk))
0228         panic("unable to get cpu clock, err=%ld", PTR_ERR(clk));
0229
0230     mips_hpt_frequency = clk_get_rate(clk) / 2;
0231 #endif /* CONFIG_CEVT_CSRC_LS1X */
0232 }