loongson2ef/fuloong-2e/irq.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (C) 2007 Lemote Inc. & Institute of Computing Technology
0004  * Author: Fuxin Zhang, zhangfx@lemote.com
0005  */
0006 #include <linux/interrupt.h>
0007
0008 #include <asm/irq_cpu.h>
0009 #include <asm/i8259.h>
0010
0011 #include <loongson.h>
0012
0013 static void i8259_irqdispatch(void)
0014 {
0015     int irq;
0016
0017     irq = i8259_irq();
0018     if (irq >= 0)
0019         do_IRQ(irq);
0020     else
0021         spurious_interrupt();
0022 }
0023
0024 asmlinkage void mach_irq_dispatch(unsigned int pending)
0025 {
0026     if (pending & CAUSEF_IP7)
0027         do_IRQ(MIPS_CPU_IRQ_BASE + 7);
0028     else if (pending & CAUSEF_IP6) /* perf counter loverflow */
0029         return;
0030     else if (pending & CAUSEF_IP5)
0031         i8259_irqdispatch();
0032     else if (pending & CAUSEF_IP2)
0033         bonito_irqdispatch();
0034     else
0035         spurious_interrupt();
0036 }
0037
0038 void __init mach_init_irq(void)
0039 {
0040     int irq;
0041
0042     /* init all controller
0043      *   0-15     ------> i8259 interrupt
0044      *   16-23    ------> mips cpu interrupt
0045      *   32-63    ------> bonito irq
0046      */
0047
0048     /* most bonito irq should be level triggered */
0049     LOONGSON_INTEDGE = LOONGSON_ICU_SYSTEMERR | LOONGSON_ICU_MASTERERR |
0050         LOONGSON_ICU_RETRYERR | LOONGSON_ICU_MBOXES;
0051
0052     /* Sets the first-level interrupt dispatcher. */
0053     mips_cpu_irq_init();
0054     init_i8259_irqs();
0055     bonito_irq_init();
0056
0057     /* bonito irq at IP2 */
0058     irq = MIPS_CPU_IRQ_BASE + 2;
0059     if (request_irq(irq, no_action, IRQF_NO_THREAD, "cascade", NULL))
0060         pr_err("Failed to request irq %d (cascade)\n", irq);
0061     /* 8259 irq at IP5 */
0062     irq = MIPS_CPU_IRQ_BASE + 5;
0063     if (request_irq(irq, no_action, IRQF_NO_THREAD, "cascade", NULL))
0064         pr_err("Failed to request irq %d (cascade)\n", irq);
0065 }