loongson2ef/common/pci.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology
0004  * Author: Fuxin Zhang, zhangfx@lemote.com
0005  */
0006 #include <linux/pci.h>
0007
0008 #include <pci.h>
0009 #include <loongson.h>
0010
0011 static struct resource loongson_pci_mem_resource = {
0012     .name   = "pci memory space",
0013     .start  = LOONGSON_PCI_MEM_START,
0014     .end    = LOONGSON_PCI_MEM_END,
0015     .flags  = IORESOURCE_MEM,
0016 };
0017
0018 static struct resource loongson_pci_io_resource = {
0019     .name   = "pci io space",
0020     .start  = LOONGSON_PCI_IO_START,
0021     .end    = IO_SPACE_LIMIT,
0022     .flags  = IORESOURCE_IO,
0023 };
0024
0025 static struct pci_controller  loongson_pci_controller = {
0026     .pci_ops    = &loongson_pci_ops,
0027     .io_resource    = &loongson_pci_io_resource,
0028     .mem_resource   = &loongson_pci_mem_resource,
0029     .mem_offset = 0x00000000UL,
0030     .io_offset  = 0x00000000UL,
0031 };
0032
0033 static void __init setup_pcimap(void)
0034 {
0035     /*
0036      * local to PCI mapping for CPU accessing PCI space
0037      * CPU address space [256M,448M] is window for accessing pci space
0038      * we set pcimap_lo[0,1,2] to map it to pci space[0M,64M], [320M,448M]
0039      *
0040      * pcimap: PCI_MAP2  PCI_Mem_Lo2 PCI_Mem_Lo1 PCI_Mem_Lo0
0041      *       [<2G]   [384M,448M] [320M,384M] [0M,64M]
0042      */
0043     LOONGSON_PCIMAP = LOONGSON_PCIMAP_PCIMAP_2 |
0044         LOONGSON_PCIMAP_WIN(2, LOONGSON_PCILO2_BASE) |
0045         LOONGSON_PCIMAP_WIN(1, LOONGSON_PCILO1_BASE) |
0046         LOONGSON_PCIMAP_WIN(0, 0);
0047
0048     /*
0049      * PCI-DMA to local mapping: [2G,2G+256M] -> [0M,256M]
0050      */
0051     LOONGSON_PCIBASE0 = 0x80000000ul;   /* base: 2G -> mmap: 0M */
0052     /* size: 256M, burst transmission, pre-fetch enable, 64bit */
0053     LOONGSON_PCI_HIT0_SEL_L = 0xc000000cul;
0054     LOONGSON_PCI_HIT0_SEL_H = 0xfffffffful;
0055     LOONGSON_PCI_HIT1_SEL_L = 0x00000006ul; /* set this BAR as invalid */
0056     LOONGSON_PCI_HIT1_SEL_H = 0x00000000ul;
0057     LOONGSON_PCI_HIT2_SEL_L = 0x00000006ul; /* set this BAR as invalid */
0058     LOONGSON_PCI_HIT2_SEL_H = 0x00000000ul;
0059
0060     /* avoid deadlock of PCI reading/writing lock operation */
0061     LOONGSON_PCI_ISR4C = 0xd2000001ul;
0062
0063     /* can not change gnt to break pci transfer when device's gnt not
0064     deassert for some broken device */
0065     LOONGSON_PXARB_CFG = 0x00fe0105ul;
0066
0067 #ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG
0068     /*
0069      * set cpu addr window2 to map CPU address space to PCI address space
0070      */
0071     LOONGSON_ADDRWIN_CPUTOPCI(ADDRWIN_WIN2, LOONGSON_CPU_MEM_SRC,
0072         LOONGSON_PCI_MEM_DST, MMAP_CPUTOPCI_SIZE);
0073 #endif
0074 }
0075
0076 extern int sbx00_acpi_init(void);
0077
0078 static int __init pcibios_init(void)
0079 {
0080     setup_pcimap();
0081
0082     loongson_pci_controller.io_map_base = mips_io_port_base;
0083     register_pci_controller(&loongson_pci_controller);
0084
0085
0086     return 0;
0087 }
0088
0089 arch_initcall(pcibios_init);