common/cs5536/cs5536_ohci.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * the OHCI Virtual Support Module of AMD CS5536
0004  *
0005  * Copyright (C) 2007 Lemote, Inc.
0006  * Author : jlliu, liujl@lemote.com
0007  *
0008  * Copyright (C) 2009 Lemote, Inc.
0009  * Author: Wu Zhangjin, wuzhangjin@gmail.com
0010  */
0011
0012 #include <cs5536/cs5536.h>
0013 #include <cs5536/cs5536_pci.h>
0014
0015 void pci_ohci_write_reg(int reg, u32 value)
0016 {
0017     u32 hi = 0, lo = value;
0018
0019     switch (reg) {
0020     case PCI_COMMAND:
0021         _rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo);
0022         if (value & PCI_COMMAND_MASTER)
0023             hi |= PCI_COMMAND_MASTER;
0024         else
0025             hi &= ~PCI_COMMAND_MASTER;
0026
0027         if (value & PCI_COMMAND_MEMORY)
0028             hi |= PCI_COMMAND_MEMORY;
0029         else
0030             hi &= ~PCI_COMMAND_MEMORY;
0031         _wrmsr(USB_MSR_REG(USB_OHCI), hi, lo);
0032         break;
0033     case PCI_STATUS:
0034         if (value & PCI_STATUS_PARITY) {
0035             _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
0036             if (lo & SB_PARE_ERR_FLAG) {
0037                 lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG;
0038                 _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
0039             }
0040         }
0041         break;
0042     case PCI_BAR0_REG:
0043         if (value == PCI_BAR_RANGE_MASK) {
0044             _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
0045             lo |= SOFT_BAR_OHCI_FLAG;
0046             _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
0047         } else if ((value & 0x01) == 0x00) {
0048             _rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo);
0049             lo = value;
0050             _wrmsr(USB_MSR_REG(USB_OHCI), hi, lo);
0051
0052             value &= 0xfffffff0;
0053             hi = 0x40000000 | ((value & 0xff000000) >> 24);
0054             lo = 0x000fffff | ((value & 0x00fff000) << 8);
0055             _wrmsr(GLIU_MSR_REG(GLIU_P2D_BM3), hi, lo);
0056         }
0057         break;
0058     case PCI_OHCI_INT_REG:
0059         _rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo);
0060         lo &= ~(0xf << PIC_YSEL_LOW_USB_SHIFT);
0061         if (value)  /* enable all the usb interrupt in PIC */
0062             lo |= (CS5536_USB_INTR << PIC_YSEL_LOW_USB_SHIFT);
0063         _wrmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), hi, lo);
0064         break;
0065     default:
0066         break;
0067     }
0068 }
0069
0070 u32 pci_ohci_read_reg(int reg)
0071 {
0072     u32 conf_data = 0;
0073     u32 hi, lo;
0074
0075     switch (reg) {
0076     case PCI_VENDOR_ID:
0077         conf_data =
0078             CFG_PCI_VENDOR_ID(CS5536_OHCI_DEVICE_ID, CS5536_VENDOR_ID);
0079         break;
0080     case PCI_COMMAND:
0081         _rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo);
0082         if (hi & PCI_COMMAND_MASTER)
0083             conf_data |= PCI_COMMAND_MASTER;
0084         if (hi & PCI_COMMAND_MEMORY)
0085             conf_data |= PCI_COMMAND_MEMORY;
0086         break;
0087     case PCI_STATUS:
0088         conf_data |= PCI_STATUS_66MHZ;
0089         conf_data |= PCI_STATUS_FAST_BACK;
0090         _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
0091         if (lo & SB_PARE_ERR_FLAG)
0092             conf_data |= PCI_STATUS_PARITY;
0093         conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
0094         break;
0095     case PCI_CLASS_REVISION:
0096         _rdmsr(USB_MSR_REG(USB_CAP), &hi, &lo);
0097         conf_data = lo & 0x000000ff;
0098         conf_data |= (CS5536_OHCI_CLASS_CODE << 8);
0099         break;
0100     case PCI_CACHE_LINE_SIZE:
0101         conf_data =
0102             CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE,
0103                         PCI_NORMAL_LATENCY_TIMER);
0104         break;
0105     case PCI_BAR0_REG:
0106         _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
0107         if (lo & SOFT_BAR_OHCI_FLAG) {
0108             conf_data = CS5536_OHCI_RANGE |
0109                 PCI_BASE_ADDRESS_SPACE_MEMORY;
0110             lo &= ~SOFT_BAR_OHCI_FLAG;
0111             _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
0112         } else {
0113             _rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo);
0114             conf_data = lo & 0xffffff00;
0115             conf_data &= ~0x0000000f;   /* 32bit mem */
0116         }
0117         break;
0118     case PCI_CARDBUS_CIS:
0119         conf_data = PCI_CARDBUS_CIS_POINTER;
0120         break;
0121     case PCI_SUBSYSTEM_VENDOR_ID:
0122         conf_data =
0123             CFG_PCI_VENDOR_ID(CS5536_OHCI_SUB_ID, CS5536_SUB_VENDOR_ID);
0124         break;
0125     case PCI_ROM_ADDRESS:
0126         conf_data = PCI_EXPANSION_ROM_BAR;
0127         break;
0128     case PCI_CAPABILITY_LIST:
0129         conf_data = PCI_CAPLIST_USB_POINTER;
0130         break;
0131     case PCI_INTERRUPT_LINE:
0132         conf_data =
0133             CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_USB_INTR);
0134         break;
0135     case PCI_OHCI_INT_REG:
0136         _rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo);
0137         if (((lo >> PIC_YSEL_LOW_USB_SHIFT) & 0xf) == CS5536_USB_INTR)
0138             conf_data = 1;
0139         break;
0140     default:
0141         break;
0142     }
0143
0144     return conf_data;
0145 }