common/cs5536/cs5536_ehci.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * the EHCI Virtual Support Module of AMD CS5536
0004  *
0005  * Copyright (C) 2007 Lemote, Inc.
0006  * Author : jlliu, liujl@lemote.com
0007  *
0008  * Copyright (C) 2009 Lemote, Inc.
0009  * Author: Wu Zhangjin, wuzhangjin@gmail.com
0010  */
0011
0012 #include <cs5536/cs5536.h>
0013 #include <cs5536/cs5536_pci.h>
0014
0015 void pci_ehci_write_reg(int reg, u32 value)
0016 {
0017     u32 hi = 0, lo = value;
0018
0019     switch (reg) {
0020     case PCI_COMMAND:
0021         _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
0022         if (value & PCI_COMMAND_MASTER)
0023             hi |= PCI_COMMAND_MASTER;
0024         else
0025             hi &= ~PCI_COMMAND_MASTER;
0026
0027         if (value & PCI_COMMAND_MEMORY)
0028             hi |= PCI_COMMAND_MEMORY;
0029         else
0030             hi &= ~PCI_COMMAND_MEMORY;
0031         _wrmsr(USB_MSR_REG(USB_EHCI), hi, lo);
0032         break;
0033     case PCI_STATUS:
0034         if (value & PCI_STATUS_PARITY) {
0035             _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
0036             if (lo & SB_PARE_ERR_FLAG) {
0037                 lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG;
0038                 _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
0039             }
0040         }
0041         break;
0042     case PCI_BAR0_REG:
0043         if (value == PCI_BAR_RANGE_MASK) {
0044             _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
0045             lo |= SOFT_BAR_EHCI_FLAG;
0046             _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
0047         } else if ((value & 0x01) == 0x00) {
0048             _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
0049             lo = value;
0050             _wrmsr(USB_MSR_REG(USB_EHCI), hi, lo);
0051
0052             value &= 0xfffffff0;
0053             hi = 0x40000000 | ((value & 0xff000000) >> 24);
0054             lo = 0x000fffff | ((value & 0x00fff000) << 8);
0055             _wrmsr(GLIU_MSR_REG(GLIU_P2D_BM4), hi, lo);
0056         }
0057         break;
0058     case PCI_EHCI_LEGSMIEN_REG:
0059         _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
0060         hi &= 0x003f0000;
0061         hi |= (value & 0x3f) << 16;
0062         _wrmsr(USB_MSR_REG(USB_EHCI), hi, lo);
0063         break;
0064     case PCI_EHCI_FLADJ_REG:
0065         _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
0066         hi &= ~0x00003f00;
0067         hi |= value & 0x00003f00;
0068         _wrmsr(USB_MSR_REG(USB_EHCI), hi, lo);
0069         break;
0070     default:
0071         break;
0072     }
0073 }
0074
0075 u32 pci_ehci_read_reg(int reg)
0076 {
0077     u32 conf_data = 0;
0078     u32 hi, lo;
0079
0080     switch (reg) {
0081     case PCI_VENDOR_ID:
0082         conf_data =
0083             CFG_PCI_VENDOR_ID(CS5536_EHCI_DEVICE_ID, CS5536_VENDOR_ID);
0084         break;
0085     case PCI_COMMAND:
0086         _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
0087         if (hi & PCI_COMMAND_MASTER)
0088             conf_data |= PCI_COMMAND_MASTER;
0089         if (hi & PCI_COMMAND_MEMORY)
0090             conf_data |= PCI_COMMAND_MEMORY;
0091         break;
0092     case PCI_STATUS:
0093         conf_data |= PCI_STATUS_66MHZ;
0094         conf_data |= PCI_STATUS_FAST_BACK;
0095         _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
0096         if (lo & SB_PARE_ERR_FLAG)
0097             conf_data |= PCI_STATUS_PARITY;
0098         conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
0099         break;
0100     case PCI_CLASS_REVISION:
0101         _rdmsr(USB_MSR_REG(USB_CAP), &hi, &lo);
0102         conf_data = lo & 0x000000ff;
0103         conf_data |= (CS5536_EHCI_CLASS_CODE << 8);
0104         break;
0105     case PCI_CACHE_LINE_SIZE:
0106         conf_data =
0107             CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE,
0108                         PCI_NORMAL_LATENCY_TIMER);
0109         break;
0110     case PCI_BAR0_REG:
0111         _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
0112         if (lo & SOFT_BAR_EHCI_FLAG) {
0113             conf_data = CS5536_EHCI_RANGE |
0114                 PCI_BASE_ADDRESS_SPACE_MEMORY;
0115             lo &= ~SOFT_BAR_EHCI_FLAG;
0116             _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
0117         } else {
0118             _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
0119             conf_data = lo & 0xfffff000;
0120         }
0121         break;
0122     case PCI_CARDBUS_CIS:
0123         conf_data = PCI_CARDBUS_CIS_POINTER;
0124         break;
0125     case PCI_SUBSYSTEM_VENDOR_ID:
0126         conf_data =
0127             CFG_PCI_VENDOR_ID(CS5536_EHCI_SUB_ID, CS5536_SUB_VENDOR_ID);
0128         break;
0129     case PCI_ROM_ADDRESS:
0130         conf_data = PCI_EXPANSION_ROM_BAR;
0131         break;
0132     case PCI_CAPABILITY_LIST:
0133         conf_data = PCI_CAPLIST_USB_POINTER;
0134         break;
0135     case PCI_INTERRUPT_LINE:
0136         conf_data =
0137             CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_USB_INTR);
0138         break;
0139     case PCI_EHCI_LEGSMIEN_REG:
0140         _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
0141         conf_data = (hi & 0x003f0000) >> 16;
0142         break;
0143     case PCI_EHCI_LEGSMISTS_REG:
0144         _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
0145         conf_data = (hi & 0x3f000000) >> 24;
0146         break;
0147     case PCI_EHCI_FLADJ_REG:
0148         _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
0149         conf_data = hi & 0x00003f00;
0150         break;
0151     default:
0152         break;
0153     }
0154
0155     return conf_data;
0156 }