common/cs5536/cs5536_acc.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * the ACC Virtual Support Module of AMD CS5536
0004  *
0005  * Copyright (C) 2007 Lemote, Inc.
0006  * Author : jlliu, liujl@lemote.com
0007  *
0008  * Copyright (C) 2009 Lemote, Inc.
0009  * Author: Wu Zhangjin, wuzhangjin@gmail.com
0010  */
0011
0012 #include <cs5536/cs5536.h>
0013 #include <cs5536/cs5536_pci.h>
0014
0015 void pci_acc_write_reg(int reg, u32 value)
0016 {
0017     u32 hi = 0, lo = value;
0018
0019     switch (reg) {
0020     case PCI_COMMAND:
0021         _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo);
0022         if (value & PCI_COMMAND_MASTER)
0023             lo |= (0x03 << 8);
0024         else
0025             lo &= ~(0x03 << 8);
0026         _wrmsr(GLIU_MSR_REG(GLIU_PAE), hi, lo);
0027         break;
0028     case PCI_STATUS:
0029         if (value & PCI_STATUS_PARITY) {
0030             _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
0031             if (lo & SB_PARE_ERR_FLAG) {
0032                 lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG;
0033                 _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
0034             }
0035         }
0036         break;
0037     case PCI_BAR0_REG:
0038         if (value == PCI_BAR_RANGE_MASK) {
0039             _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
0040             lo |= SOFT_BAR_ACC_FLAG;
0041             _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
0042         } else if (value & 0x01) {
0043             value &= 0xfffffffc;
0044             hi = 0xA0000000 | ((value & 0x000ff000) >> 12);
0045             lo = 0x000fff80 | ((value & 0x00000fff) << 20);
0046             _wrmsr(GLIU_MSR_REG(GLIU_IOD_BM1), hi, lo);
0047         }
0048         break;
0049     case PCI_ACC_INT_REG:
0050         _rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo);
0051         /* disable all the usb interrupt in PIC */
0052         lo &= ~(0xf << PIC_YSEL_LOW_ACC_SHIFT);
0053         if (value)  /* enable all the acc interrupt in PIC */
0054             lo |= (CS5536_ACC_INTR << PIC_YSEL_LOW_ACC_SHIFT);
0055         _wrmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), hi, lo);
0056         break;
0057     default:
0058         break;
0059     }
0060 }
0061
0062 u32 pci_acc_read_reg(int reg)
0063 {
0064     u32 hi, lo;
0065     u32 conf_data = 0;
0066
0067     switch (reg) {
0068     case PCI_VENDOR_ID:
0069         conf_data =
0070             CFG_PCI_VENDOR_ID(CS5536_ACC_DEVICE_ID, CS5536_VENDOR_ID);
0071         break;
0072     case PCI_COMMAND:
0073         _rdmsr(GLIU_MSR_REG(GLIU_IOD_BM1), &hi, &lo);
0074         if (((lo & 0xfff00000) || (hi & 0x000000ff))
0075             && ((hi & 0xf0000000) == 0xa0000000))
0076             conf_data |= PCI_COMMAND_IO;
0077         _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo);
0078         if ((lo & 0x300) == 0x300)
0079             conf_data |= PCI_COMMAND_MASTER;
0080         break;
0081     case PCI_STATUS:
0082         conf_data |= PCI_STATUS_66MHZ;
0083         conf_data |= PCI_STATUS_FAST_BACK;
0084         _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
0085         if (lo & SB_PARE_ERR_FLAG)
0086             conf_data |= PCI_STATUS_PARITY;
0087         conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
0088         break;
0089     case PCI_CLASS_REVISION:
0090         _rdmsr(ACC_MSR_REG(ACC_CAP), &hi, &lo);
0091         conf_data = lo & 0x000000ff;
0092         conf_data |= (CS5536_ACC_CLASS_CODE << 8);
0093         break;
0094     case PCI_CACHE_LINE_SIZE:
0095         conf_data =
0096             CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE,
0097                         PCI_NORMAL_LATENCY_TIMER);
0098         break;
0099     case PCI_BAR0_REG:
0100         _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
0101         if (lo & SOFT_BAR_ACC_FLAG) {
0102             conf_data = CS5536_ACC_RANGE |
0103                 PCI_BASE_ADDRESS_SPACE_IO;
0104             lo &= ~SOFT_BAR_ACC_FLAG;
0105             _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
0106         } else {
0107             _rdmsr(GLIU_MSR_REG(GLIU_IOD_BM1), &hi, &lo);
0108             conf_data = (hi & 0x000000ff) << 12;
0109             conf_data |= (lo & 0xfff00000) >> 20;
0110             conf_data |= 0x01;
0111             conf_data &= ~0x02;
0112         }
0113         break;
0114     case PCI_CARDBUS_CIS:
0115         conf_data = PCI_CARDBUS_CIS_POINTER;
0116         break;
0117     case PCI_SUBSYSTEM_VENDOR_ID:
0118         conf_data =
0119             CFG_PCI_VENDOR_ID(CS5536_ACC_SUB_ID, CS5536_SUB_VENDOR_ID);
0120         break;
0121     case PCI_ROM_ADDRESS:
0122         conf_data = PCI_EXPANSION_ROM_BAR;
0123         break;
0124     case PCI_CAPABILITY_LIST:
0125         conf_data = PCI_CAPLIST_USB_POINTER;
0126         break;
0127     case PCI_INTERRUPT_LINE:
0128         conf_data =
0129             CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_ACC_INTR);
0130         break;
0131     default:
0132         break;
0133     }
0134
0135     return conf_data;
0136 }