lantiq/xway/sysctrl.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *
0004  *  Copyright (C) 2011-2012 John Crispin <john@phrozen.org>
0005  *  Copyright (C) 2013-2015 Lantiq Beteiligungs-GmbH & Co.KG
0006  */
0007
0008 #include <linux/ioport.h>
0009 #include <linux/export.h>
0010 #include <linux/clkdev.h>
0011 #include <linux/spinlock.h>
0012 #include <linux/of.h>
0013 #include <linux/of_platform.h>
0014 #include <linux/of_address.h>
0015
0016 #include <lantiq_soc.h>
0017
0018 #include "../clk.h"
0019 #include "../prom.h"
0020
0021 /* clock control register for legacy */
0022 #define CGU_IFCCR   0x0018
0023 #define CGU_IFCCR_VR9   0x0024
0024 /* system clock register for legacy */
0025 #define CGU_SYS     0x0010
0026 /* pci control register */
0027 #define CGU_PCICR   0x0034
0028 #define CGU_PCICR_VR9   0x0038
0029 /* ephy configuration register */
0030 #define CGU_EPHY    0x10
0031
0032 /* Legacy PMU register for ar9, ase, danube */
0033 /* power control register */
0034 #define PMU_PWDCR   0x1C
0035 /* power status register */
0036 #define PMU_PWDSR   0x20
0037 /* power control register */
0038 #define PMU_PWDCR1  0x24
0039 /* power status register */
0040 #define PMU_PWDSR1  0x28
0041 /* power control register */
0042 #define PWDCR(x) ((x) ? (PMU_PWDCR1) : (PMU_PWDCR))
0043 /* power status register */
0044 #define PWDSR(x) ((x) ? (PMU_PWDSR1) : (PMU_PWDSR))
0045
0046
0047 /* PMU register for ar10 and grx390 */
0048
0049 /* First register set */
0050 #define PMU_CLK_SR  0x20 /* status */
0051 #define PMU_CLK_CR_A    0x24 /* Enable */
0052 #define PMU_CLK_CR_B    0x28 /* Disable */
0053 /* Second register set */
0054 #define PMU_CLK_SR1 0x30 /* status */
0055 #define PMU_CLK_CR1_A   0x34 /* Enable */
0056 #define PMU_CLK_CR1_B   0x38 /* Disable */
0057 /* Third register set */
0058 #define PMU_ANA_SR  0x40 /* status */
0059 #define PMU_ANA_CR_A    0x44 /* Enable */
0060 #define PMU_ANA_CR_B    0x48 /* Disable */
0061
0062 /* Status */
0063 static u32 pmu_clk_sr[] = {
0064     PMU_CLK_SR,
0065     PMU_CLK_SR1,
0066     PMU_ANA_SR,
0067 };
0068
0069 /* Enable */
0070 static u32 pmu_clk_cr_a[] = {
0071     PMU_CLK_CR_A,
0072     PMU_CLK_CR1_A,
0073     PMU_ANA_CR_A,
0074 };
0075
0076 /* Disable */
0077 static u32 pmu_clk_cr_b[] = {
0078     PMU_CLK_CR_B,
0079     PMU_CLK_CR1_B,
0080     PMU_ANA_CR_B,
0081 };
0082
0083 #define PWDCR_EN_XRX(x)     (pmu_clk_cr_a[(x)])
0084 #define PWDCR_DIS_XRX(x)    (pmu_clk_cr_b[(x)])
0085 #define PWDSR_XRX(x)        (pmu_clk_sr[(x)])
0086
0087 /* clock gates that we can en/disable */
0088 #define PMU_USB0_P  BIT(0)
0089 #define PMU_ASE_SDIO    BIT(2) /* ASE special */
0090 #define PMU_PCI     BIT(4)
0091 #define PMU_DMA     BIT(5)
0092 #define PMU_USB0    BIT(6)
0093 #define PMU_ASC0    BIT(7)
0094 #define PMU_EPHY    BIT(7)  /* ase */
0095 #define PMU_USIF    BIT(7) /* from vr9 until grx390 */
0096 #define PMU_SPI     BIT(8)
0097 #define PMU_DFE     BIT(9)
0098 #define PMU_EBU     BIT(10)
0099 #define PMU_STP     BIT(11)
0100 #define PMU_GPT     BIT(12)
0101 #define PMU_AHBS    BIT(13) /* vr9 */
0102 #define PMU_FPI     BIT(14)
0103 #define PMU_AHBM    BIT(15)
0104 #define PMU_SDIO    BIT(16) /* danube, ar9, vr9 */
0105 #define PMU_ASC1    BIT(17)
0106 #define PMU_PPE_QSB BIT(18)
0107 #define PMU_PPE_SLL01   BIT(19)
0108 #define PMU_DEU     BIT(20)
0109 #define PMU_PPE_TC  BIT(21)
0110 #define PMU_PPE_EMA BIT(22)
0111 #define PMU_PPE_DPLUM   BIT(23)
0112 #define PMU_PPE_DP  BIT(23)
0113 #define PMU_PPE_DPLUS   BIT(24)
0114 #define PMU_USB1_P  BIT(26)
0115 #define PMU_GPHY3   BIT(26) /* grx390 */
0116 #define PMU_USB1    BIT(27)
0117 #define PMU_SWITCH  BIT(28)
0118 #define PMU_PPE_TOP BIT(29)
0119 #define PMU_GPHY0   BIT(29) /* ar10, xrx390 */
0120 #define PMU_GPHY    BIT(30)
0121 #define PMU_GPHY1   BIT(30) /* ar10, xrx390 */
0122 #define PMU_PCIE_CLK    BIT(31)
0123 #define PMU_GPHY2   BIT(31) /* ar10, xrx390 */
0124
0125 #define PMU1_PCIE_PHY   BIT(0)  /* vr9-specific,moved in ar10/grx390 */
0126 #define PMU1_PCIE_CTL   BIT(1)
0127 #define PMU1_PCIE_PDI   BIT(4)
0128 #define PMU1_PCIE_MSI   BIT(5)
0129 #define PMU1_CKE    BIT(6)
0130 #define PMU1_PCIE1_CTL  BIT(17)
0131 #define PMU1_PCIE1_PDI  BIT(20)
0132 #define PMU1_PCIE1_MSI  BIT(21)
0133 #define PMU1_PCIE2_CTL  BIT(25)
0134 #define PMU1_PCIE2_PDI  BIT(26)
0135 #define PMU1_PCIE2_MSI  BIT(27)
0136
0137 #define PMU_ANALOG_USB0_P   BIT(0)
0138 #define PMU_ANALOG_USB1_P   BIT(1)
0139 #define PMU_ANALOG_PCIE0_P  BIT(8)
0140 #define PMU_ANALOG_PCIE1_P  BIT(9)
0141 #define PMU_ANALOG_PCIE2_P  BIT(10)
0142 #define PMU_ANALOG_DSL_AFE  BIT(16)
0143 #define PMU_ANALOG_DCDC_2V5 BIT(17)
0144 #define PMU_ANALOG_DCDC_1VX BIT(18)
0145 #define PMU_ANALOG_DCDC_1V0 BIT(19)
0146
0147 #define pmu_w32(x, y)   ltq_w32((x), pmu_membase + (y))
0148 #define pmu_r32(x)  ltq_r32(pmu_membase + (x))
0149
0150 static void __iomem *pmu_membase;
0151 void __iomem *ltq_cgu_membase;
0152 void __iomem *ltq_ebu_membase;
0153
0154 static u32 ifccr = CGU_IFCCR;
0155 static u32 pcicr = CGU_PCICR;
0156
0157 static DEFINE_SPINLOCK(g_pmu_lock);
0158
0159 /* legacy function kept alive to ease clkdev transition */
0160 void ltq_pmu_enable(unsigned int module)
0161 {
0162     int retry = 1000000;
0163
0164     spin_lock(&g_pmu_lock);
0165     pmu_w32(pmu_r32(PMU_PWDCR) & ~module, PMU_PWDCR);
0166     do {} while (--retry && (pmu_r32(PMU_PWDSR) & module));
0167     spin_unlock(&g_pmu_lock);
0168
0169     if (!retry)
0170         panic("activating PMU module failed!");
0171 }
0172 EXPORT_SYMBOL(ltq_pmu_enable);
0173
0174 /* legacy function kept alive to ease clkdev transition */
0175 void ltq_pmu_disable(unsigned int module)
0176 {
0177     int retry = 1000000;
0178
0179     spin_lock(&g_pmu_lock);
0180     pmu_w32(pmu_r32(PMU_PWDCR) | module, PMU_PWDCR);
0181     do {} while (--retry && (!(pmu_r32(PMU_PWDSR) & module)));
0182     spin_unlock(&g_pmu_lock);
0183
0184     if (!retry)
0185         pr_warn("deactivating PMU module failed!");
0186 }
0187 EXPORT_SYMBOL(ltq_pmu_disable);
0188
0189 /* enable a hw clock */
0190 static int cgu_enable(struct clk *clk)
0191 {
0192     ltq_cgu_w32(ltq_cgu_r32(ifccr) | clk->bits, ifccr);
0193     return 0;
0194 }
0195
0196 /* disable a hw clock */
0197 static void cgu_disable(struct clk *clk)
0198 {
0199     ltq_cgu_w32(ltq_cgu_r32(ifccr) & ~clk->bits, ifccr);
0200 }
0201
0202 /* enable a clock gate */
0203 static int pmu_enable(struct clk *clk)
0204 {
0205     int retry = 1000000;
0206
0207     if (of_machine_is_compatible("lantiq,ar10")
0208         || of_machine_is_compatible("lantiq,grx390")) {
0209         pmu_w32(clk->bits, PWDCR_EN_XRX(clk->module));
0210         do {} while (--retry &&
0211                  (!(pmu_r32(PWDSR_XRX(clk->module)) & clk->bits)));
0212
0213     } else {
0214         spin_lock(&g_pmu_lock);
0215         pmu_w32(pmu_r32(PWDCR(clk->module)) & ~clk->bits,
0216                 PWDCR(clk->module));
0217         do {} while (--retry &&
0218                  (pmu_r32(PWDSR(clk->module)) & clk->bits));
0219         spin_unlock(&g_pmu_lock);
0220     }
0221
0222     if (!retry)
0223         panic("activating PMU module failed!");
0224
0225     return 0;
0226 }
0227
0228 /* disable a clock gate */
0229 static void pmu_disable(struct clk *clk)
0230 {
0231     int retry = 1000000;
0232
0233     if (of_machine_is_compatible("lantiq,ar10")
0234         || of_machine_is_compatible("lantiq,grx390")) {
0235         pmu_w32(clk->bits, PWDCR_DIS_XRX(clk->module));
0236         do {} while (--retry &&
0237                  (pmu_r32(PWDSR_XRX(clk->module)) & clk->bits));
0238     } else {
0239         spin_lock(&g_pmu_lock);
0240         pmu_w32(pmu_r32(PWDCR(clk->module)) | clk->bits,
0241                 PWDCR(clk->module));
0242         do {} while (--retry &&
0243                  (!(pmu_r32(PWDSR(clk->module)) & clk->bits)));
0244         spin_unlock(&g_pmu_lock);
0245     }
0246
0247     if (!retry)
0248         pr_warn("deactivating PMU module failed!");
0249 }
0250
0251 /* the pci enable helper */
0252 static int pci_enable(struct clk *clk)
0253 {
0254     unsigned int val = ltq_cgu_r32(ifccr);
0255     /* set bus clock speed */
0256     if (of_machine_is_compatible("lantiq,ar9") ||
0257             of_machine_is_compatible("lantiq,vr9")) {
0258         val &= ~0x1f00000;
0259         if (clk->rate == CLOCK_33M)
0260             val |= 0xe00000;
0261         else
0262             val |= 0x700000; /* 62.5M */
0263     } else {
0264         val &= ~0xf00000;
0265         if (clk->rate == CLOCK_33M)
0266             val |= 0x800000;
0267         else
0268             val |= 0x400000; /* 62.5M */
0269     }
0270     ltq_cgu_w32(val, ifccr);
0271     pmu_enable(clk);
0272     return 0;
0273 }
0274
0275 /* enable the external clock as a source */
0276 static int pci_ext_enable(struct clk *clk)
0277 {
0278     ltq_cgu_w32(ltq_cgu_r32(ifccr) & ~(1 << 16), ifccr);
0279     ltq_cgu_w32((1 << 30), pcicr);
0280     return 0;
0281 }
0282
0283 /* disable the external clock as a source */
0284 static void pci_ext_disable(struct clk *clk)
0285 {
0286     ltq_cgu_w32(ltq_cgu_r32(ifccr) | (1 << 16), ifccr);
0287     ltq_cgu_w32((1 << 31) | (1 << 30), pcicr);
0288 }
0289
0290 /* enable a clockout source */
0291 static int clkout_enable(struct clk *clk)
0292 {
0293     int i;
0294
0295     /* get the correct rate */
0296     for (i = 0; i < 4; i++) {
0297         if (clk->rates[i] == clk->rate) {
0298             int shift = 14 - (2 * clk->module);
0299             int enable = 7 - clk->module;
0300             unsigned int val = ltq_cgu_r32(ifccr);
0301
0302             val &= ~(3 << shift);
0303             val |= i << shift;
0304             val |= enable;
0305             ltq_cgu_w32(val, ifccr);
0306             return 0;
0307         }
0308     }
0309     return -1;
0310 }
0311
0312 /* manage the clock gates via PMU */
0313 static void clkdev_add_pmu(const char *dev, const char *con, bool deactivate,
0314                unsigned int module, unsigned int bits)
0315 {
0316     struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
0317
0318     if (!clk)
0319         return;
0320     clk->cl.dev_id = dev;
0321     clk->cl.con_id = con;
0322     clk->cl.clk = clk;
0323     clk->enable = pmu_enable;
0324     clk->disable = pmu_disable;
0325     clk->module = module;
0326     clk->bits = bits;
0327     if (deactivate) {
0328         /*
0329          * Disable it during the initialization. Module should enable
0330          * when used
0331          */
0332         pmu_disable(clk);
0333     }
0334     clkdev_add(&clk->cl);
0335 }
0336
0337 /* manage the clock generator */
0338 static void clkdev_add_cgu(const char *dev, const char *con,
0339                     unsigned int bits)
0340 {
0341     struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
0342
0343     if (!clk)
0344         return;
0345     clk->cl.dev_id = dev;
0346     clk->cl.con_id = con;
0347     clk->cl.clk = clk;
0348     clk->enable = cgu_enable;
0349     clk->disable = cgu_disable;
0350     clk->bits = bits;
0351     clkdev_add(&clk->cl);
0352 }
0353
0354 /* pci needs its own enable function as the setup is a bit more complex */
0355 static unsigned long valid_pci_rates[] = {CLOCK_33M, CLOCK_62_5M, 0};
0356
0357 static void clkdev_add_pci(void)
0358 {
0359     struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
0360     struct clk *clk_ext = kzalloc(sizeof(struct clk), GFP_KERNEL);
0361
0362     /* main pci clock */
0363     if (clk) {
0364         clk->cl.dev_id = "17000000.pci";
0365         clk->cl.con_id = NULL;
0366         clk->cl.clk = clk;
0367         clk->rate = CLOCK_33M;
0368         clk->rates = valid_pci_rates;
0369         clk->enable = pci_enable;
0370         clk->disable = pmu_disable;
0371         clk->module = 0;
0372         clk->bits = PMU_PCI;
0373         clkdev_add(&clk->cl);
0374     }
0375
0376     /* use internal/external bus clock */
0377     if (clk_ext) {
0378         clk_ext->cl.dev_id = "17000000.pci";
0379         clk_ext->cl.con_id = "external";
0380         clk_ext->cl.clk = clk_ext;
0381         clk_ext->enable = pci_ext_enable;
0382         clk_ext->disable = pci_ext_disable;
0383         clkdev_add(&clk_ext->cl);
0384     }
0385 }
0386
0387 /* xway socs can generate clocks on gpio pins */
0388 static unsigned long valid_clkout_rates[4][5] = {
0389     {CLOCK_32_768K, CLOCK_1_536M, CLOCK_2_5M, CLOCK_12M, 0},
0390     {CLOCK_40M, CLOCK_12M, CLOCK_24M, CLOCK_48M, 0},
0391     {CLOCK_25M, CLOCK_40M, CLOCK_30M, CLOCK_60M, 0},
0392     {CLOCK_12M, CLOCK_50M, CLOCK_32_768K, CLOCK_25M, 0},
0393 };
0394
0395 static void clkdev_add_clkout(void)
0396 {
0397     int i;
0398
0399     for (i = 0; i < 4; i++) {
0400         struct clk *clk;
0401         char *name;
0402
0403         name = kzalloc(sizeof("clkout0"), GFP_KERNEL);
0404         if (!name)
0405             continue;
0406         sprintf(name, "clkout%d", i);
0407
0408         clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
0409         if (!clk) {
0410             kfree(name);
0411             continue;
0412         }
0413         clk->cl.dev_id = "1f103000.cgu";
0414         clk->cl.con_id = name;
0415         clk->cl.clk = clk;
0416         clk->rate = 0;
0417         clk->rates = valid_clkout_rates[i];
0418         clk->enable = clkout_enable;
0419         clk->module = i;
0420         clkdev_add(&clk->cl);
0421     }
0422 }
0423
0424 /* bring up all register ranges that we need for basic system control */
0425 void __init ltq_soc_init(void)
0426 {
0427     struct resource res_pmu, res_cgu, res_ebu;
0428     struct device_node *np_pmu =
0429             of_find_compatible_node(NULL, NULL, "lantiq,pmu-xway");
0430     struct device_node *np_cgu =
0431             of_find_compatible_node(NULL, NULL, "lantiq,cgu-xway");
0432     struct device_node *np_ebu =
0433             of_find_compatible_node(NULL, NULL, "lantiq,ebu-xway");
0434
0435     /* check if all the core register ranges are available */
0436     if (!np_pmu || !np_cgu || !np_ebu)
0437         panic("Failed to load core nodes from devicetree");
0438
0439     if (of_address_to_resource(np_pmu, 0, &res_pmu) ||
0440             of_address_to_resource(np_cgu, 0, &res_cgu) ||
0441             of_address_to_resource(np_ebu, 0, &res_ebu))
0442         panic("Failed to get core resources");
0443
0444     of_node_put(np_pmu);
0445     of_node_put(np_cgu);
0446     of_node_put(np_ebu);
0447
0448     if (!request_mem_region(res_pmu.start, resource_size(&res_pmu),
0449                 res_pmu.name) ||
0450         !request_mem_region(res_cgu.start, resource_size(&res_cgu),
0451                 res_cgu.name) ||
0452         !request_mem_region(res_ebu.start, resource_size(&res_ebu),
0453                 res_ebu.name))
0454         pr_err("Failed to request core resources");
0455
0456     pmu_membase = ioremap(res_pmu.start, resource_size(&res_pmu));
0457     ltq_cgu_membase = ioremap(res_cgu.start,
0458                         resource_size(&res_cgu));
0459     ltq_ebu_membase = ioremap(res_ebu.start,
0460                         resource_size(&res_ebu));
0461     if (!pmu_membase || !ltq_cgu_membase || !ltq_ebu_membase)
0462         panic("Failed to remap core resources");
0463
0464     /* make sure to unprotect the memory region where flash is located */
0465     ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0);
0466
0467     /* add our generic xway clocks */
0468     clkdev_add_pmu("10000000.fpi", NULL, 0, 0, PMU_FPI);
0469     clkdev_add_pmu("1e100a00.gptu", NULL, 1, 0, PMU_GPT);
0470     clkdev_add_pmu("1e100bb0.stp", NULL, 1, 0, PMU_STP);
0471     clkdev_add_pmu("1e100c00.serial", NULL, 0, 0, PMU_ASC1);
0472     clkdev_add_pmu("1e104100.dma", NULL, 1, 0, PMU_DMA);
0473     clkdev_add_pmu("1e100800.spi", NULL, 1, 0, PMU_SPI);
0474     clkdev_add_pmu("1e105300.ebu", NULL, 0, 0, PMU_EBU);
0475     clkdev_add_clkout();
0476
0477     /* add the soc dependent clocks */
0478     if (of_machine_is_compatible("lantiq,vr9")) {
0479         ifccr = CGU_IFCCR_VR9;
0480         pcicr = CGU_PCICR_VR9;
0481     } else {
0482         clkdev_add_pmu("1e180000.etop", NULL, 1, 0, PMU_PPE);
0483     }
0484
0485     if (!of_machine_is_compatible("lantiq,ase"))
0486         clkdev_add_pci();
0487
0488     if (of_machine_is_compatible("lantiq,grx390") ||
0489         of_machine_is_compatible("lantiq,ar10")) {
0490         clkdev_add_pmu("1e108000.switch", "gphy0", 0, 0, PMU_GPHY0);
0491         clkdev_add_pmu("1e108000.switch", "gphy1", 0, 0, PMU_GPHY1);
0492         clkdev_add_pmu("1e108000.switch", "gphy2", 0, 0, PMU_GPHY2);
0493         clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 2, PMU_ANALOG_USB0_P);
0494         clkdev_add_pmu("1f203034.usb2-phy", "phy", 1, 2, PMU_ANALOG_USB1_P);
0495         /* rc 0 */
0496         clkdev_add_pmu("1f106800.phy", "phy", 1, 2, PMU_ANALOG_PCIE0_P);
0497         clkdev_add_pmu("1d900000.pcie", "msi", 1, 1, PMU1_PCIE_MSI);
0498         clkdev_add_pmu("1f106800.phy", "pdi", 1, 1, PMU1_PCIE_PDI);
0499         clkdev_add_pmu("1d900000.pcie", "ctl", 1, 1, PMU1_PCIE_CTL);
0500         /* rc 1 */
0501         clkdev_add_pmu("1f700400.phy", "phy", 1, 2, PMU_ANALOG_PCIE1_P);
0502         clkdev_add_pmu("19000000.pcie", "msi", 1, 1, PMU1_PCIE1_MSI);
0503         clkdev_add_pmu("1f700400.phy", "pdi", 1, 1, PMU1_PCIE1_PDI);
0504         clkdev_add_pmu("19000000.pcie", "ctl", 1, 1, PMU1_PCIE1_CTL);
0505     }
0506
0507     if (of_machine_is_compatible("lantiq,ase")) {
0508         if (ltq_cgu_r32(CGU_SYS) & (1 << 5))
0509             clkdev_add_static(CLOCK_266M, CLOCK_133M,
0510                         CLOCK_133M, CLOCK_266M);
0511         else
0512             clkdev_add_static(CLOCK_133M, CLOCK_133M,
0513                         CLOCK_133M, CLOCK_133M);
0514         clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0);
0515         clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 0, PMU_USB0_P);
0516         clkdev_add_pmu("1e180000.etop", "ppe", 1, 0, PMU_PPE);
0517         clkdev_add_cgu("1e180000.etop", "ephycgu", CGU_EPHY);
0518         clkdev_add_pmu("1e180000.etop", "ephy", 1, 0, PMU_EPHY);
0519         clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_ASE_SDIO);
0520         clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
0521     } else if (of_machine_is_compatible("lantiq,grx390")) {
0522         clkdev_add_static(ltq_grx390_cpu_hz(), ltq_grx390_fpi_hz(),
0523                   ltq_grx390_fpi_hz(), ltq_grx390_pp32_hz());
0524         clkdev_add_pmu("1e108000.switch", "gphy3", 0, 0, PMU_GPHY3);
0525         clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0);
0526         clkdev_add_pmu("1e106000.usb", "otg", 1, 0, PMU_USB1);
0527         /* rc 2 */
0528         clkdev_add_pmu("1f106a00.pcie", "phy", 1, 2, PMU_ANALOG_PCIE2_P);
0529         clkdev_add_pmu("1a800000.pcie", "msi", 1, 1, PMU1_PCIE2_MSI);
0530         clkdev_add_pmu("1f106a00.pcie", "pdi", 1, 1, PMU1_PCIE2_PDI);
0531         clkdev_add_pmu("1a800000.pcie", "ctl", 1, 1, PMU1_PCIE2_CTL);
0532         clkdev_add_pmu("1e10b308.eth", NULL, 0, 0, PMU_SWITCH | PMU_PPE_DP);
0533         clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF);
0534         clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
0535     } else if (of_machine_is_compatible("lantiq,ar10")) {
0536         clkdev_add_static(ltq_ar10_cpu_hz(), ltq_ar10_fpi_hz(),
0537                   ltq_ar10_fpi_hz(), ltq_ar10_pp32_hz());
0538         clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0);
0539         clkdev_add_pmu("1e106000.usb", "otg", 1, 0, PMU_USB1);
0540         clkdev_add_pmu("1e10b308.eth", NULL, 0, 0, PMU_SWITCH |
0541                    PMU_PPE_DP | PMU_PPE_TC);
0542         clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF);
0543         clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
0544         clkdev_add_pmu("1e116000.mei", "afe", 1, 2, PMU_ANALOG_DSL_AFE);
0545         clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
0546     } else if (of_machine_is_compatible("lantiq,vr9")) {
0547         clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(),
0548                 ltq_vr9_fpi_hz(), ltq_vr9_pp32_hz());
0549         clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 0, PMU_USB0_P);
0550         clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0 | PMU_AHBM);
0551         clkdev_add_pmu("1f203034.usb2-phy", "phy", 1, 0, PMU_USB1_P);
0552         clkdev_add_pmu("1e106000.usb", "otg", 1, 0, PMU_USB1 | PMU_AHBM);
0553         clkdev_add_pmu("1f106800.phy", "phy", 1, 1, PMU1_PCIE_PHY);
0554         clkdev_add_pmu("1d900000.pcie", "bus", 1, 0, PMU_PCIE_CLK);
0555         clkdev_add_pmu("1d900000.pcie", "msi", 1, 1, PMU1_PCIE_MSI);
0556         clkdev_add_pmu("1f106800.phy", "pdi", 1, 1, PMU1_PCIE_PDI);
0557         clkdev_add_pmu("1d900000.pcie", "ctl", 1, 1, PMU1_PCIE_CTL);
0558         clkdev_add_pmu(NULL, "ahb", 1, 0, PMU_AHBM | PMU_AHBS);
0559
0560         clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF);
0561         clkdev_add_pmu("1e10b308.eth", NULL, 0, 0,
0562                 PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM |
0563                 PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 |
0564                 PMU_PPE_QSB | PMU_PPE_TOP);
0565         clkdev_add_pmu("1e108000.switch", "gphy0", 0, 0, PMU_GPHY);
0566         clkdev_add_pmu("1e108000.switch", "gphy1", 0, 0, PMU_GPHY);
0567         clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
0568         clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
0569         clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
0570     } else if (of_machine_is_compatible("lantiq,ar9")) {
0571         clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(),
0572                 ltq_ar9_fpi_hz(), CLOCK_250M);
0573         clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 0, PMU_USB0_P);
0574         clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0 | PMU_AHBM);
0575         clkdev_add_pmu("1f203034.usb2-phy", "phy", 1, 0, PMU_USB1_P);
0576         clkdev_add_pmu("1e106000.usb", "otg", 1, 0, PMU_USB1 | PMU_AHBM);
0577         clkdev_add_pmu("1e180000.etop", "switch", 1, 0, PMU_SWITCH);
0578         clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
0579         clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
0580         clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
0581         clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0);
0582     } else {
0583         clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),
0584                 ltq_danube_fpi_hz(), ltq_danube_pp32_hz());
0585         clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0 | PMU_AHBM);
0586         clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 0, PMU_USB0_P);
0587         clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
0588         clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
0589         clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
0590         clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0);
0591     }
0592 }