lantiq/xway/gptu.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *
0004  *  Copyright (C) 2012 John Crispin <john@phrozen.org>
0005  *  Copyright (C) 2012 Lantiq GmbH
0006  */
0007
0008 #include <linux/interrupt.h>
0009 #include <linux/ioport.h>
0010 #include <linux/init.h>
0011 #include <linux/of_platform.h>
0012 #include <linux/of_irq.h>
0013
0014 #include <lantiq_soc.h>
0015 #include "../clk.h"
0016
0017 /* the magic ID byte of the core */
0018 #define GPTU_MAGIC  0x59
0019 /* clock control register */
0020 #define GPTU_CLC    0x00
0021 /* id register */
0022 #define GPTU_ID     0x08
0023 /* interrupt node enable */
0024 #define GPTU_IRNEN  0xf4
0025 /* interrupt control register */
0026 #define GPTU_IRCR   0xf8
0027 /* interrupt capture register */
0028 #define GPTU_IRNCR  0xfc
0029 /* there are 3 identical blocks of 2 timers. calculate register offsets */
0030 #define GPTU_SHIFT(x)   (x % 2 ? 4 : 0)
0031 #define GPTU_BASE(x)    (((x >> 1) * 0x20) + 0x10)
0032 /* timer control register */
0033 #define GPTU_CON(x) (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x00)
0034 /* timer auto reload register */
0035 #define GPTU_RUN(x) (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x08)
0036 /* timer manual reload register */
0037 #define GPTU_RLD(x) (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x10)
0038 /* timer count register */
0039 #define GPTU_CNT(x) (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x18)
0040
0041 /* GPTU_CON(x) */
0042 #define CON_CNT     BIT(2)
0043 #define CON_EDGE_ANY    (BIT(7) | BIT(6))
0044 #define CON_SYNC    BIT(8)
0045 #define CON_CLK_INT BIT(10)
0046
0047 /* GPTU_RUN(x) */
0048 #define RUN_SEN     BIT(0)
0049 #define RUN_RL      BIT(2)
0050
0051 /* set clock to runmode */
0052 #define CLC_RMC     BIT(8)
0053 /* bring core out of suspend */
0054 #define CLC_SUSPEND BIT(4)
0055 /* the disable bit */
0056 #define CLC_DISABLE BIT(0)
0057
0058 #define gptu_w32(x, y)  ltq_w32((x), gptu_membase + (y))
0059 #define gptu_r32(x) ltq_r32(gptu_membase + (x))
0060
0061 enum gptu_timer {
0062     TIMER1A = 0,
0063     TIMER1B,
0064     TIMER2A,
0065     TIMER2B,
0066     TIMER3A,
0067     TIMER3B
0068 };
0069
0070 static void __iomem *gptu_membase;
0071 static struct resource irqres[6];
0072
0073 static irqreturn_t timer_irq_handler(int irq, void *priv)
0074 {
0075     int timer = irq - irqres[0].start;
0076     gptu_w32(1 << timer, GPTU_IRNCR);
0077     return IRQ_HANDLED;
0078 }
0079
0080 static void gptu_hwinit(void)
0081 {
0082     gptu_w32(0x00, GPTU_IRNEN);
0083     gptu_w32(0xff, GPTU_IRNCR);
0084     gptu_w32(CLC_RMC | CLC_SUSPEND, GPTU_CLC);
0085 }
0086
0087 static void gptu_hwexit(void)
0088 {
0089     gptu_w32(0x00, GPTU_IRNEN);
0090     gptu_w32(0xff, GPTU_IRNCR);
0091     gptu_w32(CLC_DISABLE, GPTU_CLC);
0092 }
0093
0094 static int gptu_enable(struct clk *clk)
0095 {
0096     int ret = request_irq(irqres[clk->bits].start, timer_irq_handler,
0097         IRQF_TIMER, "gtpu", NULL);
0098     if (ret) {
0099         pr_err("gptu: failed to request irq\n");
0100         return ret;
0101     }
0102
0103     gptu_w32(CON_CNT | CON_EDGE_ANY | CON_SYNC | CON_CLK_INT,
0104         GPTU_CON(clk->bits));
0105     gptu_w32(1, GPTU_RLD(clk->bits));
0106     gptu_w32(gptu_r32(GPTU_IRNEN) | BIT(clk->bits), GPTU_IRNEN);
0107     gptu_w32(RUN_SEN | RUN_RL, GPTU_RUN(clk->bits));
0108     return 0;
0109 }
0110
0111 static void gptu_disable(struct clk *clk)
0112 {
0113     gptu_w32(0, GPTU_RUN(clk->bits));
0114     gptu_w32(0, GPTU_CON(clk->bits));
0115     gptu_w32(0, GPTU_RLD(clk->bits));
0116     gptu_w32(gptu_r32(GPTU_IRNEN) & ~BIT(clk->bits), GPTU_IRNEN);
0117     free_irq(irqres[clk->bits].start, NULL);
0118 }
0119
0120 static inline void clkdev_add_gptu(struct device *dev, const char *con,
0121                             unsigned int timer)
0122 {
0123     struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
0124
0125     if (!clk)
0126         return;
0127     clk->cl.dev_id = dev_name(dev);
0128     clk->cl.con_id = con;
0129     clk->cl.clk = clk;
0130     clk->enable = gptu_enable;
0131     clk->disable = gptu_disable;
0132     clk->bits = timer;
0133     clkdev_add(&clk->cl);
0134 }
0135
0136 static int gptu_probe(struct platform_device *pdev)
0137 {
0138     struct clk *clk;
0139     struct resource *res;
0140
0141     if (of_irq_to_resource_table(pdev->dev.of_node, irqres, 6) != 6) {
0142         dev_err(&pdev->dev, "Failed to get IRQ list\n");
0143         return -EINVAL;
0144     }
0145
0146     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0147
0148     /* remap gptu register range */
0149     gptu_membase = devm_ioremap_resource(&pdev->dev, res);
0150     if (IS_ERR(gptu_membase))
0151         return PTR_ERR(gptu_membase);
0152
0153     /* enable our clock */
0154     clk = clk_get(&pdev->dev, NULL);
0155     if (IS_ERR(clk)) {
0156         dev_err(&pdev->dev, "Failed to get clock\n");
0157         return -ENOENT;
0158     }
0159     clk_enable(clk);
0160
0161     /* power up the core */
0162     gptu_hwinit();
0163
0164     /* the gptu has a ID register */
0165     if (((gptu_r32(GPTU_ID) >> 8) & 0xff) != GPTU_MAGIC) {
0166         dev_err(&pdev->dev, "Failed to find magic\n");
0167         gptu_hwexit();
0168         clk_disable(clk);
0169         clk_put(clk);
0170         return -ENAVAIL;
0171     }
0172
0173     /* register the clocks */
0174     clkdev_add_gptu(&pdev->dev, "timer1a", TIMER1A);
0175     clkdev_add_gptu(&pdev->dev, "timer1b", TIMER1B);
0176     clkdev_add_gptu(&pdev->dev, "timer2a", TIMER2A);
0177     clkdev_add_gptu(&pdev->dev, "timer2b", TIMER2B);
0178     clkdev_add_gptu(&pdev->dev, "timer3a", TIMER3A);
0179     clkdev_add_gptu(&pdev->dev, "timer3b", TIMER3B);
0180
0181     dev_info(&pdev->dev, "gptu: 6 timers loaded\n");
0182
0183     return 0;
0184 }
0185
0186 static const struct of_device_id gptu_match[] = {
0187     { .compatible = "lantiq,gptu-xway" },
0188     {},
0189 };
0190
0191 static struct platform_driver dma_driver = {
0192     .probe = gptu_probe,
0193     .driver = {
0194         .name = "gptu-xway",
0195         .of_match_table = gptu_match,
0196     },
0197 };
0198
0199 int __init gptu_init(void)
0200 {
0201     int ret = platform_driver_register(&dma_driver);
0202
0203     if (ret)
0204         pr_info("gptu: Error registering platform driver\n");
0205     return ret;
0206 }
0207
0208 arch_initcall(gptu_init);