lantiq/xway/clk.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *
0004  *  Copyright (C) 2010 John Crispin <john@phrozen.org>
0005  *  Copyright (C) 2013-2015 Lantiq Beteiligungs-GmbH & Co.KG
0006  */
0007
0008 #include <linux/io.h>
0009 #include <linux/export.h>
0010 #include <linux/clk.h>
0011
0012 #include <asm/time.h>
0013 #include <asm/irq.h>
0014 #include <asm/div64.h>
0015
0016 #include <lantiq_soc.h>
0017
0018 #include "../clk.h"
0019
0020 static unsigned int ram_clocks[] = {
0021     CLOCK_167M, CLOCK_133M, CLOCK_111M, CLOCK_83M };
0022 #define DDR_HZ ram_clocks[ltq_cgu_r32(CGU_SYS) & 0x3]
0023
0024 /* legacy xway clock */
0025 #define CGU_SYS         0x10
0026
0027 /* vr9, ar10/grx390 clock */
0028 #define CGU_SYS_XRX     0x0c
0029 #define CGU_IF_CLK_AR10     0x24
0030
0031 unsigned long ltq_danube_fpi_hz(void)
0032 {
0033     unsigned long ddr_clock = DDR_HZ;
0034
0035     if (ltq_cgu_r32(CGU_SYS) & 0x40)
0036         return ddr_clock >> 1;
0037     return ddr_clock;
0038 }
0039
0040 unsigned long ltq_danube_cpu_hz(void)
0041 {
0042     switch (ltq_cgu_r32(CGU_SYS) & 0xc) {
0043     case 0:
0044         return CLOCK_333M;
0045     case 4:
0046         return DDR_HZ;
0047     case 8:
0048         return DDR_HZ << 1;
0049     default:
0050         return DDR_HZ >> 1;
0051     }
0052 }
0053
0054 unsigned long ltq_danube_pp32_hz(void)
0055 {
0056     unsigned int clksys = (ltq_cgu_r32(CGU_SYS) >> 7) & 3;
0057     unsigned long clk;
0058
0059     switch (clksys) {
0060     case 1:
0061         clk = CLOCK_240M;
0062         break;
0063     case 2:
0064         clk = CLOCK_222M;
0065         break;
0066     case 3:
0067         clk = CLOCK_133M;
0068         break;
0069     default:
0070         clk = CLOCK_266M;
0071         break;
0072     }
0073
0074     return clk;
0075 }
0076
0077 unsigned long ltq_ar9_sys_hz(void)
0078 {
0079     if (((ltq_cgu_r32(CGU_SYS) >> 3) & 0x3) == 0x2)
0080         return CLOCK_393M;
0081     return CLOCK_333M;
0082 }
0083
0084 unsigned long ltq_ar9_fpi_hz(void)
0085 {
0086     unsigned long sys = ltq_ar9_sys_hz();
0087
0088     if (ltq_cgu_r32(CGU_SYS) & BIT(0))
0089         return sys / 3;
0090     else
0091         return sys / 2;
0092 }
0093
0094 unsigned long ltq_ar9_cpu_hz(void)
0095 {
0096     if (ltq_cgu_r32(CGU_SYS) & BIT(2))
0097         return ltq_ar9_fpi_hz();
0098     else
0099         return ltq_ar9_sys_hz();
0100 }
0101
0102 unsigned long ltq_vr9_cpu_hz(void)
0103 {
0104     unsigned int cpu_sel;
0105     unsigned long clk;
0106
0107     cpu_sel = (ltq_cgu_r32(CGU_SYS_XRX) >> 4) & 0xf;
0108
0109     switch (cpu_sel) {
0110     case 0:
0111         clk = CLOCK_600M;
0112         break;
0113     case 1:
0114         clk = CLOCK_500M;
0115         break;
0116     case 2:
0117         clk = CLOCK_393M;
0118         break;
0119     case 3:
0120         clk = CLOCK_333M;
0121         break;
0122     case 5:
0123     case 6:
0124         clk = CLOCK_196_608M;
0125         break;
0126     case 7:
0127         clk = CLOCK_167M;
0128         break;
0129     case 4:
0130     case 8:
0131     case 9:
0132         clk = CLOCK_125M;
0133         break;
0134     default:
0135         clk = 0;
0136         break;
0137     }
0138
0139     return clk;
0140 }
0141
0142 unsigned long ltq_vr9_fpi_hz(void)
0143 {
0144     unsigned int ocp_sel, cpu_clk;
0145     unsigned long clk;
0146
0147     cpu_clk = ltq_vr9_cpu_hz();
0148     ocp_sel = ltq_cgu_r32(CGU_SYS_XRX) & 0x3;
0149
0150     switch (ocp_sel) {
0151     case 0:
0152         /* OCP ratio 1 */
0153         clk = cpu_clk;
0154         break;
0155     case 2:
0156         /* OCP ratio 2 */
0157         clk = cpu_clk / 2;
0158         break;
0159     case 3:
0160         /* OCP ratio 2.5 */
0161         clk = (cpu_clk * 2) / 5;
0162         break;
0163     case 4:
0164         /* OCP ratio 3 */
0165         clk = cpu_clk / 3;
0166         break;
0167     default:
0168         clk = 0;
0169         break;
0170     }
0171
0172     return clk;
0173 }
0174
0175 unsigned long ltq_vr9_pp32_hz(void)
0176 {
0177     unsigned int clksys = (ltq_cgu_r32(CGU_SYS) >> 16) & 0x7;
0178     unsigned long clk;
0179
0180     switch (clksys) {
0181     case 0:
0182         clk = CLOCK_500M;
0183         break;
0184     case 1:
0185         clk = CLOCK_432M;
0186         break;
0187     case 2:
0188         clk = CLOCK_288M;
0189         break;
0190     default:
0191         clk = CLOCK_500M;
0192         break;
0193     }
0194
0195     return clk;
0196 }
0197
0198 unsigned long ltq_ar10_cpu_hz(void)
0199 {
0200     unsigned int clksys;
0201     int cpu_fs = (ltq_cgu_r32(CGU_SYS_XRX) >> 8) & 0x1;
0202     int freq_div = (ltq_cgu_r32(CGU_SYS_XRX) >> 4) & 0x7;
0203
0204     switch (cpu_fs) {
0205     case 0:
0206         clksys = CLOCK_500M;
0207         break;
0208     case 1:
0209         clksys = CLOCK_600M;
0210         break;
0211     default:
0212         clksys = CLOCK_500M;
0213         break;
0214     }
0215
0216     switch (freq_div) {
0217     case 0:
0218         return clksys;
0219     case 1:
0220         return clksys >> 1;
0221     case 2:
0222         return clksys >> 2;
0223     default:
0224         return clksys;
0225     }
0226 }
0227
0228 unsigned long ltq_ar10_fpi_hz(void)
0229 {
0230     int freq_fpi = (ltq_cgu_r32(CGU_IF_CLK_AR10) >> 25) & 0xf;
0231
0232     switch (freq_fpi) {
0233     case 1:
0234         return CLOCK_300M;
0235     case 5:
0236         return CLOCK_250M;
0237     case 2:
0238         return CLOCK_150M;
0239     case 6:
0240         return CLOCK_125M;
0241
0242     default:
0243         return CLOCK_125M;
0244     }
0245 }
0246
0247 unsigned long ltq_ar10_pp32_hz(void)
0248 {
0249     unsigned int clksys = (ltq_cgu_r32(CGU_SYS) >> 16) & 0x7;
0250     unsigned long clk;
0251
0252     switch (clksys) {
0253     case 1:
0254         clk = CLOCK_250M;
0255         break;
0256     case 4:
0257         clk = CLOCK_400M;
0258         break;
0259     default:
0260         clk = CLOCK_250M;
0261         break;
0262     }
0263
0264     return clk;
0265 }
0266
0267 unsigned long ltq_grx390_cpu_hz(void)
0268 {
0269     unsigned int clksys;
0270     int cpu_fs = ((ltq_cgu_r32(CGU_SYS_XRX) >> 9) & 0x3);
0271     int freq_div = ((ltq_cgu_r32(CGU_SYS_XRX) >> 4) & 0x7);
0272
0273     switch (cpu_fs) {
0274     case 0:
0275         clksys = CLOCK_600M;
0276         break;
0277     case 1:
0278         clksys = CLOCK_666M;
0279         break;
0280     case 2:
0281         clksys = CLOCK_720M;
0282         break;
0283     default:
0284         clksys = CLOCK_600M;
0285         break;
0286     }
0287
0288     switch (freq_div) {
0289     case 0:
0290         return clksys;
0291     case 1:
0292         return clksys >> 1;
0293     case 2:
0294         return clksys >> 2;
0295     default:
0296         return clksys;
0297     }
0298 }
0299
0300 unsigned long ltq_grx390_fpi_hz(void)
0301 {
0302     /* fpi clock is derived from ddr_clk */
0303     unsigned int clksys;
0304     int cpu_fs = ((ltq_cgu_r32(CGU_SYS_XRX) >> 9) & 0x3);
0305     int freq_div = ((ltq_cgu_r32(CGU_SYS_XRX)) & 0x7);
0306     switch (cpu_fs) {
0307     case 0:
0308         clksys = CLOCK_600M;
0309         break;
0310     case 1:
0311         clksys = CLOCK_666M;
0312         break;
0313     case 2:
0314         clksys = CLOCK_720M;
0315         break;
0316     default:
0317         clksys = CLOCK_600M;
0318         break;
0319     }
0320
0321     switch (freq_div) {
0322     case 1:
0323         return clksys >> 1;
0324     case 2:
0325         return clksys >> 2;
0326     default:
0327         return clksys >> 1;
0328     }
0329 }
0330
0331 unsigned long ltq_grx390_pp32_hz(void)
0332 {
0333     unsigned int clksys = (ltq_cgu_r32(CGU_SYS) >> 16) & 0x7;
0334     unsigned long clk;
0335
0336     switch (clksys) {
0337     case 1:
0338         clk = CLOCK_250M;
0339         break;
0340     case 2:
0341         clk = CLOCK_432M;
0342         break;
0343     case 4:
0344         clk = CLOCK_400M;
0345         break;
0346     default:
0347         clk = CLOCK_250M;
0348         break;
0349     }
0350     return clk;
0351 }