mips/kvm/fpu.S

0001 /*
0002  * This file is subject to the terms and conditions of the GNU General Public
0003  * License.  See the file "COPYING" in the main directory of this archive
0004  * for more details.
0005  *
0006  * FPU context handling code for KVM.
0007  *
0008  * Copyright (C) 2015 Imagination Technologies Ltd.
0009  */
0010
0011 #include <asm/asm.h>
0012 #include <asm/asm-offsets.h>
0013 #include <asm/fpregdef.h>
0014 #include <asm/mipsregs.h>
0015 #include <asm/regdef.h>
0016
0017 /* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */
0018 #undef fp
0019
0020     .set    noreorder
0021     .set    noat
0022
0023 LEAF(__kvm_save_fpu)
0024     .set    push
0025     SET_HARDFLOAT
0026     .set    fp=64
0027     mfc0    t0, CP0_STATUS
0028     sll     t0, t0, 5           # is Status.FR set?
0029     bgez    t0, 1f              # no: skip odd doubles
0030      nop
0031     sdc1    $f1,  VCPU_FPR1(a0)
0032     sdc1    $f3,  VCPU_FPR3(a0)
0033     sdc1    $f5,  VCPU_FPR5(a0)
0034     sdc1    $f7,  VCPU_FPR7(a0)
0035     sdc1    $f9,  VCPU_FPR9(a0)
0036     sdc1    $f11, VCPU_FPR11(a0)
0037     sdc1    $f13, VCPU_FPR13(a0)
0038     sdc1    $f15, VCPU_FPR15(a0)
0039     sdc1    $f17, VCPU_FPR17(a0)
0040     sdc1    $f19, VCPU_FPR19(a0)
0041     sdc1    $f21, VCPU_FPR21(a0)
0042     sdc1    $f23, VCPU_FPR23(a0)
0043     sdc1    $f25, VCPU_FPR25(a0)
0044     sdc1    $f27, VCPU_FPR27(a0)
0045     sdc1    $f29, VCPU_FPR29(a0)
0046     sdc1    $f31, VCPU_FPR31(a0)
0047 1:  sdc1    $f0,  VCPU_FPR0(a0)
0048     sdc1    $f2,  VCPU_FPR2(a0)
0049     sdc1    $f4,  VCPU_FPR4(a0)
0050     sdc1    $f6,  VCPU_FPR6(a0)
0051     sdc1    $f8,  VCPU_FPR8(a0)
0052     sdc1    $f10, VCPU_FPR10(a0)
0053     sdc1    $f12, VCPU_FPR12(a0)
0054     sdc1    $f14, VCPU_FPR14(a0)
0055     sdc1    $f16, VCPU_FPR16(a0)
0056     sdc1    $f18, VCPU_FPR18(a0)
0057     sdc1    $f20, VCPU_FPR20(a0)
0058     sdc1    $f22, VCPU_FPR22(a0)
0059     sdc1    $f24, VCPU_FPR24(a0)
0060     sdc1    $f26, VCPU_FPR26(a0)
0061     sdc1    $f28, VCPU_FPR28(a0)
0062     jr  ra
0063      sdc1   $f30, VCPU_FPR30(a0)
0064     .set    pop
0065     END(__kvm_save_fpu)
0066
0067 LEAF(__kvm_restore_fpu)
0068     .set    push
0069     SET_HARDFLOAT
0070     .set    fp=64
0071     mfc0    t0, CP0_STATUS
0072     sll     t0, t0, 5           # is Status.FR set?
0073     bgez    t0, 1f              # no: skip odd doubles
0074      nop
0075     ldc1    $f1,  VCPU_FPR1(a0)
0076     ldc1    $f3,  VCPU_FPR3(a0)
0077     ldc1    $f5,  VCPU_FPR5(a0)
0078     ldc1    $f7,  VCPU_FPR7(a0)
0079     ldc1    $f9,  VCPU_FPR9(a0)
0080     ldc1    $f11, VCPU_FPR11(a0)
0081     ldc1    $f13, VCPU_FPR13(a0)
0082     ldc1    $f15, VCPU_FPR15(a0)
0083     ldc1    $f17, VCPU_FPR17(a0)
0084     ldc1    $f19, VCPU_FPR19(a0)
0085     ldc1    $f21, VCPU_FPR21(a0)
0086     ldc1    $f23, VCPU_FPR23(a0)
0087     ldc1    $f25, VCPU_FPR25(a0)
0088     ldc1    $f27, VCPU_FPR27(a0)
0089     ldc1    $f29, VCPU_FPR29(a0)
0090     ldc1    $f31, VCPU_FPR31(a0)
0091 1:  ldc1    $f0,  VCPU_FPR0(a0)
0092     ldc1    $f2,  VCPU_FPR2(a0)
0093     ldc1    $f4,  VCPU_FPR4(a0)
0094     ldc1    $f6,  VCPU_FPR6(a0)
0095     ldc1    $f8,  VCPU_FPR8(a0)
0096     ldc1    $f10, VCPU_FPR10(a0)
0097     ldc1    $f12, VCPU_FPR12(a0)
0098     ldc1    $f14, VCPU_FPR14(a0)
0099     ldc1    $f16, VCPU_FPR16(a0)
0100     ldc1    $f18, VCPU_FPR18(a0)
0101     ldc1    $f20, VCPU_FPR20(a0)
0102     ldc1    $f22, VCPU_FPR22(a0)
0103     ldc1    $f24, VCPU_FPR24(a0)
0104     ldc1    $f26, VCPU_FPR26(a0)
0105     ldc1    $f28, VCPU_FPR28(a0)
0106     jr  ra
0107      ldc1   $f30, VCPU_FPR30(a0)
0108     .set    pop
0109     END(__kvm_restore_fpu)
0110
0111 LEAF(__kvm_restore_fcsr)
0112     .set    push
0113     SET_HARDFLOAT
0114     lw  t0, VCPU_FCR31(a0)
0115     /*
0116      * The ctc1 must stay at this offset in __kvm_restore_fcsr.
0117      * See kvm_mips_csr_die_notify() which handles t0 containing a value
0118      * which triggers an FP Exception, which must be stepped over and
0119      * ignored since the set cause bits must remain there for the guest.
0120      */
0121     ctc1    t0, fcr31
0122     jr  ra
0123      nop
0124     .set    pop
0125     END(__kvm_restore_fcsr)