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0001 /*
0002  * This file is subject to the terms and conditions of the GNU General Public
0003  * License.  See the file "COPYING" in the main directory of this archive
0004  * for more details.
0005  *
0006  * KVM/MIPS: Instruction/Exception emulation
0007  *
0008  * Copyright (C) 2012  MIPS Technologies, Inc.  All rights reserved.
0009  * Authors: Sanjay Lal <sanjayl@kymasys.com>
0010  */
0011 
0012 #include <linux/errno.h>
0013 #include <linux/err.h>
0014 #include <linux/ktime.h>
0015 #include <linux/kvm_host.h>
0016 #include <linux/vmalloc.h>
0017 #include <linux/fs.h>
0018 #include <linux/memblock.h>
0019 #include <linux/random.h>
0020 #include <asm/page.h>
0021 #include <asm/cacheflush.h>
0022 #include <asm/cacheops.h>
0023 #include <asm/cpu-info.h>
0024 #include <asm/mmu_context.h>
0025 #include <asm/tlbflush.h>
0026 #include <asm/inst.h>
0027 
0028 #undef CONFIG_MIPS_MT
0029 #include <asm/r4kcache.h>
0030 #define CONFIG_MIPS_MT
0031 
0032 #include "interrupt.h"
0033 
0034 #include "trace.h"
0035 
0036 /*
0037  * Compute the return address and do emulate branch simulation, if required.
0038  * This function should be called only in branch delay slot active.
0039  */
0040 static int kvm_compute_return_epc(struct kvm_vcpu *vcpu, unsigned long instpc,
0041                   unsigned long *out)
0042 {
0043     unsigned int dspcontrol;
0044     union mips_instruction insn;
0045     struct kvm_vcpu_arch *arch = &vcpu->arch;
0046     long epc = instpc;
0047     long nextpc;
0048     int err;
0049 
0050     if (epc & 3) {
0051         kvm_err("%s: unaligned epc\n", __func__);
0052         return -EINVAL;
0053     }
0054 
0055     /* Read the instruction */
0056     err = kvm_get_badinstrp((u32 *)epc, vcpu, &insn.word);
0057     if (err)
0058         return err;
0059 
0060     switch (insn.i_format.opcode) {
0061         /* jr and jalr are in r_format format. */
0062     case spec_op:
0063         switch (insn.r_format.func) {
0064         case jalr_op:
0065             arch->gprs[insn.r_format.rd] = epc + 8;
0066             fallthrough;
0067         case jr_op:
0068             nextpc = arch->gprs[insn.r_format.rs];
0069             break;
0070         default:
0071             return -EINVAL;
0072         }
0073         break;
0074 
0075         /*
0076          * This group contains:
0077          * bltz_op, bgez_op, bltzl_op, bgezl_op,
0078          * bltzal_op, bgezal_op, bltzall_op, bgezall_op.
0079          */
0080     case bcond_op:
0081         switch (insn.i_format.rt) {
0082         case bltz_op:
0083         case bltzl_op:
0084             if ((long)arch->gprs[insn.i_format.rs] < 0)
0085                 epc = epc + 4 + (insn.i_format.simmediate << 2);
0086             else
0087                 epc += 8;
0088             nextpc = epc;
0089             break;
0090 
0091         case bgez_op:
0092         case bgezl_op:
0093             if ((long)arch->gprs[insn.i_format.rs] >= 0)
0094                 epc = epc + 4 + (insn.i_format.simmediate << 2);
0095             else
0096                 epc += 8;
0097             nextpc = epc;
0098             break;
0099 
0100         case bltzal_op:
0101         case bltzall_op:
0102             arch->gprs[31] = epc + 8;
0103             if ((long)arch->gprs[insn.i_format.rs] < 0)
0104                 epc = epc + 4 + (insn.i_format.simmediate << 2);
0105             else
0106                 epc += 8;
0107             nextpc = epc;
0108             break;
0109 
0110         case bgezal_op:
0111         case bgezall_op:
0112             arch->gprs[31] = epc + 8;
0113             if ((long)arch->gprs[insn.i_format.rs] >= 0)
0114                 epc = epc + 4 + (insn.i_format.simmediate << 2);
0115             else
0116                 epc += 8;
0117             nextpc = epc;
0118             break;
0119         case bposge32_op:
0120             if (!cpu_has_dsp) {
0121                 kvm_err("%s: DSP branch but not DSP ASE\n",
0122                     __func__);
0123                 return -EINVAL;
0124             }
0125 
0126             dspcontrol = rddsp(0x01);
0127 
0128             if (dspcontrol >= 32)
0129                 epc = epc + 4 + (insn.i_format.simmediate << 2);
0130             else
0131                 epc += 8;
0132             nextpc = epc;
0133             break;
0134         default:
0135             return -EINVAL;
0136         }
0137         break;
0138 
0139         /* These are unconditional and in j_format. */
0140     case jal_op:
0141         arch->gprs[31] = instpc + 8;
0142         fallthrough;
0143     case j_op:
0144         epc += 4;
0145         epc >>= 28;
0146         epc <<= 28;
0147         epc |= (insn.j_format.target << 2);
0148         nextpc = epc;
0149         break;
0150 
0151         /* These are conditional and in i_format. */
0152     case beq_op:
0153     case beql_op:
0154         if (arch->gprs[insn.i_format.rs] ==
0155             arch->gprs[insn.i_format.rt])
0156             epc = epc + 4 + (insn.i_format.simmediate << 2);
0157         else
0158             epc += 8;
0159         nextpc = epc;
0160         break;
0161 
0162     case bne_op:
0163     case bnel_op:
0164         if (arch->gprs[insn.i_format.rs] !=
0165             arch->gprs[insn.i_format.rt])
0166             epc = epc + 4 + (insn.i_format.simmediate << 2);
0167         else
0168             epc += 8;
0169         nextpc = epc;
0170         break;
0171 
0172     case blez_op:   /* POP06 */
0173 #ifndef CONFIG_CPU_MIPSR6
0174     case blezl_op:  /* removed in R6 */
0175 #endif
0176         if (insn.i_format.rt != 0)
0177             goto compact_branch;
0178         if ((long)arch->gprs[insn.i_format.rs] <= 0)
0179             epc = epc + 4 + (insn.i_format.simmediate << 2);
0180         else
0181             epc += 8;
0182         nextpc = epc;
0183         break;
0184 
0185     case bgtz_op:   /* POP07 */
0186 #ifndef CONFIG_CPU_MIPSR6
0187     case bgtzl_op:  /* removed in R6 */
0188 #endif
0189         if (insn.i_format.rt != 0)
0190             goto compact_branch;
0191         if ((long)arch->gprs[insn.i_format.rs] > 0)
0192             epc = epc + 4 + (insn.i_format.simmediate << 2);
0193         else
0194             epc += 8;
0195         nextpc = epc;
0196         break;
0197 
0198         /* And now the FPA/cp1 branch instructions. */
0199     case cop1_op:
0200         kvm_err("%s: unsupported cop1_op\n", __func__);
0201         return -EINVAL;
0202 
0203 #ifdef CONFIG_CPU_MIPSR6
0204     /* R6 added the following compact branches with forbidden slots */
0205     case blezl_op:  /* POP26 */
0206     case bgtzl_op:  /* POP27 */
0207         /* only rt == 0 isn't compact branch */
0208         if (insn.i_format.rt != 0)
0209             goto compact_branch;
0210         return -EINVAL;
0211     case pop10_op:
0212     case pop30_op:
0213         /* only rs == rt == 0 is reserved, rest are compact branches */
0214         if (insn.i_format.rs != 0 || insn.i_format.rt != 0)
0215             goto compact_branch;
0216         return -EINVAL;
0217     case pop66_op:
0218     case pop76_op:
0219         /* only rs == 0 isn't compact branch */
0220         if (insn.i_format.rs != 0)
0221             goto compact_branch;
0222         return -EINVAL;
0223 compact_branch:
0224         /*
0225          * If we've hit an exception on the forbidden slot, then
0226          * the branch must not have been taken.
0227          */
0228         epc += 8;
0229         nextpc = epc;
0230         break;
0231 #else
0232 compact_branch:
0233         /* Fall through - Compact branches not supported before R6 */
0234 #endif
0235     default:
0236         return -EINVAL;
0237     }
0238 
0239     *out = nextpc;
0240     return 0;
0241 }
0242 
0243 enum emulation_result update_pc(struct kvm_vcpu *vcpu, u32 cause)
0244 {
0245     int err;
0246 
0247     if (cause & CAUSEF_BD) {
0248         err = kvm_compute_return_epc(vcpu, vcpu->arch.pc,
0249                          &vcpu->arch.pc);
0250         if (err)
0251             return EMULATE_FAIL;
0252     } else {
0253         vcpu->arch.pc += 4;
0254     }
0255 
0256     kvm_debug("update_pc(): New PC: %#lx\n", vcpu->arch.pc);
0257 
0258     return EMULATE_DONE;
0259 }
0260 
0261 /**
0262  * kvm_get_badinstr() - Get bad instruction encoding.
0263  * @opc:    Guest pointer to faulting instruction.
0264  * @vcpu:   KVM VCPU information.
0265  *
0266  * Gets the instruction encoding of the faulting instruction, using the saved
0267  * BadInstr register value if it exists, otherwise falling back to reading guest
0268  * memory at @opc.
0269  *
0270  * Returns: The instruction encoding of the faulting instruction.
0271  */
0272 int kvm_get_badinstr(u32 *opc, struct kvm_vcpu *vcpu, u32 *out)
0273 {
0274     if (cpu_has_badinstr) {
0275         *out = vcpu->arch.host_cp0_badinstr;
0276         return 0;
0277     } else {
0278         WARN_ONCE(1, "CPU doesn't have BadInstr register\n");
0279         return -EINVAL;
0280     }
0281 }
0282 
0283 /**
0284  * kvm_get_badinstrp() - Get bad prior instruction encoding.
0285  * @opc:    Guest pointer to prior faulting instruction.
0286  * @vcpu:   KVM VCPU information.
0287  *
0288  * Gets the instruction encoding of the prior faulting instruction (the branch
0289  * containing the delay slot which faulted), using the saved BadInstrP register
0290  * value if it exists, otherwise falling back to reading guest memory at @opc.
0291  *
0292  * Returns: The instruction encoding of the prior faulting instruction.
0293  */
0294 int kvm_get_badinstrp(u32 *opc, struct kvm_vcpu *vcpu, u32 *out)
0295 {
0296     if (cpu_has_badinstrp) {
0297         *out = vcpu->arch.host_cp0_badinstrp;
0298         return 0;
0299     } else {
0300         WARN_ONCE(1, "CPU doesn't have BadInstrp register\n");
0301         return -EINVAL;
0302     }
0303 }
0304 
0305 /**
0306  * kvm_mips_count_disabled() - Find whether the CP0_Count timer is disabled.
0307  * @vcpu:   Virtual CPU.
0308  *
0309  * Returns: 1 if the CP0_Count timer is disabled by either the guest
0310  *      CP0_Cause.DC bit or the count_ctl.DC bit.
0311  *      0 otherwise (in which case CP0_Count timer is running).
0312  */
0313 int kvm_mips_count_disabled(struct kvm_vcpu *vcpu)
0314 {
0315     struct mips_coproc *cop0 = vcpu->arch.cop0;
0316 
0317     return  (vcpu->arch.count_ctl & KVM_REG_MIPS_COUNT_CTL_DC) ||
0318         (kvm_read_c0_guest_cause(cop0) & CAUSEF_DC);
0319 }
0320 
0321 /**
0322  * kvm_mips_ktime_to_count() - Scale ktime_t to a 32-bit count.
0323  *
0324  * Caches the dynamic nanosecond bias in vcpu->arch.count_dyn_bias.
0325  *
0326  * Assumes !kvm_mips_count_disabled(@vcpu) (guest CP0_Count timer is running).
0327  */
0328 static u32 kvm_mips_ktime_to_count(struct kvm_vcpu *vcpu, ktime_t now)
0329 {
0330     s64 now_ns, periods;
0331     u64 delta;
0332 
0333     now_ns = ktime_to_ns(now);
0334     delta = now_ns + vcpu->arch.count_dyn_bias;
0335 
0336     if (delta >= vcpu->arch.count_period) {
0337         /* If delta is out of safe range the bias needs adjusting */
0338         periods = div64_s64(now_ns, vcpu->arch.count_period);
0339         vcpu->arch.count_dyn_bias = -periods * vcpu->arch.count_period;
0340         /* Recalculate delta with new bias */
0341         delta = now_ns + vcpu->arch.count_dyn_bias;
0342     }
0343 
0344     /*
0345      * We've ensured that:
0346      *   delta < count_period
0347      *
0348      * Therefore the intermediate delta*count_hz will never overflow since
0349      * at the boundary condition:
0350      *   delta = count_period
0351      *   delta = NSEC_PER_SEC * 2^32 / count_hz
0352      *   delta * count_hz = NSEC_PER_SEC * 2^32
0353      */
0354     return div_u64(delta * vcpu->arch.count_hz, NSEC_PER_SEC);
0355 }
0356 
0357 /**
0358  * kvm_mips_count_time() - Get effective current time.
0359  * @vcpu:   Virtual CPU.
0360  *
0361  * Get effective monotonic ktime. This is usually a straightforward ktime_get(),
0362  * except when the master disable bit is set in count_ctl, in which case it is
0363  * count_resume, i.e. the time that the count was disabled.
0364  *
0365  * Returns: Effective monotonic ktime for CP0_Count.
0366  */
0367 static inline ktime_t kvm_mips_count_time(struct kvm_vcpu *vcpu)
0368 {
0369     if (unlikely(vcpu->arch.count_ctl & KVM_REG_MIPS_COUNT_CTL_DC))
0370         return vcpu->arch.count_resume;
0371 
0372     return ktime_get();
0373 }
0374 
0375 /**
0376  * kvm_mips_read_count_running() - Read the current count value as if running.
0377  * @vcpu:   Virtual CPU.
0378  * @now:    Kernel time to read CP0_Count at.
0379  *
0380  * Returns the current guest CP0_Count register at time @now and handles if the
0381  * timer interrupt is pending and hasn't been handled yet.
0382  *
0383  * Returns: The current value of the guest CP0_Count register.
0384  */
0385 static u32 kvm_mips_read_count_running(struct kvm_vcpu *vcpu, ktime_t now)
0386 {
0387     struct mips_coproc *cop0 = vcpu->arch.cop0;
0388     ktime_t expires, threshold;
0389     u32 count, compare;
0390     int running;
0391 
0392     /* Calculate the biased and scaled guest CP0_Count */
0393     count = vcpu->arch.count_bias + kvm_mips_ktime_to_count(vcpu, now);
0394     compare = kvm_read_c0_guest_compare(cop0);
0395 
0396     /*
0397      * Find whether CP0_Count has reached the closest timer interrupt. If
0398      * not, we shouldn't inject it.
0399      */
0400     if ((s32)(count - compare) < 0)
0401         return count;
0402 
0403     /*
0404      * The CP0_Count we're going to return has already reached the closest
0405      * timer interrupt. Quickly check if it really is a new interrupt by
0406      * looking at whether the interval until the hrtimer expiry time is
0407      * less than 1/4 of the timer period.
0408      */
0409     expires = hrtimer_get_expires(&vcpu->arch.comparecount_timer);
0410     threshold = ktime_add_ns(now, vcpu->arch.count_period / 4);
0411     if (ktime_before(expires, threshold)) {
0412         /*
0413          * Cancel it while we handle it so there's no chance of
0414          * interference with the timeout handler.
0415          */
0416         running = hrtimer_cancel(&vcpu->arch.comparecount_timer);
0417 
0418         /* Nothing should be waiting on the timeout */
0419         kvm_mips_callbacks->queue_timer_int(vcpu);
0420 
0421         /*
0422          * Restart the timer if it was running based on the expiry time
0423          * we read, so that we don't push it back 2 periods.
0424          */
0425         if (running) {
0426             expires = ktime_add_ns(expires,
0427                            vcpu->arch.count_period);
0428             hrtimer_start(&vcpu->arch.comparecount_timer, expires,
0429                       HRTIMER_MODE_ABS);
0430         }
0431     }
0432 
0433     return count;
0434 }
0435 
0436 /**
0437  * kvm_mips_read_count() - Read the current count value.
0438  * @vcpu:   Virtual CPU.
0439  *
0440  * Read the current guest CP0_Count value, taking into account whether the timer
0441  * is stopped.
0442  *
0443  * Returns: The current guest CP0_Count value.
0444  */
0445 u32 kvm_mips_read_count(struct kvm_vcpu *vcpu)
0446 {
0447     struct mips_coproc *cop0 = vcpu->arch.cop0;
0448 
0449     /* If count disabled just read static copy of count */
0450     if (kvm_mips_count_disabled(vcpu))
0451         return kvm_read_c0_guest_count(cop0);
0452 
0453     return kvm_mips_read_count_running(vcpu, ktime_get());
0454 }
0455 
0456 /**
0457  * kvm_mips_freeze_hrtimer() - Safely stop the hrtimer.
0458  * @vcpu:   Virtual CPU.
0459  * @count:  Output pointer for CP0_Count value at point of freeze.
0460  *
0461  * Freeze the hrtimer safely and return both the ktime and the CP0_Count value
0462  * at the point it was frozen. It is guaranteed that any pending interrupts at
0463  * the point it was frozen are handled, and none after that point.
0464  *
0465  * This is useful where the time/CP0_Count is needed in the calculation of the
0466  * new parameters.
0467  *
0468  * Assumes !kvm_mips_count_disabled(@vcpu) (guest CP0_Count timer is running).
0469  *
0470  * Returns: The ktime at the point of freeze.
0471  */
0472 ktime_t kvm_mips_freeze_hrtimer(struct kvm_vcpu *vcpu, u32 *count)
0473 {
0474     ktime_t now;
0475 
0476     /* stop hrtimer before finding time */
0477     hrtimer_cancel(&vcpu->arch.comparecount_timer);
0478     now = ktime_get();
0479 
0480     /* find count at this point and handle pending hrtimer */
0481     *count = kvm_mips_read_count_running(vcpu, now);
0482 
0483     return now;
0484 }
0485 
0486 /**
0487  * kvm_mips_resume_hrtimer() - Resume hrtimer, updating expiry.
0488  * @vcpu:   Virtual CPU.
0489  * @now:    ktime at point of resume.
0490  * @count:  CP0_Count at point of resume.
0491  *
0492  * Resumes the timer and updates the timer expiry based on @now and @count.
0493  * This can be used in conjunction with kvm_mips_freeze_timer() when timer
0494  * parameters need to be changed.
0495  *
0496  * It is guaranteed that a timer interrupt immediately after resume will be
0497  * handled, but not if CP_Compare is exactly at @count. That case is already
0498  * handled by kvm_mips_freeze_timer().
0499  *
0500  * Assumes !kvm_mips_count_disabled(@vcpu) (guest CP0_Count timer is running).
0501  */
0502 static void kvm_mips_resume_hrtimer(struct kvm_vcpu *vcpu,
0503                     ktime_t now, u32 count)
0504 {
0505     struct mips_coproc *cop0 = vcpu->arch.cop0;
0506     u32 compare;
0507     u64 delta;
0508     ktime_t expire;
0509 
0510     /* Calculate timeout (wrap 0 to 2^32) */
0511     compare = kvm_read_c0_guest_compare(cop0);
0512     delta = (u64)(u32)(compare - count - 1) + 1;
0513     delta = div_u64(delta * NSEC_PER_SEC, vcpu->arch.count_hz);
0514     expire = ktime_add_ns(now, delta);
0515 
0516     /* Update hrtimer to use new timeout */
0517     hrtimer_cancel(&vcpu->arch.comparecount_timer);
0518     hrtimer_start(&vcpu->arch.comparecount_timer, expire, HRTIMER_MODE_ABS);
0519 }
0520 
0521 /**
0522  * kvm_mips_restore_hrtimer() - Restore hrtimer after a gap, updating expiry.
0523  * @vcpu:   Virtual CPU.
0524  * @before: Time before Count was saved, lower bound of drift calculation.
0525  * @count:  CP0_Count at point of restore.
0526  * @min_drift:  Minimum amount of drift permitted before correction.
0527  *      Must be <= 0.
0528  *
0529  * Restores the timer from a particular @count, accounting for drift. This can
0530  * be used in conjunction with kvm_mips_freeze_timer() when a hardware timer is
0531  * to be used for a period of time, but the exact ktime corresponding to the
0532  * final Count that must be restored is not known.
0533  *
0534  * It is gauranteed that a timer interrupt immediately after restore will be
0535  * handled, but not if CP0_Compare is exactly at @count. That case should
0536  * already be handled when the hardware timer state is saved.
0537  *
0538  * Assumes !kvm_mips_count_disabled(@vcpu) (guest CP0_Count timer is not
0539  * stopped).
0540  *
0541  * Returns: Amount of correction to count_bias due to drift.
0542  */
0543 int kvm_mips_restore_hrtimer(struct kvm_vcpu *vcpu, ktime_t before,
0544                  u32 count, int min_drift)
0545 {
0546     ktime_t now, count_time;
0547     u32 now_count, before_count;
0548     u64 delta;
0549     int drift, ret = 0;
0550 
0551     /* Calculate expected count at before */
0552     before_count = vcpu->arch.count_bias +
0553             kvm_mips_ktime_to_count(vcpu, before);
0554 
0555     /*
0556      * Detect significantly negative drift, where count is lower than
0557      * expected. Some negative drift is expected when hardware counter is
0558      * set after kvm_mips_freeze_timer(), and it is harmless to allow the
0559      * time to jump forwards a little, within reason. If the drift is too
0560      * significant, adjust the bias to avoid a big Guest.CP0_Count jump.
0561      */
0562     drift = count - before_count;
0563     if (drift < min_drift) {
0564         count_time = before;
0565         vcpu->arch.count_bias += drift;
0566         ret = drift;
0567         goto resume;
0568     }
0569 
0570     /* Calculate expected count right now */
0571     now = ktime_get();
0572     now_count = vcpu->arch.count_bias + kvm_mips_ktime_to_count(vcpu, now);
0573 
0574     /*
0575      * Detect positive drift, where count is higher than expected, and
0576      * adjust the bias to avoid guest time going backwards.
0577      */
0578     drift = count - now_count;
0579     if (drift > 0) {
0580         count_time = now;
0581         vcpu->arch.count_bias += drift;
0582         ret = drift;
0583         goto resume;
0584     }
0585 
0586     /* Subtract nanosecond delta to find ktime when count was read */
0587     delta = (u64)(u32)(now_count - count);
0588     delta = div_u64(delta * NSEC_PER_SEC, vcpu->arch.count_hz);
0589     count_time = ktime_sub_ns(now, delta);
0590 
0591 resume:
0592     /* Resume using the calculated ktime */
0593     kvm_mips_resume_hrtimer(vcpu, count_time, count);
0594     return ret;
0595 }
0596 
0597 /**
0598  * kvm_mips_write_count() - Modify the count and update timer.
0599  * @vcpu:   Virtual CPU.
0600  * @count:  Guest CP0_Count value to set.
0601  *
0602  * Sets the CP0_Count value and updates the timer accordingly.
0603  */
0604 void kvm_mips_write_count(struct kvm_vcpu *vcpu, u32 count)
0605 {
0606     struct mips_coproc *cop0 = vcpu->arch.cop0;
0607     ktime_t now;
0608 
0609     /* Calculate bias */
0610     now = kvm_mips_count_time(vcpu);
0611     vcpu->arch.count_bias = count - kvm_mips_ktime_to_count(vcpu, now);
0612 
0613     if (kvm_mips_count_disabled(vcpu))
0614         /* The timer's disabled, adjust the static count */
0615         kvm_write_c0_guest_count(cop0, count);
0616     else
0617         /* Update timeout */
0618         kvm_mips_resume_hrtimer(vcpu, now, count);
0619 }
0620 
0621 /**
0622  * kvm_mips_init_count() - Initialise timer.
0623  * @vcpu:   Virtual CPU.
0624  * @count_hz:   Frequency of timer.
0625  *
0626  * Initialise the timer to the specified frequency, zero it, and set it going if
0627  * it's enabled.
0628  */
0629 void kvm_mips_init_count(struct kvm_vcpu *vcpu, unsigned long count_hz)
0630 {
0631     vcpu->arch.count_hz = count_hz;
0632     vcpu->arch.count_period = div_u64((u64)NSEC_PER_SEC << 32, count_hz);
0633     vcpu->arch.count_dyn_bias = 0;
0634 
0635     /* Starting at 0 */
0636     kvm_mips_write_count(vcpu, 0);
0637 }
0638 
0639 /**
0640  * kvm_mips_set_count_hz() - Update the frequency of the timer.
0641  * @vcpu:   Virtual CPU.
0642  * @count_hz:   Frequency of CP0_Count timer in Hz.
0643  *
0644  * Change the frequency of the CP0_Count timer. This is done atomically so that
0645  * CP0_Count is continuous and no timer interrupt is lost.
0646  *
0647  * Returns: -EINVAL if @count_hz is out of range.
0648  *      0 on success.
0649  */
0650 int kvm_mips_set_count_hz(struct kvm_vcpu *vcpu, s64 count_hz)
0651 {
0652     struct mips_coproc *cop0 = vcpu->arch.cop0;
0653     int dc;
0654     ktime_t now;
0655     u32 count;
0656 
0657     /* ensure the frequency is in a sensible range... */
0658     if (count_hz <= 0 || count_hz > NSEC_PER_SEC)
0659         return -EINVAL;
0660     /* ... and has actually changed */
0661     if (vcpu->arch.count_hz == count_hz)
0662         return 0;
0663 
0664     /* Safely freeze timer so we can keep it continuous */
0665     dc = kvm_mips_count_disabled(vcpu);
0666     if (dc) {
0667         now = kvm_mips_count_time(vcpu);
0668         count = kvm_read_c0_guest_count(cop0);
0669     } else {
0670         now = kvm_mips_freeze_hrtimer(vcpu, &count);
0671     }
0672 
0673     /* Update the frequency */
0674     vcpu->arch.count_hz = count_hz;
0675     vcpu->arch.count_period = div_u64((u64)NSEC_PER_SEC << 32, count_hz);
0676     vcpu->arch.count_dyn_bias = 0;
0677 
0678     /* Calculate adjusted bias so dynamic count is unchanged */
0679     vcpu->arch.count_bias = count - kvm_mips_ktime_to_count(vcpu, now);
0680 
0681     /* Update and resume hrtimer */
0682     if (!dc)
0683         kvm_mips_resume_hrtimer(vcpu, now, count);
0684     return 0;
0685 }
0686 
0687 /**
0688  * kvm_mips_write_compare() - Modify compare and update timer.
0689  * @vcpu:   Virtual CPU.
0690  * @compare:    New CP0_Compare value.
0691  * @ack:    Whether to acknowledge timer interrupt.
0692  *
0693  * Update CP0_Compare to a new value and update the timeout.
0694  * If @ack, atomically acknowledge any pending timer interrupt, otherwise ensure
0695  * any pending timer interrupt is preserved.
0696  */
0697 void kvm_mips_write_compare(struct kvm_vcpu *vcpu, u32 compare, bool ack)
0698 {
0699     struct mips_coproc *cop0 = vcpu->arch.cop0;
0700     int dc;
0701     u32 old_compare = kvm_read_c0_guest_compare(cop0);
0702     s32 delta = compare - old_compare;
0703     u32 cause;
0704     ktime_t now = ktime_set(0, 0); /* silence bogus GCC warning */
0705     u32 count;
0706 
0707     /* if unchanged, must just be an ack */
0708     if (old_compare == compare) {
0709         if (!ack)
0710             return;
0711         kvm_mips_callbacks->dequeue_timer_int(vcpu);
0712         kvm_write_c0_guest_compare(cop0, compare);
0713         return;
0714     }
0715 
0716     /*
0717      * If guest CP0_Compare moves forward, CP0_GTOffset should be adjusted
0718      * too to prevent guest CP0_Count hitting guest CP0_Compare.
0719      *
0720      * The new GTOffset corresponds to the new value of CP0_Compare, and is
0721      * set prior to it being written into the guest context. We disable
0722      * preemption until the new value is written to prevent restore of a
0723      * GTOffset corresponding to the old CP0_Compare value.
0724      */
0725     if (delta > 0) {
0726         preempt_disable();
0727         write_c0_gtoffset(compare - read_c0_count());
0728         back_to_back_c0_hazard();
0729     }
0730 
0731     /* freeze_hrtimer() takes care of timer interrupts <= count */
0732     dc = kvm_mips_count_disabled(vcpu);
0733     if (!dc)
0734         now = kvm_mips_freeze_hrtimer(vcpu, &count);
0735 
0736     if (ack)
0737         kvm_mips_callbacks->dequeue_timer_int(vcpu);
0738     else
0739         /*
0740          * With VZ, writing CP0_Compare acks (clears) CP0_Cause.TI, so
0741          * preserve guest CP0_Cause.TI if we don't want to ack it.
0742          */
0743         cause = kvm_read_c0_guest_cause(cop0);
0744 
0745     kvm_write_c0_guest_compare(cop0, compare);
0746 
0747     if (delta > 0)
0748         preempt_enable();
0749 
0750     back_to_back_c0_hazard();
0751 
0752     if (!ack && cause & CAUSEF_TI)
0753         kvm_write_c0_guest_cause(cop0, cause);
0754 
0755     /* resume_hrtimer() takes care of timer interrupts > count */
0756     if (!dc)
0757         kvm_mips_resume_hrtimer(vcpu, now, count);
0758 
0759     /*
0760      * If guest CP0_Compare is moving backward, we delay CP0_GTOffset change
0761      * until after the new CP0_Compare is written, otherwise new guest
0762      * CP0_Count could hit new guest CP0_Compare.
0763      */
0764     if (delta <= 0)
0765         write_c0_gtoffset(compare - read_c0_count());
0766 }
0767 
0768 /**
0769  * kvm_mips_count_disable() - Disable count.
0770  * @vcpu:   Virtual CPU.
0771  *
0772  * Disable the CP0_Count timer. A timer interrupt on or before the final stop
0773  * time will be handled but not after.
0774  *
0775  * Assumes CP0_Count was previously enabled but now Guest.CP0_Cause.DC or
0776  * count_ctl.DC has been set (count disabled).
0777  *
0778  * Returns: The time that the timer was stopped.
0779  */
0780 static ktime_t kvm_mips_count_disable(struct kvm_vcpu *vcpu)
0781 {
0782     struct mips_coproc *cop0 = vcpu->arch.cop0;
0783     u32 count;
0784     ktime_t now;
0785 
0786     /* Stop hrtimer */
0787     hrtimer_cancel(&vcpu->arch.comparecount_timer);
0788 
0789     /* Set the static count from the dynamic count, handling pending TI */
0790     now = ktime_get();
0791     count = kvm_mips_read_count_running(vcpu, now);
0792     kvm_write_c0_guest_count(cop0, count);
0793 
0794     return now;
0795 }
0796 
0797 /**
0798  * kvm_mips_count_disable_cause() - Disable count using CP0_Cause.DC.
0799  * @vcpu:   Virtual CPU.
0800  *
0801  * Disable the CP0_Count timer and set CP0_Cause.DC. A timer interrupt on or
0802  * before the final stop time will be handled if the timer isn't disabled by
0803  * count_ctl.DC, but not after.
0804  *
0805  * Assumes CP0_Cause.DC is clear (count enabled).
0806  */
0807 void kvm_mips_count_disable_cause(struct kvm_vcpu *vcpu)
0808 {
0809     struct mips_coproc *cop0 = vcpu->arch.cop0;
0810 
0811     kvm_set_c0_guest_cause(cop0, CAUSEF_DC);
0812     if (!(vcpu->arch.count_ctl & KVM_REG_MIPS_COUNT_CTL_DC))
0813         kvm_mips_count_disable(vcpu);
0814 }
0815 
0816 /**
0817  * kvm_mips_count_enable_cause() - Enable count using CP0_Cause.DC.
0818  * @vcpu:   Virtual CPU.
0819  *
0820  * Enable the CP0_Count timer and clear CP0_Cause.DC. A timer interrupt after
0821  * the start time will be handled if the timer isn't disabled by count_ctl.DC,
0822  * potentially before even returning, so the caller should be careful with
0823  * ordering of CP0_Cause modifications so as not to lose it.
0824  *
0825  * Assumes CP0_Cause.DC is set (count disabled).
0826  */
0827 void kvm_mips_count_enable_cause(struct kvm_vcpu *vcpu)
0828 {
0829     struct mips_coproc *cop0 = vcpu->arch.cop0;
0830     u32 count;
0831 
0832     kvm_clear_c0_guest_cause(cop0, CAUSEF_DC);
0833 
0834     /*
0835      * Set the dynamic count to match the static count.
0836      * This starts the hrtimer if count_ctl.DC allows it.
0837      * Otherwise it conveniently updates the biases.
0838      */
0839     count = kvm_read_c0_guest_count(cop0);
0840     kvm_mips_write_count(vcpu, count);
0841 }
0842 
0843 /**
0844  * kvm_mips_set_count_ctl() - Update the count control KVM register.
0845  * @vcpu:   Virtual CPU.
0846  * @count_ctl:  Count control register new value.
0847  *
0848  * Set the count control KVM register. The timer is updated accordingly.
0849  *
0850  * Returns: -EINVAL if reserved bits are set.
0851  *      0 on success.
0852  */
0853 int kvm_mips_set_count_ctl(struct kvm_vcpu *vcpu, s64 count_ctl)
0854 {
0855     struct mips_coproc *cop0 = vcpu->arch.cop0;
0856     s64 changed = count_ctl ^ vcpu->arch.count_ctl;
0857     s64 delta;
0858     ktime_t expire, now;
0859     u32 count, compare;
0860 
0861     /* Only allow defined bits to be changed */
0862     if (changed & ~(s64)(KVM_REG_MIPS_COUNT_CTL_DC))
0863         return -EINVAL;
0864 
0865     /* Apply new value */
0866     vcpu->arch.count_ctl = count_ctl;
0867 
0868     /* Master CP0_Count disable */
0869     if (changed & KVM_REG_MIPS_COUNT_CTL_DC) {
0870         /* Is CP0_Cause.DC already disabling CP0_Count? */
0871         if (kvm_read_c0_guest_cause(cop0) & CAUSEF_DC) {
0872             if (count_ctl & KVM_REG_MIPS_COUNT_CTL_DC)
0873                 /* Just record the current time */
0874                 vcpu->arch.count_resume = ktime_get();
0875         } else if (count_ctl & KVM_REG_MIPS_COUNT_CTL_DC) {
0876             /* disable timer and record current time */
0877             vcpu->arch.count_resume = kvm_mips_count_disable(vcpu);
0878         } else {
0879             /*
0880              * Calculate timeout relative to static count at resume
0881              * time (wrap 0 to 2^32).
0882              */
0883             count = kvm_read_c0_guest_count(cop0);
0884             compare = kvm_read_c0_guest_compare(cop0);
0885             delta = (u64)(u32)(compare - count - 1) + 1;
0886             delta = div_u64(delta * NSEC_PER_SEC,
0887                     vcpu->arch.count_hz);
0888             expire = ktime_add_ns(vcpu->arch.count_resume, delta);
0889 
0890             /* Handle pending interrupt */
0891             now = ktime_get();
0892             if (ktime_compare(now, expire) >= 0)
0893                 /* Nothing should be waiting on the timeout */
0894                 kvm_mips_callbacks->queue_timer_int(vcpu);
0895 
0896             /* Resume hrtimer without changing bias */
0897             count = kvm_mips_read_count_running(vcpu, now);
0898             kvm_mips_resume_hrtimer(vcpu, now, count);
0899         }
0900     }
0901 
0902     return 0;
0903 }
0904 
0905 /**
0906  * kvm_mips_set_count_resume() - Update the count resume KVM register.
0907  * @vcpu:       Virtual CPU.
0908  * @count_resume:   Count resume register new value.
0909  *
0910  * Set the count resume KVM register.
0911  *
0912  * Returns: -EINVAL if out of valid range (0..now).
0913  *      0 on success.
0914  */
0915 int kvm_mips_set_count_resume(struct kvm_vcpu *vcpu, s64 count_resume)
0916 {
0917     /*
0918      * It doesn't make sense for the resume time to be in the future, as it
0919      * would be possible for the next interrupt to be more than a full
0920      * period in the future.
0921      */
0922     if (count_resume < 0 || count_resume > ktime_to_ns(ktime_get()))
0923         return -EINVAL;
0924 
0925     vcpu->arch.count_resume = ns_to_ktime(count_resume);
0926     return 0;
0927 }
0928 
0929 /**
0930  * kvm_mips_count_timeout() - Push timer forward on timeout.
0931  * @vcpu:   Virtual CPU.
0932  *
0933  * Handle an hrtimer event by push the hrtimer forward a period.
0934  *
0935  * Returns: The hrtimer_restart value to return to the hrtimer subsystem.
0936  */
0937 enum hrtimer_restart kvm_mips_count_timeout(struct kvm_vcpu *vcpu)
0938 {
0939     /* Add the Count period to the current expiry time */
0940     hrtimer_add_expires_ns(&vcpu->arch.comparecount_timer,
0941                    vcpu->arch.count_period);
0942     return HRTIMER_RESTART;
0943 }
0944 
0945 enum emulation_result kvm_mips_emul_wait(struct kvm_vcpu *vcpu)
0946 {
0947     kvm_debug("[%#lx] !!!WAIT!!! (%#lx)\n", vcpu->arch.pc,
0948           vcpu->arch.pending_exceptions);
0949 
0950     ++vcpu->stat.wait_exits;
0951     trace_kvm_exit(vcpu, KVM_TRACE_EXIT_WAIT);
0952     if (!vcpu->arch.pending_exceptions) {
0953         kvm_vz_lose_htimer(vcpu);
0954         vcpu->arch.wait = 1;
0955         kvm_vcpu_halt(vcpu);
0956 
0957         /*
0958          * We we are runnable, then definitely go off to user space to
0959          * check if any I/O interrupts are pending.
0960          */
0961         if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
0962             kvm_clear_request(KVM_REQ_UNHALT, vcpu);
0963             vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
0964         }
0965     }
0966 
0967     return EMULATE_DONE;
0968 }
0969 
0970 enum emulation_result kvm_mips_emulate_store(union mips_instruction inst,
0971                          u32 cause,
0972                          struct kvm_vcpu *vcpu)
0973 {
0974     int r;
0975     enum emulation_result er;
0976     u32 rt;
0977     struct kvm_run *run = vcpu->run;
0978     void *data = run->mmio.data;
0979     unsigned int imme;
0980     unsigned long curr_pc;
0981 
0982     /*
0983      * Update PC and hold onto current PC in case there is
0984      * an error and we want to rollback the PC
0985      */
0986     curr_pc = vcpu->arch.pc;
0987     er = update_pc(vcpu, cause);
0988     if (er == EMULATE_FAIL)
0989         return er;
0990 
0991     rt = inst.i_format.rt;
0992 
0993     run->mmio.phys_addr = kvm_mips_callbacks->gva_to_gpa(
0994                         vcpu->arch.host_cp0_badvaddr);
0995     if (run->mmio.phys_addr == KVM_INVALID_ADDR)
0996         goto out_fail;
0997 
0998     switch (inst.i_format.opcode) {
0999 #if defined(CONFIG_64BIT)
1000     case sd_op:
1001         run->mmio.len = 8;
1002         *(u64 *)data = vcpu->arch.gprs[rt];
1003 
1004         kvm_debug("[%#lx] OP_SD: eaddr: %#lx, gpr: %#lx, data: %#llx\n",
1005               vcpu->arch.pc, vcpu->arch.host_cp0_badvaddr,
1006               vcpu->arch.gprs[rt], *(u64 *)data);
1007         break;
1008 #endif
1009 
1010     case sw_op:
1011         run->mmio.len = 4;
1012         *(u32 *)data = vcpu->arch.gprs[rt];
1013 
1014         kvm_debug("[%#lx] OP_SW: eaddr: %#lx, gpr: %#lx, data: %#x\n",
1015               vcpu->arch.pc, vcpu->arch.host_cp0_badvaddr,
1016               vcpu->arch.gprs[rt], *(u32 *)data);
1017         break;
1018 
1019     case sh_op:
1020         run->mmio.len = 2;
1021         *(u16 *)data = vcpu->arch.gprs[rt];
1022 
1023         kvm_debug("[%#lx] OP_SH: eaddr: %#lx, gpr: %#lx, data: %#x\n",
1024               vcpu->arch.pc, vcpu->arch.host_cp0_badvaddr,
1025               vcpu->arch.gprs[rt], *(u16 *)data);
1026         break;
1027 
1028     case sb_op:
1029         run->mmio.len = 1;
1030         *(u8 *)data = vcpu->arch.gprs[rt];
1031 
1032         kvm_debug("[%#lx] OP_SB: eaddr: %#lx, gpr: %#lx, data: %#x\n",
1033               vcpu->arch.pc, vcpu->arch.host_cp0_badvaddr,
1034               vcpu->arch.gprs[rt], *(u8 *)data);
1035         break;
1036 
1037     case swl_op:
1038         run->mmio.phys_addr = kvm_mips_callbacks->gva_to_gpa(
1039                     vcpu->arch.host_cp0_badvaddr) & (~0x3);
1040         run->mmio.len = 4;
1041         imme = vcpu->arch.host_cp0_badvaddr & 0x3;
1042         switch (imme) {
1043         case 0:
1044             *(u32 *)data = ((*(u32 *)data) & 0xffffff00) |
1045                     (vcpu->arch.gprs[rt] >> 24);
1046             break;
1047         case 1:
1048             *(u32 *)data = ((*(u32 *)data) & 0xffff0000) |
1049                     (vcpu->arch.gprs[rt] >> 16);
1050             break;
1051         case 2:
1052             *(u32 *)data = ((*(u32 *)data) & 0xff000000) |
1053                     (vcpu->arch.gprs[rt] >> 8);
1054             break;
1055         case 3:
1056             *(u32 *)data = vcpu->arch.gprs[rt];
1057             break;
1058         default:
1059             break;
1060         }
1061 
1062         kvm_debug("[%#lx] OP_SWL: eaddr: %#lx, gpr: %#lx, data: %#x\n",
1063               vcpu->arch.pc, vcpu->arch.host_cp0_badvaddr,
1064               vcpu->arch.gprs[rt], *(u32 *)data);
1065         break;
1066 
1067     case swr_op:
1068         run->mmio.phys_addr = kvm_mips_callbacks->gva_to_gpa(
1069                     vcpu->arch.host_cp0_badvaddr) & (~0x3);
1070         run->mmio.len = 4;
1071         imme = vcpu->arch.host_cp0_badvaddr & 0x3;
1072         switch (imme) {
1073         case 0:
1074             *(u32 *)data = vcpu->arch.gprs[rt];
1075             break;
1076         case 1:
1077             *(u32 *)data = ((*(u32 *)data) & 0xff) |
1078                     (vcpu->arch.gprs[rt] << 8);
1079             break;
1080         case 2:
1081             *(u32 *)data = ((*(u32 *)data) & 0xffff) |
1082                     (vcpu->arch.gprs[rt] << 16);
1083             break;
1084         case 3:
1085             *(u32 *)data = ((*(u32 *)data) & 0xffffff) |
1086                     (vcpu->arch.gprs[rt] << 24);
1087             break;
1088         default:
1089             break;
1090         }
1091 
1092         kvm_debug("[%#lx] OP_SWR: eaddr: %#lx, gpr: %#lx, data: %#x\n",
1093               vcpu->arch.pc, vcpu->arch.host_cp0_badvaddr,
1094               vcpu->arch.gprs[rt], *(u32 *)data);
1095         break;
1096 
1097 #if defined(CONFIG_64BIT)
1098     case sdl_op:
1099         run->mmio.phys_addr = kvm_mips_callbacks->gva_to_gpa(
1100                     vcpu->arch.host_cp0_badvaddr) & (~0x7);
1101 
1102         run->mmio.len = 8;
1103         imme = vcpu->arch.host_cp0_badvaddr & 0x7;
1104         switch (imme) {
1105         case 0:
1106             *(u64 *)data = ((*(u64 *)data) & 0xffffffffffffff00) |
1107                     ((vcpu->arch.gprs[rt] >> 56) & 0xff);
1108             break;
1109         case 1:
1110             *(u64 *)data = ((*(u64 *)data) & 0xffffffffffff0000) |
1111                     ((vcpu->arch.gprs[rt] >> 48) & 0xffff);
1112             break;
1113         case 2:
1114             *(u64 *)data = ((*(u64 *)data) & 0xffffffffff000000) |
1115                     ((vcpu->arch.gprs[rt] >> 40) & 0xffffff);
1116             break;
1117         case 3:
1118             *(u64 *)data = ((*(u64 *)data) & 0xffffffff00000000) |
1119                     ((vcpu->arch.gprs[rt] >> 32) & 0xffffffff);
1120             break;
1121         case 4:
1122             *(u64 *)data = ((*(u64 *)data) & 0xffffff0000000000) |
1123                     ((vcpu->arch.gprs[rt] >> 24) & 0xffffffffff);
1124             break;
1125         case 5:
1126             *(u64 *)data = ((*(u64 *)data) & 0xffff000000000000) |
1127                     ((vcpu->arch.gprs[rt] >> 16) & 0xffffffffffff);
1128             break;
1129         case 6:
1130             *(u64 *)data = ((*(u64 *)data) & 0xff00000000000000) |
1131                     ((vcpu->arch.gprs[rt] >> 8) & 0xffffffffffffff);
1132             break;
1133         case 7:
1134             *(u64 *)data = vcpu->arch.gprs[rt];
1135             break;
1136         default:
1137             break;
1138         }
1139 
1140         kvm_debug("[%#lx] OP_SDL: eaddr: %#lx, gpr: %#lx, data: %llx\n",
1141               vcpu->arch.pc, vcpu->arch.host_cp0_badvaddr,
1142               vcpu->arch.gprs[rt], *(u64 *)data);
1143         break;
1144 
1145     case sdr_op:
1146         run->mmio.phys_addr = kvm_mips_callbacks->gva_to_gpa(
1147                     vcpu->arch.host_cp0_badvaddr) & (~0x7);
1148 
1149         run->mmio.len = 8;
1150         imme = vcpu->arch.host_cp0_badvaddr & 0x7;
1151         switch (imme) {
1152         case 0:
1153             *(u64 *)data = vcpu->arch.gprs[rt];
1154             break;
1155         case 1:
1156             *(u64 *)data = ((*(u64 *)data) & 0xff) |
1157                     (vcpu->arch.gprs[rt] << 8);
1158             break;
1159         case 2:
1160             *(u64 *)data = ((*(u64 *)data) & 0xffff) |
1161                     (vcpu->arch.gprs[rt] << 16);
1162             break;
1163         case 3:
1164             *(u64 *)data = ((*(u64 *)data) & 0xffffff) |
1165                     (vcpu->arch.gprs[rt] << 24);
1166             break;
1167         case 4:
1168             *(u64 *)data = ((*(u64 *)data) & 0xffffffff) |
1169                     (vcpu->arch.gprs[rt] << 32);
1170             break;
1171         case 5:
1172             *(u64 *)data = ((*(u64 *)data) & 0xffffffffff) |
1173                     (vcpu->arch.gprs[rt] << 40);
1174             break;
1175         case 6:
1176             *(u64 *)data = ((*(u64 *)data) & 0xffffffffffff) |
1177                     (vcpu->arch.gprs[rt] << 48);
1178             break;
1179         case 7:
1180             *(u64 *)data = ((*(u64 *)data) & 0xffffffffffffff) |
1181                     (vcpu->arch.gprs[rt] << 56);
1182             break;
1183         default:
1184             break;
1185         }
1186 
1187         kvm_debug("[%#lx] OP_SDR: eaddr: %#lx, gpr: %#lx, data: %llx\n",
1188               vcpu->arch.pc, vcpu->arch.host_cp0_badvaddr,
1189               vcpu->arch.gprs[rt], *(u64 *)data);
1190         break;
1191 #endif
1192 
1193 #ifdef CONFIG_CPU_LOONGSON64
1194     case sdc2_op:
1195         rt = inst.loongson3_lsdc2_format.rt;
1196         switch (inst.loongson3_lsdc2_format.opcode1) {
1197         /*
1198          * Loongson-3 overridden sdc2 instructions.
1199          * opcode1              instruction
1200          *   0x0          gssbx: store 1 bytes from GPR
1201          *   0x1          gsshx: store 2 bytes from GPR
1202          *   0x2          gsswx: store 4 bytes from GPR
1203          *   0x3          gssdx: store 8 bytes from GPR
1204          */
1205         case 0x0:
1206             run->mmio.len = 1;
1207             *(u8 *)data = vcpu->arch.gprs[rt];
1208 
1209             kvm_debug("[%#lx] OP_GSSBX: eaddr: %#lx, gpr: %#lx, data: %#x\n",
1210                   vcpu->arch.pc, vcpu->arch.host_cp0_badvaddr,
1211                   vcpu->arch.gprs[rt], *(u8 *)data);
1212             break;
1213         case 0x1:
1214             run->mmio.len = 2;
1215             *(u16 *)data = vcpu->arch.gprs[rt];
1216 
1217             kvm_debug("[%#lx] OP_GSSSHX: eaddr: %#lx, gpr: %#lx, data: %#x\n",
1218                   vcpu->arch.pc, vcpu->arch.host_cp0_badvaddr,
1219                   vcpu->arch.gprs[rt], *(u16 *)data);
1220             break;
1221         case 0x2:
1222             run->mmio.len = 4;
1223             *(u32 *)data = vcpu->arch.gprs[rt];
1224 
1225             kvm_debug("[%#lx] OP_GSSWX: eaddr: %#lx, gpr: %#lx, data: %#x\n",
1226                   vcpu->arch.pc, vcpu->arch.host_cp0_badvaddr,
1227                   vcpu->arch.gprs[rt], *(u32 *)data);
1228             break;
1229         case 0x3:
1230             run->mmio.len = 8;
1231             *(u64 *)data = vcpu->arch.gprs[rt];
1232 
1233             kvm_debug("[%#lx] OP_GSSDX: eaddr: %#lx, gpr: %#lx, data: %#llx\n",
1234                   vcpu->arch.pc, vcpu->arch.host_cp0_badvaddr,
1235                   vcpu->arch.gprs[rt], *(u64 *)data);
1236             break;
1237         default:
1238             kvm_err("Godson Extended GS-Store not yet supported (inst=0x%08x)\n",
1239                 inst.word);
1240             break;
1241         }
1242         break;
1243 #endif
1244     default:
1245         kvm_err("Store not yet supported (inst=0x%08x)\n",
1246             inst.word);
1247         goto out_fail;
1248     }
1249 
1250     vcpu->mmio_needed = 1;
1251     run->mmio.is_write = 1;
1252     vcpu->mmio_is_write = 1;
1253 
1254     r = kvm_io_bus_write(vcpu, KVM_MMIO_BUS,
1255             run->mmio.phys_addr, run->mmio.len, data);
1256 
1257     if (!r) {
1258         vcpu->mmio_needed = 0;
1259         return EMULATE_DONE;
1260     }
1261 
1262     return EMULATE_DO_MMIO;
1263 
1264 out_fail:
1265     /* Rollback PC if emulation was unsuccessful */
1266     vcpu->arch.pc = curr_pc;
1267     return EMULATE_FAIL;
1268 }
1269 
1270 enum emulation_result kvm_mips_emulate_load(union mips_instruction inst,
1271                         u32 cause, struct kvm_vcpu *vcpu)
1272 {
1273     struct kvm_run *run = vcpu->run;
1274     int r;
1275     enum emulation_result er;
1276     unsigned long curr_pc;
1277     u32 op, rt;
1278     unsigned int imme;
1279 
1280     rt = inst.i_format.rt;
1281     op = inst.i_format.opcode;
1282 
1283     /*
1284      * Find the resume PC now while we have safe and easy access to the
1285      * prior branch instruction, and save it for
1286      * kvm_mips_complete_mmio_load() to restore later.
1287      */
1288     curr_pc = vcpu->arch.pc;
1289     er = update_pc(vcpu, cause);
1290     if (er == EMULATE_FAIL)
1291         return er;
1292     vcpu->arch.io_pc = vcpu->arch.pc;
1293     vcpu->arch.pc = curr_pc;
1294 
1295     vcpu->arch.io_gpr = rt;
1296 
1297     run->mmio.phys_addr = kvm_mips_callbacks->gva_to_gpa(
1298                         vcpu->arch.host_cp0_badvaddr);
1299     if (run->mmio.phys_addr == KVM_INVALID_ADDR)
1300         return EMULATE_FAIL;
1301 
1302     vcpu->mmio_needed = 2;  /* signed */
1303     switch (op) {
1304 #if defined(CONFIG_64BIT)
1305     case ld_op:
1306         run->mmio.len = 8;
1307         break;
1308 
1309     case lwu_op:
1310         vcpu->mmio_needed = 1;  /* unsigned */
1311         fallthrough;
1312 #endif
1313     case lw_op:
1314         run->mmio.len = 4;
1315         break;
1316 
1317     case lhu_op:
1318         vcpu->mmio_needed = 1;  /* unsigned */
1319         fallthrough;
1320     case lh_op:
1321         run->mmio.len = 2;
1322         break;
1323 
1324     case lbu_op:
1325         vcpu->mmio_needed = 1;  /* unsigned */
1326         fallthrough;
1327     case lb_op:
1328         run->mmio.len = 1;
1329         break;
1330 
1331     case lwl_op:
1332         run->mmio.phys_addr = kvm_mips_callbacks->gva_to_gpa(
1333                     vcpu->arch.host_cp0_badvaddr) & (~0x3);
1334 
1335         run->mmio.len = 4;
1336         imme = vcpu->arch.host_cp0_badvaddr & 0x3;
1337         switch (imme) {
1338         case 0:
1339             vcpu->mmio_needed = 3;  /* 1 byte */
1340             break;
1341         case 1:
1342             vcpu->mmio_needed = 4;  /* 2 bytes */
1343             break;
1344         case 2:
1345             vcpu->mmio_needed = 5;  /* 3 bytes */
1346             break;
1347         case 3:
1348             vcpu->mmio_needed = 6;  /* 4 bytes */
1349             break;
1350         default:
1351             break;
1352         }
1353         break;
1354 
1355     case lwr_op:
1356         run->mmio.phys_addr = kvm_mips_callbacks->gva_to_gpa(
1357                     vcpu->arch.host_cp0_badvaddr) & (~0x3);
1358 
1359         run->mmio.len = 4;
1360         imme = vcpu->arch.host_cp0_badvaddr & 0x3;
1361         switch (imme) {
1362         case 0:
1363             vcpu->mmio_needed = 7;  /* 4 bytes */
1364             break;
1365         case 1:
1366             vcpu->mmio_needed = 8;  /* 3 bytes */
1367             break;
1368         case 2:
1369             vcpu->mmio_needed = 9;  /* 2 bytes */
1370             break;
1371         case 3:
1372             vcpu->mmio_needed = 10; /* 1 byte */
1373             break;
1374         default:
1375             break;
1376         }
1377         break;
1378 
1379 #if defined(CONFIG_64BIT)
1380     case ldl_op:
1381         run->mmio.phys_addr = kvm_mips_callbacks->gva_to_gpa(
1382                     vcpu->arch.host_cp0_badvaddr) & (~0x7);
1383 
1384         run->mmio.len = 8;
1385         imme = vcpu->arch.host_cp0_badvaddr & 0x7;
1386         switch (imme) {
1387         case 0:
1388             vcpu->mmio_needed = 11; /* 1 byte */
1389             break;
1390         case 1:
1391             vcpu->mmio_needed = 12; /* 2 bytes */
1392             break;
1393         case 2:
1394             vcpu->mmio_needed = 13; /* 3 bytes */
1395             break;
1396         case 3:
1397             vcpu->mmio_needed = 14; /* 4 bytes */
1398             break;
1399         case 4:
1400             vcpu->mmio_needed = 15; /* 5 bytes */
1401             break;
1402         case 5:
1403             vcpu->mmio_needed = 16; /* 6 bytes */
1404             break;
1405         case 6:
1406             vcpu->mmio_needed = 17; /* 7 bytes */
1407             break;
1408         case 7:
1409             vcpu->mmio_needed = 18; /* 8 bytes */
1410             break;
1411         default:
1412             break;
1413         }
1414         break;
1415 
1416     case ldr_op:
1417         run->mmio.phys_addr = kvm_mips_callbacks->gva_to_gpa(
1418                     vcpu->arch.host_cp0_badvaddr) & (~0x7);
1419 
1420         run->mmio.len = 8;
1421         imme = vcpu->arch.host_cp0_badvaddr & 0x7;
1422         switch (imme) {
1423         case 0:
1424             vcpu->mmio_needed = 19; /* 8 bytes */
1425             break;
1426         case 1:
1427             vcpu->mmio_needed = 20; /* 7 bytes */
1428             break;
1429         case 2:
1430             vcpu->mmio_needed = 21; /* 6 bytes */
1431             break;
1432         case 3:
1433             vcpu->mmio_needed = 22; /* 5 bytes */
1434             break;
1435         case 4:
1436             vcpu->mmio_needed = 23; /* 4 bytes */
1437             break;
1438         case 5:
1439             vcpu->mmio_needed = 24; /* 3 bytes */
1440             break;
1441         case 6:
1442             vcpu->mmio_needed = 25; /* 2 bytes */
1443             break;
1444         case 7:
1445             vcpu->mmio_needed = 26; /* 1 byte */
1446             break;
1447         default:
1448             break;
1449         }
1450         break;
1451 #endif
1452 
1453 #ifdef CONFIG_CPU_LOONGSON64
1454     case ldc2_op:
1455         rt = inst.loongson3_lsdc2_format.rt;
1456         switch (inst.loongson3_lsdc2_format.opcode1) {
1457         /*
1458          * Loongson-3 overridden ldc2 instructions.
1459          * opcode1              instruction
1460          *   0x0          gslbx: store 1 bytes from GPR
1461          *   0x1          gslhx: store 2 bytes from GPR
1462          *   0x2          gslwx: store 4 bytes from GPR
1463          *   0x3          gsldx: store 8 bytes from GPR
1464          */
1465         case 0x0:
1466             run->mmio.len = 1;
1467             vcpu->mmio_needed = 27; /* signed */
1468             break;
1469         case 0x1:
1470             run->mmio.len = 2;
1471             vcpu->mmio_needed = 28; /* signed */
1472             break;
1473         case 0x2:
1474             run->mmio.len = 4;
1475             vcpu->mmio_needed = 29; /* signed */
1476             break;
1477         case 0x3:
1478             run->mmio.len = 8;
1479             vcpu->mmio_needed = 30; /* signed */
1480             break;
1481         default:
1482             kvm_err("Godson Extended GS-Load for float not yet supported (inst=0x%08x)\n",
1483                 inst.word);
1484             break;
1485         }
1486         break;
1487 #endif
1488 
1489     default:
1490         kvm_err("Load not yet supported (inst=0x%08x)\n",
1491             inst.word);
1492         vcpu->mmio_needed = 0;
1493         return EMULATE_FAIL;
1494     }
1495 
1496     run->mmio.is_write = 0;
1497     vcpu->mmio_is_write = 0;
1498 
1499     r = kvm_io_bus_read(vcpu, KVM_MMIO_BUS,
1500             run->mmio.phys_addr, run->mmio.len, run->mmio.data);
1501 
1502     if (!r) {
1503         kvm_mips_complete_mmio_load(vcpu);
1504         vcpu->mmio_needed = 0;
1505         return EMULATE_DONE;
1506     }
1507 
1508     return EMULATE_DO_MMIO;
1509 }
1510 
1511 enum emulation_result kvm_mips_complete_mmio_load(struct kvm_vcpu *vcpu)
1512 {
1513     struct kvm_run *run = vcpu->run;
1514     unsigned long *gpr = &vcpu->arch.gprs[vcpu->arch.io_gpr];
1515     enum emulation_result er = EMULATE_DONE;
1516 
1517     if (run->mmio.len > sizeof(*gpr)) {
1518         kvm_err("Bad MMIO length: %d", run->mmio.len);
1519         er = EMULATE_FAIL;
1520         goto done;
1521     }
1522 
1523     /* Restore saved resume PC */
1524     vcpu->arch.pc = vcpu->arch.io_pc;
1525 
1526     switch (run->mmio.len) {
1527     case 8:
1528         switch (vcpu->mmio_needed) {
1529         case 11:
1530             *gpr = (vcpu->arch.gprs[vcpu->arch.io_gpr] & 0xffffffffffffff) |
1531                 (((*(s64 *)run->mmio.data) & 0xff) << 56);
1532             break;
1533         case 12:
1534             *gpr = (vcpu->arch.gprs[vcpu->arch.io_gpr] & 0xffffffffffff) |
1535                 (((*(s64 *)run->mmio.data) & 0xffff) << 48);
1536             break;
1537         case 13:
1538             *gpr = (vcpu->arch.gprs[vcpu->arch.io_gpr] & 0xffffffffff) |
1539                 (((*(s64 *)run->mmio.data) & 0xffffff) << 40);
1540             break;
1541         case 14:
1542             *gpr = (vcpu->arch.gprs[vcpu->arch.io_gpr] & 0xffffffff) |
1543                 (((*(s64 *)run->mmio.data) & 0xffffffff) << 32);
1544             break;
1545         case 15:
1546             *gpr = (vcpu->arch.gprs[vcpu->arch.io_gpr] & 0xffffff) |
1547                 (((*(s64 *)run->mmio.data) & 0xffffffffff) << 24);
1548             break;
1549         case 16:
1550             *gpr = (vcpu->arch.gprs[vcpu->arch.io_gpr] & 0xffff) |
1551                 (((*(s64 *)run->mmio.data) & 0xffffffffffff) << 16);
1552             break;
1553         case 17:
1554             *gpr = (vcpu->arch.gprs[vcpu->arch.io_gpr] & 0xff) |
1555                 (((*(s64 *)run->mmio.data) & 0xffffffffffffff) << 8);
1556             break;
1557         case 18:
1558         case 19:
1559             *gpr = *(s64 *)run->mmio.data;
1560             break;
1561         case 20:
1562             *gpr = (vcpu->arch.gprs[vcpu->arch.io_gpr] & 0xff00000000000000) |
1563                 ((((*(s64 *)run->mmio.data)) >> 8) & 0xffffffffffffff);
1564             break;
1565         case 21:
1566             *gpr = (vcpu->arch.gprs[vcpu->arch.io_gpr] & 0xffff000000000000) |
1567                 ((((*(s64 *)run->mmio.data)) >> 16) & 0xffffffffffff);
1568             break;
1569         case 22:
1570             *gpr = (vcpu->arch.gprs[vcpu->arch.io_gpr] & 0xffffff0000000000) |
1571                 ((((*(s64 *)run->mmio.data)) >> 24) & 0xffffffffff);
1572             break;
1573         case 23:
1574             *gpr = (vcpu->arch.gprs[vcpu->arch.io_gpr] & 0xffffffff00000000) |
1575                 ((((*(s64 *)run->mmio.data)) >> 32) & 0xffffffff);
1576             break;
1577         case 24:
1578             *gpr = (vcpu->arch.gprs[vcpu->arch.io_gpr] & 0xffffffffff000000) |
1579                 ((((*(s64 *)run->mmio.data)) >> 40) & 0xffffff);
1580             break;
1581         case 25:
1582             *gpr = (vcpu->arch.gprs[vcpu->arch.io_gpr] & 0xffffffffffff0000) |
1583                 ((((*(s64 *)run->mmio.data)) >> 48) & 0xffff);
1584             break;
1585         case 26:
1586             *gpr = (vcpu->arch.gprs[vcpu->arch.io_gpr] & 0xffffffffffffff00) |
1587                 ((((*(s64 *)run->mmio.data)) >> 56) & 0xff);
1588             break;
1589         default:
1590             *gpr = *(s64 *)run->mmio.data;
1591         }
1592         break;
1593 
1594     case 4:
1595         switch (vcpu->mmio_needed) {
1596         case 1:
1597             *gpr = *(u32 *)run->mmio.data;
1598             break;
1599         case 2:
1600             *gpr = *(s32 *)run->mmio.data;
1601             break;
1602         case 3:
1603             *gpr = (vcpu->arch.gprs[vcpu->arch.io_gpr] & 0xffffff) |
1604                 (((*(s32 *)run->mmio.data) & 0xff) << 24);
1605             break;
1606         case 4:
1607             *gpr = (vcpu->arch.gprs[vcpu->arch.io_gpr] & 0xffff) |
1608                 (((*(s32 *)run->mmio.data) & 0xffff) << 16);
1609             break;
1610         case 5:
1611             *gpr = (vcpu->arch.gprs[vcpu->arch.io_gpr] & 0xff) |
1612                 (((*(s32 *)run->mmio.data) & 0xffffff) << 8);
1613             break;
1614         case 6:
1615         case 7:
1616             *gpr = *(s32 *)run->mmio.data;
1617             break;
1618         case 8:
1619             *gpr = (vcpu->arch.gprs[vcpu->arch.io_gpr] & 0xff000000) |
1620                 ((((*(s32 *)run->mmio.data)) >> 8) & 0xffffff);
1621             break;
1622         case 9:
1623             *gpr = (vcpu->arch.gprs[vcpu->arch.io_gpr] & 0xffff0000) |
1624                 ((((*(s32 *)run->mmio.data)) >> 16) & 0xffff);
1625             break;
1626         case 10:
1627             *gpr = (vcpu->arch.gprs[vcpu->arch.io_gpr] & 0xffffff00) |
1628                 ((((*(s32 *)run->mmio.data)) >> 24) & 0xff);
1629             break;
1630         default:
1631             *gpr = *(s32 *)run->mmio.data;
1632         }
1633         break;
1634 
1635     case 2:
1636         if (vcpu->mmio_needed == 1)
1637             *gpr = *(u16 *)run->mmio.data;
1638         else
1639             *gpr = *(s16 *)run->mmio.data;
1640 
1641         break;
1642     case 1:
1643         if (vcpu->mmio_needed == 1)
1644             *gpr = *(u8 *)run->mmio.data;
1645         else
1646             *gpr = *(s8 *)run->mmio.data;
1647         break;
1648     }
1649 
1650 done:
1651     return er;
1652 }
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