mips/kernel/unaligned.c

0001 /*
0002  * Handle unaligned accesses by emulation.
0003  *
0004  * This file is subject to the terms and conditions of the GNU General Public
0005  * License.  See the file "COPYING" in the main directory of this archive
0006  * for more details.
0007  *
0008  * Copyright (C) 1996, 1998, 1999, 2002 by Ralf Baechle
0009  * Copyright (C) 1999 Silicon Graphics, Inc.
0010  * Copyright (C) 2014 Imagination Technologies Ltd.
0011  *
0012  * This file contains exception handler for address error exception with the
0013  * special capability to execute faulting instructions in software.  The
0014  * handler does not try to handle the case when the program counter points
0015  * to an address not aligned to a word boundary.
0016  *
0017  * Putting data to unaligned addresses is a bad practice even on Intel where
0018  * only the performance is affected.  Much worse is that such code is non-
0019  * portable.  Due to several programs that die on MIPS due to alignment
0020  * problems I decided to implement this handler anyway though I originally
0021  * didn't intend to do this at all for user code.
0022  *
0023  * For now I enable fixing of address errors by default to make life easier.
0024  * I however intend to disable this somewhen in the future when the alignment
0025  * problems with user programs have been fixed.  For programmers this is the
0026  * right way to go.
0027  *
0028  * Fixing address errors is a per process option.  The option is inherited
0029  * across fork(2) and execve(2) calls.  If you really want to use the
0030  * option in your user programs - I discourage the use of the software
0031  * emulation strongly - use the following code in your userland stuff:
0032  *
0033  * #include <sys/sysmips.h>
0034  *
0035  * ...
0036  * sysmips(MIPS_FIXADE, x);
0037  * ...
0038  *
0039  * The argument x is 0 for disabling software emulation, enabled otherwise.
0040  *
0041  * Below a little program to play around with this feature.
0042  *
0043  * #include <stdio.h>
0044  * #include <sys/sysmips.h>
0045  *
0046  * struct foo {
0047  *     unsigned char bar[8];
0048  * };
0049  *
0050  * main(int argc, char *argv[])
0051  * {
0052  *     struct foo x = {0, 1, 2, 3, 4, 5, 6, 7};
0053  *     unsigned int *p = (unsigned int *) (x.bar + 3);
0054  *     int i;
0055  *
0056  *     if (argc > 1)
0057  *         sysmips(MIPS_FIXADE, atoi(argv[1]));
0058  *
0059  *     printf("*p = %08lx\n", *p);
0060  *
0061  *     *p = 0xdeadface;
0062  *
0063  *     for(i = 0; i <= 7; i++)
0064  *     printf("%02x ", x.bar[i]);
0065  *     printf("\n");
0066  * }
0067  *
0068  * Coprocessor loads are not supported; I think this case is unimportant
0069  * in the practice.
0070  *
0071  * TODO: Handle ndc (attempted store to doubleword in uncached memory)
0072  *   exception for the R6000.
0073  *   A store crossing a page boundary might be executed only partially.
0074  *   Undo the partial store in this case.
0075  */
0076 #include <linux/context_tracking.h>
0077 #include <linux/mm.h>
0078 #include <linux/signal.h>
0079 #include <linux/smp.h>
0080 #include <linux/sched.h>
0081 #include <linux/debugfs.h>
0082 #include <linux/perf_event.h>
0083
0084 #include <asm/asm.h>
0085 #include <asm/branch.h>
0086 #include <asm/byteorder.h>
0087 #include <asm/cop2.h>
0088 #include <asm/debug.h>
0089 #include <asm/fpu.h>
0090 #include <asm/fpu_emulator.h>
0091 #include <asm/inst.h>
0092 #include <asm/unaligned-emul.h>
0093 #include <asm/mmu_context.h>
0094 #include <linux/uaccess.h>
0095
0096 #include "access-helper.h"
0097
0098 enum {
0099     UNALIGNED_ACTION_QUIET,
0100     UNALIGNED_ACTION_SIGNAL,
0101     UNALIGNED_ACTION_SHOW,
0102 };
0103 #ifdef CONFIG_DEBUG_FS
0104 static u32 unaligned_instructions;
0105 static u32 unaligned_action;
0106 #else
0107 #define unaligned_action UNALIGNED_ACTION_QUIET
0108 #endif
0109 extern void show_registers(struct pt_regs *regs);
0110
0111 static void emulate_load_store_insn(struct pt_regs *regs,
0112     void __user *addr, unsigned int *pc)
0113 {
0114     unsigned long origpc, orig31, value;
0115     union mips_instruction insn;
0116     unsigned int res;
0117     bool user = user_mode(regs);
0118
0119     origpc = (unsigned long)pc;
0120     orig31 = regs->regs[31];
0121
0122     perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0);
0123
0124     /*
0125      * This load never faults.
0126      */
0127     __get_inst32(&insn.word, pc, user);
0128
0129     switch (insn.i_format.opcode) {
0130         /*
0131          * These are instructions that a compiler doesn't generate.  We
0132          * can assume therefore that the code is MIPS-aware and
0133          * really buggy.  Emulating these instructions would break the
0134          * semantics anyway.
0135          */
0136     case ll_op:
0137     case lld_op:
0138     case sc_op:
0139     case scd_op:
0140
0141         /*
0142          * For these instructions the only way to create an address
0143          * error is an attempted access to kernel/supervisor address
0144          * space.
0145          */
0146     case ldl_op:
0147     case ldr_op:
0148     case lwl_op:
0149     case lwr_op:
0150     case sdl_op:
0151     case sdr_op:
0152     case swl_op:
0153     case swr_op:
0154     case lb_op:
0155     case lbu_op:
0156     case sb_op:
0157         goto sigbus;
0158
0159         /*
0160          * The remaining opcodes are the ones that are really of
0161          * interest.
0162          */
0163     case spec3_op:
0164         if (insn.dsp_format.func == lx_op) {
0165             switch (insn.dsp_format.op) {
0166             case lwx_op:
0167                 if (user && !access_ok(addr, 4))
0168                     goto sigbus;
0169                 LoadW(addr, value, res);
0170                 if (res)
0171                     goto fault;
0172                 compute_return_epc(regs);
0173                 regs->regs[insn.dsp_format.rd] = value;
0174                 break;
0175             case lhx_op:
0176                 if (user && !access_ok(addr, 2))
0177                     goto sigbus;
0178                 LoadHW(addr, value, res);
0179                 if (res)
0180                     goto fault;
0181                 compute_return_epc(regs);
0182                 regs->regs[insn.dsp_format.rd] = value;
0183                 break;
0184             default:
0185                 goto sigill;
0186             }
0187         }
0188 #ifdef CONFIG_EVA
0189         else {
0190             /*
0191              * we can land here only from kernel accessing user
0192              * memory, so we need to "switch" the address limit to
0193              * user space, so that address check can work properly.
0194              */
0195             switch (insn.spec3_format.func) {
0196             case lhe_op:
0197                 if (!access_ok(addr, 2))
0198                     goto sigbus;
0199                 LoadHWE(addr, value, res);
0200                 if (res)
0201                     goto fault;
0202                 compute_return_epc(regs);
0203                 regs->regs[insn.spec3_format.rt] = value;
0204                 break;
0205             case lwe_op:
0206                 if (!access_ok(addr, 4))
0207                     goto sigbus;
0208                 LoadWE(addr, value, res);
0209                 if (res)
0210                     goto fault;
0211                 compute_return_epc(regs);
0212                 regs->regs[insn.spec3_format.rt] = value;
0213                 break;
0214             case lhue_op:
0215                 if (!access_ok(addr, 2))
0216                     goto sigbus;
0217                 LoadHWUE(addr, value, res);
0218                 if (res)
0219                     goto fault;
0220                 compute_return_epc(regs);
0221                 regs->regs[insn.spec3_format.rt] = value;
0222                 break;
0223             case she_op:
0224                 if (!access_ok(addr, 2))
0225                     goto sigbus;
0226                 compute_return_epc(regs);
0227                 value = regs->regs[insn.spec3_format.rt];
0228                 StoreHWE(addr, value, res);
0229                 if (res)
0230                     goto fault;
0231                 break;
0232             case swe_op:
0233                 if (!access_ok(addr, 4))
0234                     goto sigbus;
0235                 compute_return_epc(regs);
0236                 value = regs->regs[insn.spec3_format.rt];
0237                 StoreWE(addr, value, res);
0238                 if (res)
0239                     goto fault;
0240                 break;
0241             default:
0242                 goto sigill;
0243             }
0244         }
0245 #endif
0246         break;
0247     case lh_op:
0248         if (user && !access_ok(addr, 2))
0249             goto sigbus;
0250
0251         if (IS_ENABLED(CONFIG_EVA) && user)
0252             LoadHWE(addr, value, res);
0253         else
0254             LoadHW(addr, value, res);
0255
0256         if (res)
0257             goto fault;
0258         compute_return_epc(regs);
0259         regs->regs[insn.i_format.rt] = value;
0260         break;
0261
0262     case lw_op:
0263         if (user && !access_ok(addr, 4))
0264             goto sigbus;
0265
0266         if (IS_ENABLED(CONFIG_EVA) && user)
0267             LoadWE(addr, value, res);
0268         else
0269             LoadW(addr, value, res);
0270
0271         if (res)
0272             goto fault;
0273         compute_return_epc(regs);
0274         regs->regs[insn.i_format.rt] = value;
0275         break;
0276
0277     case lhu_op:
0278         if (user && !access_ok(addr, 2))
0279             goto sigbus;
0280
0281         if (IS_ENABLED(CONFIG_EVA) && user)
0282             LoadHWUE(addr, value, res);
0283         else
0284             LoadHWU(addr, value, res);
0285
0286         if (res)
0287             goto fault;
0288         compute_return_epc(regs);
0289         regs->regs[insn.i_format.rt] = value;
0290         break;
0291
0292     case lwu_op:
0293 #ifdef CONFIG_64BIT
0294         /*
0295          * A 32-bit kernel might be running on a 64-bit processor.  But
0296          * if we're on a 32-bit processor and an i-cache incoherency
0297          * or race makes us see a 64-bit instruction here the sdl/sdr
0298          * would blow up, so for now we don't handle unaligned 64-bit
0299          * instructions on 32-bit kernels.
0300          */
0301         if (user && !access_ok(addr, 4))
0302             goto sigbus;
0303
0304         LoadWU(addr, value, res);
0305         if (res)
0306             goto fault;
0307         compute_return_epc(regs);
0308         regs->regs[insn.i_format.rt] = value;
0309         break;
0310 #endif /* CONFIG_64BIT */
0311
0312         /* Cannot handle 64-bit instructions in 32-bit kernel */
0313         goto sigill;
0314
0315     case ld_op:
0316 #ifdef CONFIG_64BIT
0317         /*
0318          * A 32-bit kernel might be running on a 64-bit processor.  But
0319          * if we're on a 32-bit processor and an i-cache incoherency
0320          * or race makes us see a 64-bit instruction here the sdl/sdr
0321          * would blow up, so for now we don't handle unaligned 64-bit
0322          * instructions on 32-bit kernels.
0323          */
0324         if (user && !access_ok(addr, 8))
0325             goto sigbus;
0326
0327         LoadDW(addr, value, res);
0328         if (res)
0329             goto fault;
0330         compute_return_epc(regs);
0331         regs->regs[insn.i_format.rt] = value;
0332         break;
0333 #endif /* CONFIG_64BIT */
0334
0335         /* Cannot handle 64-bit instructions in 32-bit kernel */
0336         goto sigill;
0337
0338     case sh_op:
0339         if (user && !access_ok(addr, 2))
0340             goto sigbus;
0341
0342         compute_return_epc(regs);
0343         value = regs->regs[insn.i_format.rt];
0344
0345         if (IS_ENABLED(CONFIG_EVA) && user)
0346             StoreHWE(addr, value, res);
0347         else
0348             StoreHW(addr, value, res);
0349
0350         if (res)
0351             goto fault;
0352         break;
0353
0354     case sw_op:
0355         if (user && !access_ok(addr, 4))
0356             goto sigbus;
0357
0358         compute_return_epc(regs);
0359         value = regs->regs[insn.i_format.rt];
0360
0361         if (IS_ENABLED(CONFIG_EVA) && user)
0362             StoreWE(addr, value, res);
0363         else
0364             StoreW(addr, value, res);
0365
0366         if (res)
0367             goto fault;
0368         break;
0369
0370     case sd_op:
0371 #ifdef CONFIG_64BIT
0372         /*
0373          * A 32-bit kernel might be running on a 64-bit processor.  But
0374          * if we're on a 32-bit processor and an i-cache incoherency
0375          * or race makes us see a 64-bit instruction here the sdl/sdr
0376          * would blow up, so for now we don't handle unaligned 64-bit
0377          * instructions on 32-bit kernels.
0378          */
0379         if (user && !access_ok(addr, 8))
0380             goto sigbus;
0381
0382         compute_return_epc(regs);
0383         value = regs->regs[insn.i_format.rt];
0384         StoreDW(addr, value, res);
0385         if (res)
0386             goto fault;
0387         break;
0388 #endif /* CONFIG_64BIT */
0389
0390         /* Cannot handle 64-bit instructions in 32-bit kernel */
0391         goto sigill;
0392
0393 #ifdef CONFIG_MIPS_FP_SUPPORT
0394
0395     case lwc1_op:
0396     case ldc1_op:
0397     case swc1_op:
0398     case sdc1_op:
0399     case cop1x_op: {
0400         void __user *fault_addr = NULL;
0401
0402         die_if_kernel("Unaligned FP access in kernel code", regs);
0403         BUG_ON(!used_math());
0404
0405         res = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 1,
0406                            &fault_addr);
0407         own_fpu(1); /* Restore FPU state. */
0408
0409         /* Signal if something went wrong. */
0410         process_fpemu_return(res, fault_addr, 0);
0411
0412         if (res == 0)
0413             break;
0414         return;
0415     }
0416 #endif /* CONFIG_MIPS_FP_SUPPORT */
0417
0418 #ifdef CONFIG_CPU_HAS_MSA
0419
0420     case msa_op: {
0421         unsigned int wd, preempted;
0422         enum msa_2b_fmt df;
0423         union fpureg *fpr;
0424
0425         if (!cpu_has_msa)
0426             goto sigill;
0427
0428         /*
0429          * If we've reached this point then userland should have taken
0430          * the MSA disabled exception & initialised vector context at
0431          * some point in the past.
0432          */
0433         BUG_ON(!thread_msa_context_live());
0434
0435         df = insn.msa_mi10_format.df;
0436         wd = insn.msa_mi10_format.wd;
0437         fpr = &current->thread.fpu.fpr[wd];
0438
0439         switch (insn.msa_mi10_format.func) {
0440         case msa_ld_op:
0441             if (!access_ok(addr, sizeof(*fpr)))
0442                 goto sigbus;
0443
0444             do {
0445                 /*
0446                  * If we have live MSA context keep track of
0447                  * whether we get preempted in order to avoid
0448                  * the register context we load being clobbered
0449                  * by the live context as it's saved during
0450                  * preemption. If we don't have live context
0451                  * then it can't be saved to clobber the value
0452                  * we load.
0453                  */
0454                 preempted = test_thread_flag(TIF_USEDMSA);
0455
0456                 res = __copy_from_user_inatomic(fpr, addr,
0457                                 sizeof(*fpr));
0458                 if (res)
0459                     goto fault;
0460
0461                 /*
0462                  * Update the hardware register if it is in use
0463                  * by the task in this quantum, in order to
0464                  * avoid having to save & restore the whole
0465                  * vector context.
0466                  */
0467                 preempt_disable();
0468                 if (test_thread_flag(TIF_USEDMSA)) {
0469                     write_msa_wr(wd, fpr, df);
0470                     preempted = 0;
0471                 }
0472                 preempt_enable();
0473             } while (preempted);
0474             break;
0475
0476         case msa_st_op:
0477             if (!access_ok(addr, sizeof(*fpr)))
0478                 goto sigbus;
0479
0480             /*
0481              * Update from the hardware register if it is in use by
0482              * the task in this quantum, in order to avoid having to
0483              * save & restore the whole vector context.
0484              */
0485             preempt_disable();
0486             if (test_thread_flag(TIF_USEDMSA))
0487                 read_msa_wr(wd, fpr, df);
0488             preempt_enable();
0489
0490             res = __copy_to_user_inatomic(addr, fpr, sizeof(*fpr));
0491             if (res)
0492                 goto fault;
0493             break;
0494
0495         default:
0496             goto sigbus;
0497         }
0498
0499         compute_return_epc(regs);
0500         break;
0501     }
0502 #endif /* CONFIG_CPU_HAS_MSA */
0503
0504 #ifndef CONFIG_CPU_MIPSR6
0505     /*
0506      * COP2 is available to implementor for application specific use.
0507      * It's up to applications to register a notifier chain and do
0508      * whatever they have to do, including possible sending of signals.
0509      *
0510      * This instruction has been reallocated in Release 6
0511      */
0512     case lwc2_op:
0513         cu2_notifier_call_chain(CU2_LWC2_OP, regs);
0514         break;
0515
0516     case ldc2_op:
0517         cu2_notifier_call_chain(CU2_LDC2_OP, regs);
0518         break;
0519
0520     case swc2_op:
0521         cu2_notifier_call_chain(CU2_SWC2_OP, regs);
0522         break;
0523
0524     case sdc2_op:
0525         cu2_notifier_call_chain(CU2_SDC2_OP, regs);
0526         break;
0527 #endif
0528     default:
0529         /*
0530          * Pheeee...  We encountered an yet unknown instruction or
0531          * cache coherence problem.  Die sucker, die ...
0532          */
0533         goto sigill;
0534     }
0535
0536 #ifdef CONFIG_DEBUG_FS
0537     unaligned_instructions++;
0538 #endif
0539
0540     return;
0541
0542 fault:
0543     /* roll back jump/branch */
0544     regs->cp0_epc = origpc;
0545     regs->regs[31] = orig31;
0546     /* Did we have an exception handler installed? */
0547     if (fixup_exception(regs))
0548         return;
0549
0550     die_if_kernel("Unhandled kernel unaligned access", regs);
0551     force_sig(SIGSEGV);
0552
0553     return;
0554
0555 sigbus:
0556     die_if_kernel("Unhandled kernel unaligned access", regs);
0557     force_sig(SIGBUS);
0558
0559     return;
0560
0561 sigill:
0562     die_if_kernel
0563         ("Unhandled kernel unaligned access or invalid instruction", regs);
0564     force_sig(SIGILL);
0565 }
0566
0567 /* Recode table from 16-bit register notation to 32-bit GPR. */
0568 const int reg16to32[] = { 16, 17, 2, 3, 4, 5, 6, 7 };
0569
0570 /* Recode table from 16-bit STORE register notation to 32-bit GPR. */
0571 static const int reg16to32st[] = { 0, 17, 2, 3, 4, 5, 6, 7 };
0572
0573 static void emulate_load_store_microMIPS(struct pt_regs *regs,
0574                      void __user *addr)
0575 {
0576     unsigned long value;
0577     unsigned int res;
0578     int i;
0579     unsigned int reg = 0, rvar;
0580     unsigned long orig31;
0581     u16 __user *pc16;
0582     u16 halfword;
0583     unsigned int word;
0584     unsigned long origpc, contpc;
0585     union mips_instruction insn;
0586     struct mm_decoded_insn mminsn;
0587     bool user = user_mode(regs);
0588
0589     origpc = regs->cp0_epc;
0590     orig31 = regs->regs[31];
0591
0592     mminsn.micro_mips_mode = 1;
0593
0594     /*
0595      * This load never faults.
0596      */
0597     pc16 = (unsigned short __user *)msk_isa16_mode(regs->cp0_epc);
0598     __get_user(halfword, pc16);
0599     pc16++;
0600     contpc = regs->cp0_epc + 2;
0601     word = ((unsigned int)halfword << 16);
0602     mminsn.pc_inc = 2;
0603
0604     if (!mm_insn_16bit(halfword)) {
0605         __get_user(halfword, pc16);
0606         pc16++;
0607         contpc = regs->cp0_epc + 4;
0608         mminsn.pc_inc = 4;
0609         word |= halfword;
0610     }
0611     mminsn.insn = word;
0612
0613     if (get_user(halfword, pc16))
0614         goto fault;
0615     mminsn.next_pc_inc = 2;
0616     word = ((unsigned int)halfword << 16);
0617
0618     if (!mm_insn_16bit(halfword)) {
0619         pc16++;
0620         if (get_user(halfword, pc16))
0621             goto fault;
0622         mminsn.next_pc_inc = 4;
0623         word |= halfword;
0624     }
0625     mminsn.next_insn = word;
0626
0627     insn = (union mips_instruction)(mminsn.insn);
0628     if (mm_isBranchInstr(regs, mminsn, &contpc))
0629         insn = (union mips_instruction)(mminsn.next_insn);
0630
0631     /*  Parse instruction to find what to do */
0632
0633     switch (insn.mm_i_format.opcode) {
0634
0635     case mm_pool32a_op:
0636         switch (insn.mm_x_format.func) {
0637         case mm_lwxs_op:
0638             reg = insn.mm_x_format.rd;
0639             goto loadW;
0640         }
0641
0642         goto sigbus;
0643
0644     case mm_pool32b_op:
0645         switch (insn.mm_m_format.func) {
0646         case mm_lwp_func:
0647             reg = insn.mm_m_format.rd;
0648             if (reg == 31)
0649                 goto sigbus;
0650
0651             if (user && !access_ok(addr, 8))
0652                 goto sigbus;
0653
0654             LoadW(addr, value, res);
0655             if (res)
0656                 goto fault;
0657             regs->regs[reg] = value;
0658             addr += 4;
0659             LoadW(addr, value, res);
0660             if (res)
0661                 goto fault;
0662             regs->regs[reg + 1] = value;
0663             goto success;
0664
0665         case mm_swp_func:
0666             reg = insn.mm_m_format.rd;
0667             if (reg == 31)
0668                 goto sigbus;
0669
0670             if (user && !access_ok(addr, 8))
0671                 goto sigbus;
0672
0673             value = regs->regs[reg];
0674             StoreW(addr, value, res);
0675             if (res)
0676                 goto fault;
0677             addr += 4;
0678             value = regs->regs[reg + 1];
0679             StoreW(addr, value, res);
0680             if (res)
0681                 goto fault;
0682             goto success;
0683
0684         case mm_ldp_func:
0685 #ifdef CONFIG_64BIT
0686             reg = insn.mm_m_format.rd;
0687             if (reg == 31)
0688                 goto sigbus;
0689
0690             if (user && !access_ok(addr, 16))
0691                 goto sigbus;
0692
0693             LoadDW(addr, value, res);
0694             if (res)
0695                 goto fault;
0696             regs->regs[reg] = value;
0697             addr += 8;
0698             LoadDW(addr, value, res);
0699             if (res)
0700                 goto fault;
0701             regs->regs[reg + 1] = value;
0702             goto success;
0703 #endif /* CONFIG_64BIT */
0704
0705             goto sigill;
0706
0707         case mm_sdp_func:
0708 #ifdef CONFIG_64BIT
0709             reg = insn.mm_m_format.rd;
0710             if (reg == 31)
0711                 goto sigbus;
0712
0713             if (user && !access_ok(addr, 16))
0714                 goto sigbus;
0715
0716             value = regs->regs[reg];
0717             StoreDW(addr, value, res);
0718             if (res)
0719                 goto fault;
0720             addr += 8;
0721             value = regs->regs[reg + 1];
0722             StoreDW(addr, value, res);
0723             if (res)
0724                 goto fault;
0725             goto success;
0726 #endif /* CONFIG_64BIT */
0727
0728             goto sigill;
0729
0730         case mm_lwm32_func:
0731             reg = insn.mm_m_format.rd;
0732             rvar = reg & 0xf;
0733             if ((rvar > 9) || !reg)
0734                 goto sigill;
0735             if (reg & 0x10) {
0736                 if (user && !access_ok(addr, 4 * (rvar + 1)))
0737                     goto sigbus;
0738             } else {
0739                 if (user && !access_ok(addr, 4 * rvar))
0740                     goto sigbus;
0741             }
0742             if (rvar == 9)
0743                 rvar = 8;
0744             for (i = 16; rvar; rvar--, i++) {
0745                 LoadW(addr, value, res);
0746                 if (res)
0747                     goto fault;
0748                 addr += 4;
0749                 regs->regs[i] = value;
0750             }
0751             if ((reg & 0xf) == 9) {
0752                 LoadW(addr, value, res);
0753                 if (res)
0754                     goto fault;
0755                 addr += 4;
0756                 regs->regs[30] = value;
0757             }
0758             if (reg & 0x10) {
0759                 LoadW(addr, value, res);
0760                 if (res)
0761                     goto fault;
0762                 regs->regs[31] = value;
0763             }
0764             goto success;
0765
0766         case mm_swm32_func:
0767             reg = insn.mm_m_format.rd;
0768             rvar = reg & 0xf;
0769             if ((rvar > 9) || !reg)
0770                 goto sigill;
0771             if (reg & 0x10) {
0772                 if (user && !access_ok(addr, 4 * (rvar + 1)))
0773                     goto sigbus;
0774             } else {
0775                 if (user && !access_ok(addr, 4 * rvar))
0776                     goto sigbus;
0777             }
0778             if (rvar == 9)
0779                 rvar = 8;
0780             for (i = 16; rvar; rvar--, i++) {
0781                 value = regs->regs[i];
0782                 StoreW(addr, value, res);
0783                 if (res)
0784                     goto fault;
0785                 addr += 4;
0786             }
0787             if ((reg & 0xf) == 9) {
0788                 value = regs->regs[30];
0789                 StoreW(addr, value, res);
0790                 if (res)
0791                     goto fault;
0792                 addr += 4;
0793             }
0794             if (reg & 0x10) {
0795                 value = regs->regs[31];
0796                 StoreW(addr, value, res);
0797                 if (res)
0798                     goto fault;
0799             }
0800             goto success;
0801
0802         case mm_ldm_func:
0803 #ifdef CONFIG_64BIT
0804             reg = insn.mm_m_format.rd;
0805             rvar = reg & 0xf;
0806             if ((rvar > 9) || !reg)
0807                 goto sigill;
0808             if (reg & 0x10) {
0809                 if (user && !access_ok(addr, 8 * (rvar + 1)))
0810                     goto sigbus;
0811             } else {
0812                 if (user && !access_ok(addr, 8 * rvar))
0813                     goto sigbus;
0814             }
0815             if (rvar == 9)
0816                 rvar = 8;
0817
0818             for (i = 16; rvar; rvar--, i++) {
0819                 LoadDW(addr, value, res);
0820                 if (res)
0821                     goto fault;
0822                 addr += 4;
0823                 regs->regs[i] = value;
0824             }
0825             if ((reg & 0xf) == 9) {
0826                 LoadDW(addr, value, res);
0827                 if (res)
0828                     goto fault;
0829                 addr += 8;
0830                 regs->regs[30] = value;
0831             }
0832             if (reg & 0x10) {
0833                 LoadDW(addr, value, res);
0834                 if (res)
0835                     goto fault;
0836                 regs->regs[31] = value;
0837             }
0838             goto success;
0839 #endif /* CONFIG_64BIT */
0840
0841             goto sigill;
0842
0843         case mm_sdm_func:
0844 #ifdef CONFIG_64BIT
0845             reg = insn.mm_m_format.rd;
0846             rvar = reg & 0xf;
0847             if ((rvar > 9) || !reg)
0848                 goto sigill;
0849             if (reg & 0x10) {
0850                 if (user && !access_ok(addr, 8 * (rvar + 1)))
0851                     goto sigbus;
0852             } else {
0853                 if (user && !access_ok(addr, 8 * rvar))
0854                     goto sigbus;
0855             }
0856             if (rvar == 9)
0857                 rvar = 8;
0858
0859             for (i = 16; rvar; rvar--, i++) {
0860                 value = regs->regs[i];
0861                 StoreDW(addr, value, res);
0862                 if (res)
0863                     goto fault;
0864                 addr += 8;
0865             }
0866             if ((reg & 0xf) == 9) {
0867                 value = regs->regs[30];
0868                 StoreDW(addr, value, res);
0869                 if (res)
0870                     goto fault;
0871                 addr += 8;
0872             }
0873             if (reg & 0x10) {
0874                 value = regs->regs[31];
0875                 StoreDW(addr, value, res);
0876                 if (res)
0877                     goto fault;
0878             }
0879             goto success;
0880 #endif /* CONFIG_64BIT */
0881
0882             goto sigill;
0883
0884             /*  LWC2, SWC2, LDC2, SDC2 are not serviced */
0885         }
0886
0887         goto sigbus;
0888
0889     case mm_pool32c_op:
0890         switch (insn.mm_m_format.func) {
0891         case mm_lwu_func:
0892             reg = insn.mm_m_format.rd;
0893             goto loadWU;
0894         }
0895
0896         /*  LL,SC,LLD,SCD are not serviced */
0897         goto sigbus;
0898
0899 #ifdef CONFIG_MIPS_FP_SUPPORT
0900     case mm_pool32f_op:
0901         switch (insn.mm_x_format.func) {
0902         case mm_lwxc1_func:
0903         case mm_swxc1_func:
0904         case mm_ldxc1_func:
0905         case mm_sdxc1_func:
0906             goto fpu_emul;
0907         }
0908
0909         goto sigbus;
0910
0911     case mm_ldc132_op:
0912     case mm_sdc132_op:
0913     case mm_lwc132_op:
0914     case mm_swc132_op: {
0915         void __user *fault_addr = NULL;
0916
0917 fpu_emul:
0918         /* roll back jump/branch */
0919         regs->cp0_epc = origpc;
0920         regs->regs[31] = orig31;
0921
0922         die_if_kernel("Unaligned FP access in kernel code", regs);
0923         BUG_ON(!used_math());
0924         BUG_ON(!is_fpu_owner());
0925
0926         res = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 1,
0927                            &fault_addr);
0928         own_fpu(1); /* restore FPU state */
0929
0930         /* If something went wrong, signal */
0931         process_fpemu_return(res, fault_addr, 0);
0932
0933         if (res == 0)
0934             goto success;
0935         return;
0936     }
0937 #endif /* CONFIG_MIPS_FP_SUPPORT */
0938
0939     case mm_lh32_op:
0940         reg = insn.mm_i_format.rt;
0941         goto loadHW;
0942
0943     case mm_lhu32_op:
0944         reg = insn.mm_i_format.rt;
0945         goto loadHWU;
0946
0947     case mm_lw32_op:
0948         reg = insn.mm_i_format.rt;
0949         goto loadW;
0950
0951     case mm_sh32_op:
0952         reg = insn.mm_i_format.rt;
0953         goto storeHW;
0954
0955     case mm_sw32_op:
0956         reg = insn.mm_i_format.rt;
0957         goto storeW;
0958
0959     case mm_ld32_op:
0960         reg = insn.mm_i_format.rt;
0961         goto loadDW;
0962
0963     case mm_sd32_op:
0964         reg = insn.mm_i_format.rt;
0965         goto storeDW;
0966
0967     case mm_pool16c_op:
0968         switch (insn.mm16_m_format.func) {
0969         case mm_lwm16_op:
0970             reg = insn.mm16_m_format.rlist;
0971             rvar = reg + 1;
0972             if (user && !access_ok(addr, 4 * rvar))
0973                 goto sigbus;
0974
0975             for (i = 16; rvar; rvar--, i++) {
0976                 LoadW(addr, value, res);
0977                 if (res)
0978                     goto fault;
0979                 addr += 4;
0980                 regs->regs[i] = value;
0981             }
0982             LoadW(addr, value, res);
0983             if (res)
0984                 goto fault;
0985             regs->regs[31] = value;
0986
0987             goto success;
0988
0989         case mm_swm16_op:
0990             reg = insn.mm16_m_format.rlist;
0991             rvar = reg + 1;
0992             if (user && !access_ok(addr, 4 * rvar))
0993                 goto sigbus;
0994
0995             for (i = 16; rvar; rvar--, i++) {
0996                 value = regs->regs[i];
0997                 StoreW(addr, value, res);
0998                 if (res)
0999                     goto fault;
1000                 addr += 4;
1001             }
1002             value = regs->regs[31];
1003             StoreW(addr, value, res);
1004             if (res)
1005                 goto fault;
1006
1007             goto success;
1008
1009         }
1010
1011         goto sigbus;
1012
1013     case mm_lhu16_op:
1014         reg = reg16to32[insn.mm16_rb_format.rt];
1015         goto loadHWU;
1016
1017     case mm_lw16_op:
1018         reg = reg16to32[insn.mm16_rb_format.rt];
1019         goto loadW;
1020
1021     case mm_sh16_op:
1022         reg = reg16to32st[insn.mm16_rb_format.rt];
1023         goto storeHW;
1024
1025     case mm_sw16_op:
1026         reg = reg16to32st[insn.mm16_rb_format.rt];
1027         goto storeW;
1028
1029     case mm_lwsp16_op:
1030         reg = insn.mm16_r5_format.rt;
1031         goto loadW;
1032
1033     case mm_swsp16_op:
1034         reg = insn.mm16_r5_format.rt;
1035         goto storeW;
1036
1037     case mm_lwgp16_op:
1038         reg = reg16to32[insn.mm16_r3_format.rt];
1039         goto loadW;
1040
1041     default:
1042         goto sigill;
1043     }
1044
1045 loadHW:
1046     if (user && !access_ok(addr, 2))
1047         goto sigbus;
1048
1049     LoadHW(addr, value, res);
1050     if (res)
1051         goto fault;
1052     regs->regs[reg] = value;
1053     goto success;
1054
1055 loadHWU:
1056     if (user && !access_ok(addr, 2))
1057         goto sigbus;
1058
1059     LoadHWU(addr, value, res);
1060     if (res)
1061         goto fault;
1062     regs->regs[reg] = value;
1063     goto success;
1064
1065 loadW:
1066     if (user && !access_ok(addr, 4))
1067         goto sigbus;
1068
1069     LoadW(addr, value, res);
1070     if (res)
1071         goto fault;
1072     regs->regs[reg] = value;
1073     goto success;
1074
1075 loadWU:
1076 #ifdef CONFIG_64BIT
1077     /*
1078      * A 32-bit kernel might be running on a 64-bit processor.  But
1079      * if we're on a 32-bit processor and an i-cache incoherency
1080      * or race makes us see a 64-bit instruction here the sdl/sdr
1081      * would blow up, so for now we don't handle unaligned 64-bit
1082      * instructions on 32-bit kernels.
1083      */
1084     if (user && !access_ok(addr, 4))
1085         goto sigbus;
1086
1087     LoadWU(addr, value, res);
1088     if (res)
1089         goto fault;
1090     regs->regs[reg] = value;
1091     goto success;
1092 #endif /* CONFIG_64BIT */
1093
1094     /* Cannot handle 64-bit instructions in 32-bit kernel */
1095     goto sigill;
1096
1097 loadDW:
1098 #ifdef CONFIG_64BIT
1099     /*
1100      * A 32-bit kernel might be running on a 64-bit processor.  But
1101      * if we're on a 32-bit processor and an i-cache incoherency
1102      * or race makes us see a 64-bit instruction here the sdl/sdr
1103      * would blow up, so for now we don't handle unaligned 64-bit
1104      * instructions on 32-bit kernels.
1105      */
1106     if (user && !access_ok(addr, 8))
1107         goto sigbus;
1108
1109     LoadDW(addr, value, res);
1110     if (res)
1111         goto fault;
1112     regs->regs[reg] = value;
1113     goto success;
1114 #endif /* CONFIG_64BIT */
1115
1116     /* Cannot handle 64-bit instructions in 32-bit kernel */
1117     goto sigill;
1118
1119 storeHW:
1120     if (user && !access_ok(addr, 2))
1121         goto sigbus;
1122
1123     value = regs->regs[reg];
1124     StoreHW(addr, value, res);
1125     if (res)
1126         goto fault;
1127     goto success;
1128
1129 storeW:
1130     if (user && !access_ok(addr, 4))
1131         goto sigbus;
1132
1133     value = regs->regs[reg];
1134     StoreW(addr, value, res);
1135     if (res)
1136         goto fault;
1137     goto success;
1138
1139 storeDW:
1140 #ifdef CONFIG_64BIT
1141     /*
1142      * A 32-bit kernel might be running on a 64-bit processor.  But
1143      * if we're on a 32-bit processor and an i-cache incoherency
1144      * or race makes us see a 64-bit instruction here the sdl/sdr
1145      * would blow up, so for now we don't handle unaligned 64-bit
1146      * instructions on 32-bit kernels.
1147      */
1148     if (user && !access_ok(addr, 8))
1149         goto sigbus;
1150
1151     value = regs->regs[reg];
1152     StoreDW(addr, value, res);
1153     if (res)
1154         goto fault;
1155     goto success;
1156 #endif /* CONFIG_64BIT */
1157
1158     /* Cannot handle 64-bit instructions in 32-bit kernel */
1159     goto sigill;
1160
1161 success:
1162     regs->cp0_epc = contpc; /* advance or branch */
1163
1164 #ifdef CONFIG_DEBUG_FS
1165     unaligned_instructions++;
1166 #endif
1167     return;
1168
1169 fault:
1170     /* roll back jump/branch */
1171     regs->cp0_epc = origpc;
1172     regs->regs[31] = orig31;
1173     /* Did we have an exception handler installed? */
1174     if (fixup_exception(regs))
1175         return;
1176
1177     die_if_kernel("Unhandled kernel unaligned access", regs);
1178     force_sig(SIGSEGV);
1179
1180     return;
1181
1182 sigbus:
1183     die_if_kernel("Unhandled kernel unaligned access", regs);
1184     force_sig(SIGBUS);
1185
1186     return;
1187
1188 sigill:
1189     die_if_kernel
1190         ("Unhandled kernel unaligned access or invalid instruction", regs);
1191     force_sig(SIGILL);
1192 }
1193
1194 static void emulate_load_store_MIPS16e(struct pt_regs *regs, void __user * addr)
1195 {
1196     unsigned long value;
1197     unsigned int res;
1198     int reg;
1199     unsigned long orig31;
1200     u16 __user *pc16;
1201     unsigned long origpc;
1202     union mips16e_instruction mips16inst, oldinst;
1203     unsigned int opcode;
1204     int extended = 0;
1205     bool user = user_mode(regs);
1206
1207     origpc = regs->cp0_epc;
1208     orig31 = regs->regs[31];
1209     pc16 = (unsigned short __user *)msk_isa16_mode(origpc);
1210     /*
1211      * This load never faults.
1212      */
1213     __get_user(mips16inst.full, pc16);
1214     oldinst = mips16inst;
1215
1216     /* skip EXTEND instruction */
1217     if (mips16inst.ri.opcode == MIPS16e_extend_op) {
1218         extended = 1;
1219         pc16++;
1220         __get_user(mips16inst.full, pc16);
1221     } else if (delay_slot(regs)) {
1222         /*  skip jump instructions */
1223         /*  JAL/JALX are 32 bits but have OPCODE in first short int */
1224         if (mips16inst.ri.opcode == MIPS16e_jal_op)
1225             pc16++;
1226         pc16++;
1227         if (get_user(mips16inst.full, pc16))
1228             goto sigbus;
1229     }
1230
1231     opcode = mips16inst.ri.opcode;
1232     switch (opcode) {
1233     case MIPS16e_i64_op:    /* I64 or RI64 instruction */
1234         switch (mips16inst.i64.func) {  /* I64/RI64 func field check */
1235         case MIPS16e_ldpc_func:
1236         case MIPS16e_ldsp_func:
1237             reg = reg16to32[mips16inst.ri64.ry];
1238             goto loadDW;
1239
1240         case MIPS16e_sdsp_func:
1241             reg = reg16to32[mips16inst.ri64.ry];
1242             goto writeDW;
1243
1244         case MIPS16e_sdrasp_func:
1245             reg = 29;   /* GPRSP */
1246             goto writeDW;
1247         }
1248
1249         goto sigbus;
1250
1251     case MIPS16e_swsp_op:
1252         reg = reg16to32[mips16inst.ri.rx];
1253         if (extended && cpu_has_mips16e2)
1254             switch (mips16inst.ri.imm >> 5) {
1255             case 0:     /* SWSP */
1256             case 1:     /* SWGP */
1257                 break;
1258             case 2:     /* SHGP */
1259                 opcode = MIPS16e_sh_op;
1260                 break;
1261             default:
1262                 goto sigbus;
1263             }
1264         break;
1265
1266     case MIPS16e_lwpc_op:
1267         reg = reg16to32[mips16inst.ri.rx];
1268         break;
1269
1270     case MIPS16e_lwsp_op:
1271         reg = reg16to32[mips16inst.ri.rx];
1272         if (extended && cpu_has_mips16e2)
1273             switch (mips16inst.ri.imm >> 5) {
1274             case 0:     /* LWSP */
1275             case 1:     /* LWGP */
1276                 break;
1277             case 2:     /* LHGP */
1278                 opcode = MIPS16e_lh_op;
1279                 break;
1280             case 4:     /* LHUGP */
1281                 opcode = MIPS16e_lhu_op;
1282                 break;
1283             default:
1284                 goto sigbus;
1285             }
1286         break;
1287
1288     case MIPS16e_i8_op:
1289         if (mips16inst.i8.func != MIPS16e_swrasp_func)
1290             goto sigbus;
1291         reg = 29;   /* GPRSP */
1292         break;
1293
1294     default:
1295         reg = reg16to32[mips16inst.rri.ry];
1296         break;
1297     }
1298
1299     switch (opcode) {
1300
1301     case MIPS16e_lb_op:
1302     case MIPS16e_lbu_op:
1303     case MIPS16e_sb_op:
1304         goto sigbus;
1305
1306     case MIPS16e_lh_op:
1307         if (user && !access_ok(addr, 2))
1308             goto sigbus;
1309
1310         LoadHW(addr, value, res);
1311         if (res)
1312             goto fault;
1313         MIPS16e_compute_return_epc(regs, &oldinst);
1314         regs->regs[reg] = value;
1315         break;
1316
1317     case MIPS16e_lhu_op:
1318         if (user && !access_ok(addr, 2))
1319             goto sigbus;
1320
1321         LoadHWU(addr, value, res);
1322         if (res)
1323             goto fault;
1324         MIPS16e_compute_return_epc(regs, &oldinst);
1325         regs->regs[reg] = value;
1326         break;
1327
1328     case MIPS16e_lw_op:
1329     case MIPS16e_lwpc_op:
1330     case MIPS16e_lwsp_op:
1331         if (user && !access_ok(addr, 4))
1332             goto sigbus;
1333
1334         LoadW(addr, value, res);
1335         if (res)
1336             goto fault;
1337         MIPS16e_compute_return_epc(regs, &oldinst);
1338         regs->regs[reg] = value;
1339         break;
1340
1341     case MIPS16e_lwu_op:
1342 #ifdef CONFIG_64BIT
1343         /*
1344          * A 32-bit kernel might be running on a 64-bit processor.  But
1345          * if we're on a 32-bit processor and an i-cache incoherency
1346          * or race makes us see a 64-bit instruction here the sdl/sdr
1347          * would blow up, so for now we don't handle unaligned 64-bit
1348          * instructions on 32-bit kernels.
1349          */
1350         if (user && !access_ok(addr, 4))
1351             goto sigbus;
1352
1353         LoadWU(addr, value, res);
1354         if (res)
1355             goto fault;
1356         MIPS16e_compute_return_epc(regs, &oldinst);
1357         regs->regs[reg] = value;
1358         break;
1359 #endif /* CONFIG_64BIT */
1360
1361         /* Cannot handle 64-bit instructions in 32-bit kernel */
1362         goto sigill;
1363
1364     case MIPS16e_ld_op:
1365 loadDW:
1366 #ifdef CONFIG_64BIT
1367         /*
1368          * A 32-bit kernel might be running on a 64-bit processor.  But
1369          * if we're on a 32-bit processor and an i-cache incoherency
1370          * or race makes us see a 64-bit instruction here the sdl/sdr
1371          * would blow up, so for now we don't handle unaligned 64-bit
1372          * instructions on 32-bit kernels.
1373          */
1374         if (user && !access_ok(addr, 8))
1375             goto sigbus;
1376
1377         LoadDW(addr, value, res);
1378         if (res)
1379             goto fault;
1380         MIPS16e_compute_return_epc(regs, &oldinst);
1381         regs->regs[reg] = value;
1382         break;
1383 #endif /* CONFIG_64BIT */
1384
1385         /* Cannot handle 64-bit instructions in 32-bit kernel */
1386         goto sigill;
1387
1388     case MIPS16e_sh_op:
1389         if (user && !access_ok(addr, 2))
1390             goto sigbus;
1391
1392         MIPS16e_compute_return_epc(regs, &oldinst);
1393         value = regs->regs[reg];
1394         StoreHW(addr, value, res);
1395         if (res)
1396             goto fault;
1397         break;
1398
1399     case MIPS16e_sw_op:
1400     case MIPS16e_swsp_op:
1401     case MIPS16e_i8_op: /* actually - MIPS16e_swrasp_func */
1402         if (user && !access_ok(addr, 4))
1403             goto sigbus;
1404
1405         MIPS16e_compute_return_epc(regs, &oldinst);
1406         value = regs->regs[reg];
1407         StoreW(addr, value, res);
1408         if (res)
1409             goto fault;
1410         break;
1411
1412     case MIPS16e_sd_op:
1413 writeDW:
1414 #ifdef CONFIG_64BIT
1415         /*
1416          * A 32-bit kernel might be running on a 64-bit processor.  But
1417          * if we're on a 32-bit processor and an i-cache incoherency
1418          * or race makes us see a 64-bit instruction here the sdl/sdr
1419          * would blow up, so for now we don't handle unaligned 64-bit
1420          * instructions on 32-bit kernels.
1421          */
1422         if (user && !access_ok(addr, 8))
1423             goto sigbus;
1424
1425         MIPS16e_compute_return_epc(regs, &oldinst);
1426         value = regs->regs[reg];
1427         StoreDW(addr, value, res);
1428         if (res)
1429             goto fault;
1430         break;
1431 #endif /* CONFIG_64BIT */
1432
1433         /* Cannot handle 64-bit instructions in 32-bit kernel */
1434         goto sigill;
1435
1436     default:
1437         /*
1438          * Pheeee...  We encountered an yet unknown instruction or
1439          * cache coherence problem.  Die sucker, die ...
1440          */
1441         goto sigill;
1442     }
1443
1444 #ifdef CONFIG_DEBUG_FS
1445     unaligned_instructions++;
1446 #endif
1447
1448     return;
1449
1450 fault:
1451     /* roll back jump/branch */
1452     regs->cp0_epc = origpc;
1453     regs->regs[31] = orig31;
1454     /* Did we have an exception handler installed? */
1455     if (fixup_exception(regs))
1456         return;
1457
1458     die_if_kernel("Unhandled kernel unaligned access", regs);
1459     force_sig(SIGSEGV);
1460
1461     return;
1462
1463 sigbus:
1464     die_if_kernel("Unhandled kernel unaligned access", regs);
1465     force_sig(SIGBUS);
1466
1467     return;
1468
1469 sigill:
1470     die_if_kernel
1471         ("Unhandled kernel unaligned access or invalid instruction", regs);
1472     force_sig(SIGILL);
1473 }
1474
1475 asmlinkage void do_ade(struct pt_regs *regs)
1476 {
1477     enum ctx_state prev_state;
1478     unsigned int *pc;
1479
1480     prev_state = exception_enter();
1481     perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS,
1482             1, regs, regs->cp0_badvaddr);
1483
1484 #ifdef CONFIG_64BIT
1485     /*
1486      * check, if we are hitting space between CPU implemented maximum
1487      * virtual user address and 64bit maximum virtual user address
1488      * and do exception handling to get EFAULTs for get_user/put_user
1489      */
1490     if ((regs->cp0_badvaddr >= (1UL << cpu_vmbits)) &&
1491         (regs->cp0_badvaddr < XKSSEG)) {
1492         if (fixup_exception(regs)) {
1493             current->thread.cp0_baduaddr = regs->cp0_badvaddr;
1494             return;
1495         }
1496         goto sigbus;
1497     }
1498 #endif
1499
1500     /*
1501      * Did we catch a fault trying to load an instruction?
1502      */
1503     if (regs->cp0_badvaddr == regs->cp0_epc)
1504         goto sigbus;
1505
1506     if (user_mode(regs) && !test_thread_flag(TIF_FIXADE))
1507         goto sigbus;
1508     if (unaligned_action == UNALIGNED_ACTION_SIGNAL)
1509         goto sigbus;
1510
1511     /*
1512      * Do branch emulation only if we didn't forward the exception.
1513      * This is all so but ugly ...
1514      */
1515
1516     /*
1517      * Are we running in microMIPS mode?
1518      */
1519     if (get_isa16_mode(regs->cp0_epc)) {
1520         /*
1521          * Did we catch a fault trying to load an instruction in
1522          * 16-bit mode?
1523          */
1524         if (regs->cp0_badvaddr == msk_isa16_mode(regs->cp0_epc))
1525             goto sigbus;
1526         if (unaligned_action == UNALIGNED_ACTION_SHOW)
1527             show_registers(regs);
1528
1529         if (cpu_has_mmips) {
1530             emulate_load_store_microMIPS(regs,
1531                 (void __user *)regs->cp0_badvaddr);
1532             return;
1533         }
1534
1535         if (cpu_has_mips16) {
1536             emulate_load_store_MIPS16e(regs,
1537                 (void __user *)regs->cp0_badvaddr);
1538             return;
1539         }
1540
1541         goto sigbus;
1542     }
1543
1544     if (unaligned_action == UNALIGNED_ACTION_SHOW)
1545         show_registers(regs);
1546     pc = (unsigned int *)exception_epc(regs);
1547
1548     emulate_load_store_insn(regs, (void __user *)regs->cp0_badvaddr, pc);
1549
1550     return;
1551
1552 sigbus:
1553     die_if_kernel("Kernel unaligned instruction access", regs);
1554     force_sig(SIGBUS);
1555
1556     /*
1557      * XXX On return from the signal handler we should advance the epc
1558      */
1559     exception_exit(prev_state);
1560 }
1561
1562 #ifdef CONFIG_DEBUG_FS
1563 static int __init debugfs_unaligned(void)
1564 {
1565     debugfs_create_u32("unaligned_instructions", S_IRUGO, mips_debugfs_dir,
1566                &unaligned_instructions);
1567     debugfs_create_u32("unaligned_action", S_IRUGO | S_IWUSR,
1568                mips_debugfs_dir, &unaligned_action);
1569     return 0;
1570 }
1571 arch_initcall(debugfs_unaligned);
1572 #endif