mips/kernel/smp-cmp.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *
0004  * Copyright (C) 2007 MIPS Technologies, Inc.
0005  *    Chris Dearman (chris@mips.com)
0006  */
0007
0008 #undef DEBUG
0009
0010 #include <linux/kernel.h>
0011 #include <linux/sched/task_stack.h>
0012 #include <linux/smp.h>
0013 #include <linux/cpumask.h>
0014 #include <linux/interrupt.h>
0015 #include <linux/compiler.h>
0016
0017 #include <linux/atomic.h>
0018 #include <asm/cacheflush.h>
0019 #include <asm/cpu.h>
0020 #include <asm/processor.h>
0021 #include <asm/hardirq.h>
0022 #include <asm/mmu_context.h>
0023 #include <asm/smp.h>
0024 #include <asm/time.h>
0025 #include <asm/mipsregs.h>
0026 #include <asm/mipsmtregs.h>
0027 #include <asm/mips_mt.h>
0028 #include <asm/amon.h>
0029
0030 static void cmp_init_secondary(void)
0031 {
0032     struct cpuinfo_mips *c __maybe_unused = &current_cpu_data;
0033
0034     /* Assume GIC is present */
0035     change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 | STATUSF_IP4 |
0036                  STATUSF_IP5 | STATUSF_IP6 | STATUSF_IP7);
0037
0038     /* Enable per-cpu interrupts: platform specific */
0039
0040 #ifdef CONFIG_MIPS_MT_SMP
0041     if (cpu_has_mipsmt)
0042         cpu_set_vpe_id(c, (read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) &
0043                   TCBIND_CURVPE);
0044 #endif
0045 }
0046
0047 static void cmp_smp_finish(void)
0048 {
0049     pr_debug("SMPCMP: CPU%d: %s\n", smp_processor_id(), __func__);
0050
0051     /* CDFIXME: remove this? */
0052     write_c0_compare(read_c0_count() + (8 * mips_hpt_frequency / HZ));
0053
0054 #ifdef CONFIG_MIPS_MT_FPAFF
0055     /* If we have an FPU, enroll ourselves in the FPU-full mask */
0056     if (cpu_has_fpu)
0057         cpumask_set_cpu(smp_processor_id(), &mt_fpu_cpumask);
0058 #endif /* CONFIG_MIPS_MT_FPAFF */
0059
0060     local_irq_enable();
0061 }
0062
0063 /*
0064  * Setup the PC, SP, and GP of a secondary processor and start it running
0065  * smp_bootstrap is the place to resume from
0066  * __KSTK_TOS(idle) is apparently the stack pointer
0067  * (unsigned long)idle->thread_info the gp
0068  */
0069 static int cmp_boot_secondary(int cpu, struct task_struct *idle)
0070 {
0071     struct thread_info *gp = task_thread_info(idle);
0072     unsigned long sp = __KSTK_TOS(idle);
0073     unsigned long pc = (unsigned long)&smp_bootstrap;
0074     unsigned long a0 = 0;
0075
0076     pr_debug("SMPCMP: CPU%d: %s cpu %d\n", smp_processor_id(),
0077         __func__, cpu);
0078
0079 #if 0
0080     /* Needed? */
0081     flush_icache_range((unsigned long)gp,
0082                (unsigned long)(gp + sizeof(struct thread_info)));
0083 #endif
0084
0085     amon_cpu_start(cpu, pc, sp, (unsigned long)gp, a0);
0086     return 0;
0087 }
0088
0089 /*
0090  * Common setup before any secondaries are started
0091  */
0092 void __init cmp_smp_setup(void)
0093 {
0094     int i;
0095     int ncpu = 0;
0096
0097     pr_debug("SMPCMP: CPU%d: %s\n", smp_processor_id(), __func__);
0098
0099 #ifdef CONFIG_MIPS_MT_FPAFF
0100     /* If we have an FPU, enroll ourselves in the FPU-full mask */
0101     if (cpu_has_fpu)
0102         cpumask_set_cpu(0, &mt_fpu_cpumask);
0103 #endif /* CONFIG_MIPS_MT_FPAFF */
0104
0105     for (i = 1; i < NR_CPUS; i++) {
0106         if (amon_cpu_avail(i)) {
0107             set_cpu_possible(i, true);
0108             __cpu_number_map[i] = ++ncpu;
0109             __cpu_logical_map[ncpu] = i;
0110         }
0111     }
0112
0113     if (cpu_has_mipsmt) {
0114         unsigned int nvpe = 1;
0115 #ifdef CONFIG_MIPS_MT_SMP
0116         unsigned int mvpconf0 = read_c0_mvpconf0();
0117
0118         nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
0119 #endif
0120         smp_num_siblings = nvpe;
0121     }
0122     pr_info("Detected %i available secondary CPU(s)\n", ncpu);
0123 }
0124
0125 void __init cmp_prepare_cpus(unsigned int max_cpus)
0126 {
0127     pr_debug("SMPCMP: CPU%d: %s max_cpus=%d\n",
0128          smp_processor_id(), __func__, max_cpus);
0129
0130 #ifdef CONFIG_MIPS_MT
0131     /*
0132      * FIXME: some of these options are per-system, some per-core and
0133      * some per-cpu
0134      */
0135     mips_mt_set_cpuoptions();
0136 #endif
0137
0138 }
0139
0140 const struct plat_smp_ops cmp_smp_ops = {
0141     .send_ipi_single    = mips_smp_send_ipi_single,
0142     .send_ipi_mask      = mips_smp_send_ipi_mask,
0143     .init_secondary     = cmp_init_secondary,
0144     .smp_finish     = cmp_smp_finish,
0145     .boot_secondary     = cmp_boot_secondary,
0146     .smp_setup      = cmp_smp_setup,
0147     .prepare_cpus       = cmp_prepare_cpus,
0148 };