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0001 /*
0002  * This file is subject to the terms and conditions of the GNU General Public
0003  * License.  See the file "COPYING" in the main directory of this archive
0004  * for more details.
0005  *
0006  * Copyright (C) 1992 Ross Biro
0007  * Copyright (C) Linus Torvalds
0008  * Copyright (C) 1994, 95, 96, 97, 98, 2000 Ralf Baechle
0009  * Copyright (C) 1996 David S. Miller
0010  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
0011  * Copyright (C) 1999 MIPS Technologies, Inc.
0012  * Copyright (C) 2000 Ulf Carlsson
0013  *
0014  * At this time Linux/MIPS64 only supports syscall tracing, even for 32-bit
0015  * binaries.
0016  */
0017 #include <linux/compiler.h>
0018 #include <linux/context_tracking.h>
0019 #include <linux/elf.h>
0020 #include <linux/kernel.h>
0021 #include <linux/sched.h>
0022 #include <linux/sched/task_stack.h>
0023 #include <linux/mm.h>
0024 #include <linux/errno.h>
0025 #include <linux/ptrace.h>
0026 #include <linux/regset.h>
0027 #include <linux/smp.h>
0028 #include <linux/security.h>
0029 #include <linux/stddef.h>
0030 #include <linux/audit.h>
0031 #include <linux/seccomp.h>
0032 #include <linux/ftrace.h>
0033 
0034 #include <asm/byteorder.h>
0035 #include <asm/cpu.h>
0036 #include <asm/cpu-info.h>
0037 #include <asm/dsp.h>
0038 #include <asm/fpu.h>
0039 #include <asm/mipsregs.h>
0040 #include <asm/mipsmtregs.h>
0041 #include <asm/page.h>
0042 #include <asm/processor.h>
0043 #include <asm/syscall.h>
0044 #include <linux/uaccess.h>
0045 #include <asm/bootinfo.h>
0046 #include <asm/reg.h>
0047 
0048 #define CREATE_TRACE_POINTS
0049 #include <trace/events/syscalls.h>
0050 
0051 /*
0052  * Called by kernel/ptrace.c when detaching..
0053  *
0054  * Make sure single step bits etc are not set.
0055  */
0056 void ptrace_disable(struct task_struct *child)
0057 {
0058     /* Don't load the watchpoint registers for the ex-child. */
0059     clear_tsk_thread_flag(child, TIF_LOAD_WATCH);
0060 }
0061 
0062 /*
0063  * Read a general register set.  We always use the 64-bit format, even
0064  * for 32-bit kernels and for 32-bit processes on a 64-bit kernel.
0065  * Registers are sign extended to fill the available space.
0066  */
0067 int ptrace_getregs(struct task_struct *child, struct user_pt_regs __user *data)
0068 {
0069     struct pt_regs *regs;
0070     int i;
0071 
0072     if (!access_ok(data, 38 * 8))
0073         return -EIO;
0074 
0075     regs = task_pt_regs(child);
0076 
0077     for (i = 0; i < 32; i++)
0078         __put_user((long)regs->regs[i], (__s64 __user *)&data->regs[i]);
0079     __put_user((long)regs->lo, (__s64 __user *)&data->lo);
0080     __put_user((long)regs->hi, (__s64 __user *)&data->hi);
0081     __put_user((long)regs->cp0_epc, (__s64 __user *)&data->cp0_epc);
0082     __put_user((long)regs->cp0_badvaddr, (__s64 __user *)&data->cp0_badvaddr);
0083     __put_user((long)regs->cp0_status, (__s64 __user *)&data->cp0_status);
0084     __put_user((long)regs->cp0_cause, (__s64 __user *)&data->cp0_cause);
0085 
0086     return 0;
0087 }
0088 
0089 /*
0090  * Write a general register set.  As for PTRACE_GETREGS, we always use
0091  * the 64-bit format.  On a 32-bit kernel only the lower order half
0092  * (according to endianness) will be used.
0093  */
0094 int ptrace_setregs(struct task_struct *child, struct user_pt_regs __user *data)
0095 {
0096     struct pt_regs *regs;
0097     int i;
0098 
0099     if (!access_ok(data, 38 * 8))
0100         return -EIO;
0101 
0102     regs = task_pt_regs(child);
0103 
0104     for (i = 0; i < 32; i++)
0105         __get_user(regs->regs[i], (__s64 __user *)&data->regs[i]);
0106     __get_user(regs->lo, (__s64 __user *)&data->lo);
0107     __get_user(regs->hi, (__s64 __user *)&data->hi);
0108     __get_user(regs->cp0_epc, (__s64 __user *)&data->cp0_epc);
0109 
0110     /* badvaddr, status, and cause may not be written.  */
0111 
0112     /* System call number may have been changed */
0113     mips_syscall_update_nr(child, regs);
0114 
0115     return 0;
0116 }
0117 
0118 int ptrace_get_watch_regs(struct task_struct *child,
0119               struct pt_watch_regs __user *addr)
0120 {
0121     enum pt_watch_style style;
0122     int i;
0123 
0124     if (!cpu_has_watch || boot_cpu_data.watch_reg_use_cnt == 0)
0125         return -EIO;
0126     if (!access_ok(addr, sizeof(struct pt_watch_regs)))
0127         return -EIO;
0128 
0129 #ifdef CONFIG_32BIT
0130     style = pt_watch_style_mips32;
0131 #define WATCH_STYLE mips32
0132 #else
0133     style = pt_watch_style_mips64;
0134 #define WATCH_STYLE mips64
0135 #endif
0136 
0137     __put_user(style, &addr->style);
0138     __put_user(boot_cpu_data.watch_reg_use_cnt,
0139            &addr->WATCH_STYLE.num_valid);
0140     for (i = 0; i < boot_cpu_data.watch_reg_use_cnt; i++) {
0141         __put_user(child->thread.watch.mips3264.watchlo[i],
0142                &addr->WATCH_STYLE.watchlo[i]);
0143         __put_user(child->thread.watch.mips3264.watchhi[i] &
0144                 (MIPS_WATCHHI_MASK | MIPS_WATCHHI_IRW),
0145                &addr->WATCH_STYLE.watchhi[i]);
0146         __put_user(boot_cpu_data.watch_reg_masks[i],
0147                &addr->WATCH_STYLE.watch_masks[i]);
0148     }
0149     for (; i < 8; i++) {
0150         __put_user(0, &addr->WATCH_STYLE.watchlo[i]);
0151         __put_user(0, &addr->WATCH_STYLE.watchhi[i]);
0152         __put_user(0, &addr->WATCH_STYLE.watch_masks[i]);
0153     }
0154 
0155     return 0;
0156 }
0157 
0158 int ptrace_set_watch_regs(struct task_struct *child,
0159               struct pt_watch_regs __user *addr)
0160 {
0161     int i;
0162     int watch_active = 0;
0163     unsigned long lt[NUM_WATCH_REGS];
0164     u16 ht[NUM_WATCH_REGS];
0165 
0166     if (!cpu_has_watch || boot_cpu_data.watch_reg_use_cnt == 0)
0167         return -EIO;
0168     if (!access_ok(addr, sizeof(struct pt_watch_regs)))
0169         return -EIO;
0170     /* Check the values. */
0171     for (i = 0; i < boot_cpu_data.watch_reg_use_cnt; i++) {
0172         __get_user(lt[i], &addr->WATCH_STYLE.watchlo[i]);
0173 #ifdef CONFIG_32BIT
0174         if (lt[i] & __UA_LIMIT)
0175             return -EINVAL;
0176 #else
0177         if (test_tsk_thread_flag(child, TIF_32BIT_ADDR)) {
0178             if (lt[i] & 0xffffffff80000000UL)
0179                 return -EINVAL;
0180         } else {
0181             if (lt[i] & __UA_LIMIT)
0182                 return -EINVAL;
0183         }
0184 #endif
0185         __get_user(ht[i], &addr->WATCH_STYLE.watchhi[i]);
0186         if (ht[i] & ~MIPS_WATCHHI_MASK)
0187             return -EINVAL;
0188     }
0189     /* Install them. */
0190     for (i = 0; i < boot_cpu_data.watch_reg_use_cnt; i++) {
0191         if (lt[i] & MIPS_WATCHLO_IRW)
0192             watch_active = 1;
0193         child->thread.watch.mips3264.watchlo[i] = lt[i];
0194         /* Set the G bit. */
0195         child->thread.watch.mips3264.watchhi[i] = ht[i];
0196     }
0197 
0198     if (watch_active)
0199         set_tsk_thread_flag(child, TIF_LOAD_WATCH);
0200     else
0201         clear_tsk_thread_flag(child, TIF_LOAD_WATCH);
0202 
0203     return 0;
0204 }
0205 
0206 /* regset get/set implementations */
0207 
0208 #if defined(CONFIG_32BIT) || defined(CONFIG_MIPS32_O32)
0209 
0210 static int gpr32_get(struct task_struct *target,
0211              const struct user_regset *regset,
0212              struct membuf to)
0213 {
0214     struct pt_regs *regs = task_pt_regs(target);
0215     u32 uregs[ELF_NGREG] = {};
0216 
0217     mips_dump_regs32(uregs, regs);
0218     return membuf_write(&to, uregs, sizeof(uregs));
0219 }
0220 
0221 static int gpr32_set(struct task_struct *target,
0222              const struct user_regset *regset,
0223              unsigned int pos, unsigned int count,
0224              const void *kbuf, const void __user *ubuf)
0225 {
0226     struct pt_regs *regs = task_pt_regs(target);
0227     u32 uregs[ELF_NGREG];
0228     unsigned start, num_regs, i;
0229     int err;
0230 
0231     start = pos / sizeof(u32);
0232     num_regs = count / sizeof(u32);
0233 
0234     if (start + num_regs > ELF_NGREG)
0235         return -EIO;
0236 
0237     err = user_regset_copyin(&pos, &count, &kbuf, &ubuf, uregs, 0,
0238                  sizeof(uregs));
0239     if (err)
0240         return err;
0241 
0242     for (i = start; i < num_regs; i++) {
0243         /*
0244          * Cast all values to signed here so that if this is a 64-bit
0245          * kernel, the supplied 32-bit values will be sign extended.
0246          */
0247         switch (i) {
0248         case MIPS32_EF_R1 ... MIPS32_EF_R25:
0249             /* k0/k1 are ignored. */
0250         case MIPS32_EF_R28 ... MIPS32_EF_R31:
0251             regs->regs[i - MIPS32_EF_R0] = (s32)uregs[i];
0252             break;
0253         case MIPS32_EF_LO:
0254             regs->lo = (s32)uregs[i];
0255             break;
0256         case MIPS32_EF_HI:
0257             regs->hi = (s32)uregs[i];
0258             break;
0259         case MIPS32_EF_CP0_EPC:
0260             regs->cp0_epc = (s32)uregs[i];
0261             break;
0262         }
0263     }
0264 
0265     /* System call number may have been changed */
0266     mips_syscall_update_nr(target, regs);
0267 
0268     return 0;
0269 }
0270 
0271 #endif /* CONFIG_32BIT || CONFIG_MIPS32_O32 */
0272 
0273 #ifdef CONFIG_64BIT
0274 
0275 static int gpr64_get(struct task_struct *target,
0276              const struct user_regset *regset,
0277              struct membuf to)
0278 {
0279     struct pt_regs *regs = task_pt_regs(target);
0280     u64 uregs[ELF_NGREG] = {};
0281 
0282     mips_dump_regs64(uregs, regs);
0283     return membuf_write(&to, uregs, sizeof(uregs));
0284 }
0285 
0286 static int gpr64_set(struct task_struct *target,
0287              const struct user_regset *regset,
0288              unsigned int pos, unsigned int count,
0289              const void *kbuf, const void __user *ubuf)
0290 {
0291     struct pt_regs *regs = task_pt_regs(target);
0292     u64 uregs[ELF_NGREG];
0293     unsigned start, num_regs, i;
0294     int err;
0295 
0296     start = pos / sizeof(u64);
0297     num_regs = count / sizeof(u64);
0298 
0299     if (start + num_regs > ELF_NGREG)
0300         return -EIO;
0301 
0302     err = user_regset_copyin(&pos, &count, &kbuf, &ubuf, uregs, 0,
0303                  sizeof(uregs));
0304     if (err)
0305         return err;
0306 
0307     for (i = start; i < num_regs; i++) {
0308         switch (i) {
0309         case MIPS64_EF_R1 ... MIPS64_EF_R25:
0310             /* k0/k1 are ignored. */
0311         case MIPS64_EF_R28 ... MIPS64_EF_R31:
0312             regs->regs[i - MIPS64_EF_R0] = uregs[i];
0313             break;
0314         case MIPS64_EF_LO:
0315             regs->lo = uregs[i];
0316             break;
0317         case MIPS64_EF_HI:
0318             regs->hi = uregs[i];
0319             break;
0320         case MIPS64_EF_CP0_EPC:
0321             regs->cp0_epc = uregs[i];
0322             break;
0323         }
0324     }
0325 
0326     /* System call number may have been changed */
0327     mips_syscall_update_nr(target, regs);
0328 
0329     return 0;
0330 }
0331 
0332 #endif /* CONFIG_64BIT */
0333 
0334 
0335 #ifdef CONFIG_MIPS_FP_SUPPORT
0336 
0337 /*
0338  * Poke at FCSR according to its mask.  Set the Cause bits even
0339  * if a corresponding Enable bit is set.  This will be noticed at
0340  * the time the thread is switched to and SIGFPE thrown accordingly.
0341  */
0342 static void ptrace_setfcr31(struct task_struct *child, u32 value)
0343 {
0344     u32 fcr31;
0345     u32 mask;
0346 
0347     fcr31 = child->thread.fpu.fcr31;
0348     mask = boot_cpu_data.fpu_msk31;
0349     child->thread.fpu.fcr31 = (value & ~mask) | (fcr31 & mask);
0350 }
0351 
0352 int ptrace_getfpregs(struct task_struct *child, __u32 __user *data)
0353 {
0354     int i;
0355 
0356     if (!access_ok(data, 33 * 8))
0357         return -EIO;
0358 
0359     if (tsk_used_math(child)) {
0360         union fpureg *fregs = get_fpu_regs(child);
0361         for (i = 0; i < 32; i++)
0362             __put_user(get_fpr64(&fregs[i], 0),
0363                    i + (__u64 __user *)data);
0364     } else {
0365         for (i = 0; i < 32; i++)
0366             __put_user((__u64) -1, i + (__u64 __user *) data);
0367     }
0368 
0369     __put_user(child->thread.fpu.fcr31, data + 64);
0370     __put_user(boot_cpu_data.fpu_id, data + 65);
0371 
0372     return 0;
0373 }
0374 
0375 int ptrace_setfpregs(struct task_struct *child, __u32 __user *data)
0376 {
0377     union fpureg *fregs;
0378     u64 fpr_val;
0379     u32 value;
0380     int i;
0381 
0382     if (!access_ok(data, 33 * 8))
0383         return -EIO;
0384 
0385     init_fp_ctx(child);
0386     fregs = get_fpu_regs(child);
0387 
0388     for (i = 0; i < 32; i++) {
0389         __get_user(fpr_val, i + (__u64 __user *)data);
0390         set_fpr64(&fregs[i], 0, fpr_val);
0391     }
0392 
0393     __get_user(value, data + 64);
0394     ptrace_setfcr31(child, value);
0395 
0396     /* FIR may not be written.  */
0397 
0398     return 0;
0399 }
0400 
0401 /*
0402  * Copy the floating-point context to the supplied NT_PRFPREG buffer,
0403  * !CONFIG_CPU_HAS_MSA variant.  FP context's general register slots
0404  * correspond 1:1 to buffer slots.  Only general registers are copied.
0405  */
0406 static void fpr_get_fpa(struct task_struct *target,
0407                struct membuf *to)
0408 {
0409     membuf_write(to, &target->thread.fpu,
0410             NUM_FPU_REGS * sizeof(elf_fpreg_t));
0411 }
0412 
0413 /*
0414  * Copy the floating-point context to the supplied NT_PRFPREG buffer,
0415  * CONFIG_CPU_HAS_MSA variant.  Only lower 64 bits of FP context's
0416  * general register slots are copied to buffer slots.  Only general
0417  * registers are copied.
0418  */
0419 static void fpr_get_msa(struct task_struct *target, struct membuf *to)
0420 {
0421     unsigned int i;
0422 
0423     BUILD_BUG_ON(sizeof(u64) != sizeof(elf_fpreg_t));
0424     for (i = 0; i < NUM_FPU_REGS; i++)
0425         membuf_store(to, get_fpr64(&target->thread.fpu.fpr[i], 0));
0426 }
0427 
0428 /*
0429  * Copy the floating-point context to the supplied NT_PRFPREG buffer.
0430  * Choose the appropriate helper for general registers, and then copy
0431  * the FCSR and FIR registers separately.
0432  */
0433 static int fpr_get(struct task_struct *target,
0434            const struct user_regset *regset,
0435            struct membuf to)
0436 {
0437     if (sizeof(target->thread.fpu.fpr[0]) == sizeof(elf_fpreg_t))
0438         fpr_get_fpa(target, &to);
0439     else
0440         fpr_get_msa(target, &to);
0441 
0442     membuf_write(&to, &target->thread.fpu.fcr31, sizeof(u32));
0443     membuf_write(&to, &boot_cpu_data.fpu_id, sizeof(u32));
0444     return 0;
0445 }
0446 
0447 /*
0448  * Copy the supplied NT_PRFPREG buffer to the floating-point context,
0449  * !CONFIG_CPU_HAS_MSA variant.   Buffer slots correspond 1:1 to FP
0450  * context's general register slots.  Only general registers are copied.
0451  */
0452 static int fpr_set_fpa(struct task_struct *target,
0453                unsigned int *pos, unsigned int *count,
0454                const void **kbuf, const void __user **ubuf)
0455 {
0456     return user_regset_copyin(pos, count, kbuf, ubuf,
0457                   &target->thread.fpu,
0458                   0, NUM_FPU_REGS * sizeof(elf_fpreg_t));
0459 }
0460 
0461 /*
0462  * Copy the supplied NT_PRFPREG buffer to the floating-point context,
0463  * CONFIG_CPU_HAS_MSA variant.  Buffer slots are copied to lower 64
0464  * bits only of FP context's general register slots.  Only general
0465  * registers are copied.
0466  */
0467 static int fpr_set_msa(struct task_struct *target,
0468                unsigned int *pos, unsigned int *count,
0469                const void **kbuf, const void __user **ubuf)
0470 {
0471     unsigned int i;
0472     u64 fpr_val;
0473     int err;
0474 
0475     BUILD_BUG_ON(sizeof(fpr_val) != sizeof(elf_fpreg_t));
0476     for (i = 0; i < NUM_FPU_REGS && *count > 0; i++) {
0477         err = user_regset_copyin(pos, count, kbuf, ubuf,
0478                      &fpr_val, i * sizeof(elf_fpreg_t),
0479                      (i + 1) * sizeof(elf_fpreg_t));
0480         if (err)
0481             return err;
0482         set_fpr64(&target->thread.fpu.fpr[i], 0, fpr_val);
0483     }
0484 
0485     return 0;
0486 }
0487 
0488 /*
0489  * Copy the supplied NT_PRFPREG buffer to the floating-point context.
0490  * Choose the appropriate helper for general registers, and then copy
0491  * the FCSR register separately.  Ignore the incoming FIR register
0492  * contents though, as the register is read-only.
0493  *
0494  * We optimize for the case where `count % sizeof(elf_fpreg_t) == 0',
0495  * which is supposed to have been guaranteed by the kernel before
0496  * calling us, e.g. in `ptrace_regset'.  We enforce that requirement,
0497  * so that we can safely avoid preinitializing temporaries for
0498  * partial register writes.
0499  */
0500 static int fpr_set(struct task_struct *target,
0501            const struct user_regset *regset,
0502            unsigned int pos, unsigned int count,
0503            const void *kbuf, const void __user *ubuf)
0504 {
0505     const int fcr31_pos = NUM_FPU_REGS * sizeof(elf_fpreg_t);
0506     const int fir_pos = fcr31_pos + sizeof(u32);
0507     u32 fcr31;
0508     int err;
0509 
0510     BUG_ON(count % sizeof(elf_fpreg_t));
0511 
0512     if (pos + count > sizeof(elf_fpregset_t))
0513         return -EIO;
0514 
0515     init_fp_ctx(target);
0516 
0517     if (sizeof(target->thread.fpu.fpr[0]) == sizeof(elf_fpreg_t))
0518         err = fpr_set_fpa(target, &pos, &count, &kbuf, &ubuf);
0519     else
0520         err = fpr_set_msa(target, &pos, &count, &kbuf, &ubuf);
0521     if (err)
0522         return err;
0523 
0524     if (count > 0) {
0525         err = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
0526                      &fcr31,
0527                      fcr31_pos, fcr31_pos + sizeof(u32));
0528         if (err)
0529             return err;
0530 
0531         ptrace_setfcr31(target, fcr31);
0532     }
0533 
0534     if (count > 0)
0535         err = user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf,
0536                         fir_pos,
0537                         fir_pos + sizeof(u32));
0538 
0539     return err;
0540 }
0541 
0542 /* Copy the FP mode setting to the supplied NT_MIPS_FP_MODE buffer.  */
0543 static int fp_mode_get(struct task_struct *target,
0544                const struct user_regset *regset,
0545                struct membuf to)
0546 {
0547     return membuf_store(&to, (int)mips_get_process_fp_mode(target));
0548 }
0549 
0550 /*
0551  * Copy the supplied NT_MIPS_FP_MODE buffer to the FP mode setting.
0552  *
0553  * We optimize for the case where `count % sizeof(int) == 0', which
0554  * is supposed to have been guaranteed by the kernel before calling
0555  * us, e.g. in `ptrace_regset'.  We enforce that requirement, so
0556  * that we can safely avoid preinitializing temporaries for partial
0557  * mode writes.
0558  */
0559 static int fp_mode_set(struct task_struct *target,
0560                const struct user_regset *regset,
0561                unsigned int pos, unsigned int count,
0562                const void *kbuf, const void __user *ubuf)
0563 {
0564     int fp_mode;
0565     int err;
0566 
0567     BUG_ON(count % sizeof(int));
0568 
0569     if (pos + count > sizeof(fp_mode))
0570         return -EIO;
0571 
0572     err = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &fp_mode, 0,
0573                  sizeof(fp_mode));
0574     if (err)
0575         return err;
0576 
0577     if (count > 0)
0578         err = mips_set_process_fp_mode(target, fp_mode);
0579 
0580     return err;
0581 }
0582 
0583 #endif /* CONFIG_MIPS_FP_SUPPORT */
0584 
0585 #ifdef CONFIG_CPU_HAS_MSA
0586 
0587 struct msa_control_regs {
0588     unsigned int fir;
0589     unsigned int fcsr;
0590     unsigned int msair;
0591     unsigned int msacsr;
0592 };
0593 
0594 static void copy_pad_fprs(struct task_struct *target,
0595              const struct user_regset *regset,
0596              struct membuf *to,
0597              unsigned int live_sz)
0598 {
0599     int i, j;
0600     unsigned long long fill = ~0ull;
0601     unsigned int cp_sz, pad_sz;
0602 
0603     cp_sz = min(regset->size, live_sz);
0604     pad_sz = regset->size - cp_sz;
0605     WARN_ON(pad_sz % sizeof(fill));
0606 
0607     for (i = 0; i < NUM_FPU_REGS; i++) {
0608         membuf_write(to, &target->thread.fpu.fpr[i], cp_sz);
0609         for (j = 0; j < (pad_sz / sizeof(fill)); j++)
0610             membuf_store(to, fill);
0611     }
0612 }
0613 
0614 static int msa_get(struct task_struct *target,
0615            const struct user_regset *regset,
0616            struct membuf to)
0617 {
0618     const unsigned int wr_size = NUM_FPU_REGS * regset->size;
0619     const struct msa_control_regs ctrl_regs = {
0620         .fir = boot_cpu_data.fpu_id,
0621         .fcsr = target->thread.fpu.fcr31,
0622         .msair = boot_cpu_data.msa_id,
0623         .msacsr = target->thread.fpu.msacsr,
0624     };
0625 
0626     if (!tsk_used_math(target)) {
0627         /* The task hasn't used FP or MSA, fill with 0xff */
0628         copy_pad_fprs(target, regset, &to, 0);
0629     } else if (!test_tsk_thread_flag(target, TIF_MSA_CTX_LIVE)) {
0630         /* Copy scalar FP context, fill the rest with 0xff */
0631         copy_pad_fprs(target, regset, &to, 8);
0632     } else if (sizeof(target->thread.fpu.fpr[0]) == regset->size) {
0633         /* Trivially copy the vector registers */
0634         membuf_write(&to, &target->thread.fpu.fpr, wr_size);
0635     } else {
0636         /* Copy as much context as possible, fill the rest with 0xff */
0637         copy_pad_fprs(target, regset, &to,
0638                 sizeof(target->thread.fpu.fpr[0]));
0639     }
0640 
0641     return membuf_write(&to, &ctrl_regs, sizeof(ctrl_regs));
0642 }
0643 
0644 static int msa_set(struct task_struct *target,
0645            const struct user_regset *regset,
0646            unsigned int pos, unsigned int count,
0647            const void *kbuf, const void __user *ubuf)
0648 {
0649     const unsigned int wr_size = NUM_FPU_REGS * regset->size;
0650     struct msa_control_regs ctrl_regs;
0651     unsigned int cp_sz;
0652     int i, err, start;
0653 
0654     init_fp_ctx(target);
0655 
0656     if (sizeof(target->thread.fpu.fpr[0]) == regset->size) {
0657         /* Trivially copy the vector registers */
0658         err = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
0659                      &target->thread.fpu.fpr,
0660                      0, wr_size);
0661     } else {
0662         /* Copy as much context as possible */
0663         cp_sz = min_t(unsigned int, regset->size,
0664                   sizeof(target->thread.fpu.fpr[0]));
0665 
0666         i = start = err = 0;
0667         for (; i < NUM_FPU_REGS; i++, start += regset->size) {
0668             err |= user_regset_copyin(&pos, &count, &kbuf, &ubuf,
0669                           &target->thread.fpu.fpr[i],
0670                           start, start + cp_sz);
0671         }
0672     }
0673 
0674     if (!err)
0675         err = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &ctrl_regs,
0676                      wr_size, wr_size + sizeof(ctrl_regs));
0677     if (!err) {
0678         target->thread.fpu.fcr31 = ctrl_regs.fcsr & ~FPU_CSR_ALL_X;
0679         target->thread.fpu.msacsr = ctrl_regs.msacsr & ~MSA_CSR_CAUSEF;
0680     }
0681 
0682     return err;
0683 }
0684 
0685 #endif /* CONFIG_CPU_HAS_MSA */
0686 
0687 #if defined(CONFIG_32BIT) || defined(CONFIG_MIPS32_O32)
0688 
0689 /*
0690  * Copy the DSP context to the supplied 32-bit NT_MIPS_DSP buffer.
0691  */
0692 static int dsp32_get(struct task_struct *target,
0693              const struct user_regset *regset,
0694              struct membuf to)
0695 {
0696     u32 dspregs[NUM_DSP_REGS + 1];
0697     unsigned int i;
0698 
0699     BUG_ON(to.left % sizeof(u32));
0700 
0701     if (!cpu_has_dsp)
0702         return -EIO;
0703 
0704     for (i = 0; i < NUM_DSP_REGS; i++)
0705         dspregs[i] = target->thread.dsp.dspr[i];
0706     dspregs[NUM_DSP_REGS] = target->thread.dsp.dspcontrol;
0707     return membuf_write(&to, dspregs, sizeof(dspregs));
0708 }
0709 
0710 /*
0711  * Copy the supplied 32-bit NT_MIPS_DSP buffer to the DSP context.
0712  */
0713 static int dsp32_set(struct task_struct *target,
0714              const struct user_regset *regset,
0715              unsigned int pos, unsigned int count,
0716              const void *kbuf, const void __user *ubuf)
0717 {
0718     unsigned int start, num_regs, i;
0719     u32 dspregs[NUM_DSP_REGS + 1];
0720     int err;
0721 
0722     BUG_ON(count % sizeof(u32));
0723 
0724     if (!cpu_has_dsp)
0725         return -EIO;
0726 
0727     start = pos / sizeof(u32);
0728     num_regs = count / sizeof(u32);
0729 
0730     if (start + num_regs > NUM_DSP_REGS + 1)
0731         return -EIO;
0732 
0733     err = user_regset_copyin(&pos, &count, &kbuf, &ubuf, dspregs, 0,
0734                  sizeof(dspregs));
0735     if (err)
0736         return err;
0737 
0738     for (i = start; i < num_regs; i++)
0739         switch (i) {
0740         case 0 ... NUM_DSP_REGS - 1:
0741             target->thread.dsp.dspr[i] = (s32)dspregs[i];
0742             break;
0743         case NUM_DSP_REGS:
0744             target->thread.dsp.dspcontrol = (s32)dspregs[i];
0745             break;
0746         }
0747 
0748     return 0;
0749 }
0750 
0751 #endif /* CONFIG_32BIT || CONFIG_MIPS32_O32 */
0752 
0753 #ifdef CONFIG_64BIT
0754 
0755 /*
0756  * Copy the DSP context to the supplied 64-bit NT_MIPS_DSP buffer.
0757  */
0758 static int dsp64_get(struct task_struct *target,
0759              const struct user_regset *regset,
0760              struct membuf to)
0761 {
0762     u64 dspregs[NUM_DSP_REGS + 1];
0763     unsigned int i;
0764 
0765     BUG_ON(to.left % sizeof(u64));
0766 
0767     if (!cpu_has_dsp)
0768         return -EIO;
0769 
0770     for (i = 0; i < NUM_DSP_REGS; i++)
0771         dspregs[i] = target->thread.dsp.dspr[i];
0772     dspregs[NUM_DSP_REGS] = target->thread.dsp.dspcontrol;
0773     return membuf_write(&to, dspregs, sizeof(dspregs));
0774 }
0775 
0776 /*
0777  * Copy the supplied 64-bit NT_MIPS_DSP buffer to the DSP context.
0778  */
0779 static int dsp64_set(struct task_struct *target,
0780              const struct user_regset *regset,
0781              unsigned int pos, unsigned int count,
0782              const void *kbuf, const void __user *ubuf)
0783 {
0784     unsigned int start, num_regs, i;
0785     u64 dspregs[NUM_DSP_REGS + 1];
0786     int err;
0787 
0788     BUG_ON(count % sizeof(u64));
0789 
0790     if (!cpu_has_dsp)
0791         return -EIO;
0792 
0793     start = pos / sizeof(u64);
0794     num_regs = count / sizeof(u64);
0795 
0796     if (start + num_regs > NUM_DSP_REGS + 1)
0797         return -EIO;
0798 
0799     err = user_regset_copyin(&pos, &count, &kbuf, &ubuf, dspregs, 0,
0800                  sizeof(dspregs));
0801     if (err)
0802         return err;
0803 
0804     for (i = start; i < num_regs; i++)
0805         switch (i) {
0806         case 0 ... NUM_DSP_REGS - 1:
0807             target->thread.dsp.dspr[i] = dspregs[i];
0808             break;
0809         case NUM_DSP_REGS:
0810             target->thread.dsp.dspcontrol = dspregs[i];
0811             break;
0812         }
0813 
0814     return 0;
0815 }
0816 
0817 #endif /* CONFIG_64BIT */
0818 
0819 /*
0820  * Determine whether the DSP context is present.
0821  */
0822 static int dsp_active(struct task_struct *target,
0823               const struct user_regset *regset)
0824 {
0825     return cpu_has_dsp ? NUM_DSP_REGS + 1 : -ENODEV;
0826 }
0827 
0828 enum mips_regset {
0829     REGSET_GPR,
0830     REGSET_DSP,
0831 #ifdef CONFIG_MIPS_FP_SUPPORT
0832     REGSET_FPR,
0833     REGSET_FP_MODE,
0834 #endif
0835 #ifdef CONFIG_CPU_HAS_MSA
0836     REGSET_MSA,
0837 #endif
0838 };
0839 
0840 struct pt_regs_offset {
0841     const char *name;
0842     int offset;
0843 };
0844 
0845 #define REG_OFFSET_NAME(reg, r) {                   \
0846     .name = #reg,                           \
0847     .offset = offsetof(struct pt_regs, r)               \
0848 }
0849 
0850 #define REG_OFFSET_END {                        \
0851     .name = NULL,                           \
0852     .offset = 0                         \
0853 }
0854 
0855 static const struct pt_regs_offset regoffset_table[] = {
0856     REG_OFFSET_NAME(r0, regs[0]),
0857     REG_OFFSET_NAME(r1, regs[1]),
0858     REG_OFFSET_NAME(r2, regs[2]),
0859     REG_OFFSET_NAME(r3, regs[3]),
0860     REG_OFFSET_NAME(r4, regs[4]),
0861     REG_OFFSET_NAME(r5, regs[5]),
0862     REG_OFFSET_NAME(r6, regs[6]),
0863     REG_OFFSET_NAME(r7, regs[7]),
0864     REG_OFFSET_NAME(r8, regs[8]),
0865     REG_OFFSET_NAME(r9, regs[9]),
0866     REG_OFFSET_NAME(r10, regs[10]),
0867     REG_OFFSET_NAME(r11, regs[11]),
0868     REG_OFFSET_NAME(r12, regs[12]),
0869     REG_OFFSET_NAME(r13, regs[13]),
0870     REG_OFFSET_NAME(r14, regs[14]),
0871     REG_OFFSET_NAME(r15, regs[15]),
0872     REG_OFFSET_NAME(r16, regs[16]),
0873     REG_OFFSET_NAME(r17, regs[17]),
0874     REG_OFFSET_NAME(r18, regs[18]),
0875     REG_OFFSET_NAME(r19, regs[19]),
0876     REG_OFFSET_NAME(r20, regs[20]),
0877     REG_OFFSET_NAME(r21, regs[21]),
0878     REG_OFFSET_NAME(r22, regs[22]),
0879     REG_OFFSET_NAME(r23, regs[23]),
0880     REG_OFFSET_NAME(r24, regs[24]),
0881     REG_OFFSET_NAME(r25, regs[25]),
0882     REG_OFFSET_NAME(r26, regs[26]),
0883     REG_OFFSET_NAME(r27, regs[27]),
0884     REG_OFFSET_NAME(r28, regs[28]),
0885     REG_OFFSET_NAME(r29, regs[29]),
0886     REG_OFFSET_NAME(r30, regs[30]),
0887     REG_OFFSET_NAME(r31, regs[31]),
0888     REG_OFFSET_NAME(c0_status, cp0_status),
0889     REG_OFFSET_NAME(hi, hi),
0890     REG_OFFSET_NAME(lo, lo),
0891 #ifdef CONFIG_CPU_HAS_SMARTMIPS
0892     REG_OFFSET_NAME(acx, acx),
0893 #endif
0894     REG_OFFSET_NAME(c0_badvaddr, cp0_badvaddr),
0895     REG_OFFSET_NAME(c0_cause, cp0_cause),
0896     REG_OFFSET_NAME(c0_epc, cp0_epc),
0897 #ifdef CONFIG_CPU_CAVIUM_OCTEON
0898     REG_OFFSET_NAME(mpl0, mpl[0]),
0899     REG_OFFSET_NAME(mpl1, mpl[1]),
0900     REG_OFFSET_NAME(mpl2, mpl[2]),
0901     REG_OFFSET_NAME(mtp0, mtp[0]),
0902     REG_OFFSET_NAME(mtp1, mtp[1]),
0903     REG_OFFSET_NAME(mtp2, mtp[2]),
0904 #endif
0905     REG_OFFSET_END,
0906 };
0907 
0908 /**
0909  * regs_query_register_offset() - query register offset from its name
0910  * @name:       the name of a register
0911  *
0912  * regs_query_register_offset() returns the offset of a register in struct
0913  * pt_regs from its name. If the name is invalid, this returns -EINVAL;
0914  */
0915 int regs_query_register_offset(const char *name)
0916 {
0917         const struct pt_regs_offset *roff;
0918         for (roff = regoffset_table; roff->name != NULL; roff++)
0919                 if (!strcmp(roff->name, name))
0920                         return roff->offset;
0921         return -EINVAL;
0922 }
0923 
0924 #if defined(CONFIG_32BIT) || defined(CONFIG_MIPS32_O32)
0925 
0926 static const struct user_regset mips_regsets[] = {
0927     [REGSET_GPR] = {
0928         .core_note_type = NT_PRSTATUS,
0929         .n      = ELF_NGREG,
0930         .size       = sizeof(unsigned int),
0931         .align      = sizeof(unsigned int),
0932         .regset_get     = gpr32_get,
0933         .set        = gpr32_set,
0934     },
0935     [REGSET_DSP] = {
0936         .core_note_type = NT_MIPS_DSP,
0937         .n      = NUM_DSP_REGS + 1,
0938         .size       = sizeof(u32),
0939         .align      = sizeof(u32),
0940         .regset_get     = dsp32_get,
0941         .set        = dsp32_set,
0942         .active     = dsp_active,
0943     },
0944 #ifdef CONFIG_MIPS_FP_SUPPORT
0945     [REGSET_FPR] = {
0946         .core_note_type = NT_PRFPREG,
0947         .n      = ELF_NFPREG,
0948         .size       = sizeof(elf_fpreg_t),
0949         .align      = sizeof(elf_fpreg_t),
0950         .regset_get     = fpr_get,
0951         .set        = fpr_set,
0952     },
0953     [REGSET_FP_MODE] = {
0954         .core_note_type = NT_MIPS_FP_MODE,
0955         .n      = 1,
0956         .size       = sizeof(int),
0957         .align      = sizeof(int),
0958         .regset_get     = fp_mode_get,
0959         .set        = fp_mode_set,
0960     },
0961 #endif
0962 #ifdef CONFIG_CPU_HAS_MSA
0963     [REGSET_MSA] = {
0964         .core_note_type = NT_MIPS_MSA,
0965         .n      = NUM_FPU_REGS + 1,
0966         .size       = 16,
0967         .align      = 16,
0968         .regset_get     = msa_get,
0969         .set        = msa_set,
0970     },
0971 #endif
0972 };
0973 
0974 static const struct user_regset_view user_mips_view = {
0975     .name       = "mips",
0976     .e_machine  = ELF_ARCH,
0977     .ei_osabi   = ELF_OSABI,
0978     .regsets    = mips_regsets,
0979     .n      = ARRAY_SIZE(mips_regsets),
0980 };
0981 
0982 #endif /* CONFIG_32BIT || CONFIG_MIPS32_O32 */
0983 
0984 #ifdef CONFIG_64BIT
0985 
0986 static const struct user_regset mips64_regsets[] = {
0987     [REGSET_GPR] = {
0988         .core_note_type = NT_PRSTATUS,
0989         .n      = ELF_NGREG,
0990         .size       = sizeof(unsigned long),
0991         .align      = sizeof(unsigned long),
0992         .regset_get     = gpr64_get,
0993         .set        = gpr64_set,
0994     },
0995     [REGSET_DSP] = {
0996         .core_note_type = NT_MIPS_DSP,
0997         .n      = NUM_DSP_REGS + 1,
0998         .size       = sizeof(u64),
0999         .align      = sizeof(u64),
1000         .regset_get     = dsp64_get,
1001         .set        = dsp64_set,
1002         .active     = dsp_active,
1003     },
1004 #ifdef CONFIG_MIPS_FP_SUPPORT
1005     [REGSET_FP_MODE] = {
1006         .core_note_type = NT_MIPS_FP_MODE,
1007         .n      = 1,
1008         .size       = sizeof(int),
1009         .align      = sizeof(int),
1010         .regset_get     = fp_mode_get,
1011         .set        = fp_mode_set,
1012     },
1013     [REGSET_FPR] = {
1014         .core_note_type = NT_PRFPREG,
1015         .n      = ELF_NFPREG,
1016         .size       = sizeof(elf_fpreg_t),
1017         .align      = sizeof(elf_fpreg_t),
1018         .regset_get     = fpr_get,
1019         .set        = fpr_set,
1020     },
1021 #endif
1022 #ifdef CONFIG_CPU_HAS_MSA
1023     [REGSET_MSA] = {
1024         .core_note_type = NT_MIPS_MSA,
1025         .n      = NUM_FPU_REGS + 1,
1026         .size       = 16,
1027         .align      = 16,
1028         .regset_get     = msa_get,
1029         .set        = msa_set,
1030     },
1031 #endif
1032 };
1033 
1034 static const struct user_regset_view user_mips64_view = {
1035     .name       = "mips64",
1036     .e_machine  = ELF_ARCH,
1037     .ei_osabi   = ELF_OSABI,
1038     .regsets    = mips64_regsets,
1039     .n      = ARRAY_SIZE(mips64_regsets),
1040 };
1041 
1042 #ifdef CONFIG_MIPS32_N32
1043 
1044 static const struct user_regset_view user_mipsn32_view = {
1045     .name       = "mipsn32",
1046     .e_flags    = EF_MIPS_ABI2,
1047     .e_machine  = ELF_ARCH,
1048     .ei_osabi   = ELF_OSABI,
1049     .regsets    = mips64_regsets,
1050     .n      = ARRAY_SIZE(mips64_regsets),
1051 };
1052 
1053 #endif /* CONFIG_MIPS32_N32 */
1054 
1055 #endif /* CONFIG_64BIT */
1056 
1057 const struct user_regset_view *task_user_regset_view(struct task_struct *task)
1058 {
1059 #ifdef CONFIG_32BIT
1060     return &user_mips_view;
1061 #else
1062 #ifdef CONFIG_MIPS32_O32
1063     if (test_tsk_thread_flag(task, TIF_32BIT_REGS))
1064         return &user_mips_view;
1065 #endif
1066 #ifdef CONFIG_MIPS32_N32
1067     if (test_tsk_thread_flag(task, TIF_32BIT_ADDR))
1068         return &user_mipsn32_view;
1069 #endif
1070     return &user_mips64_view;
1071 #endif
1072 }
1073 
1074 long arch_ptrace(struct task_struct *child, long request,
1075          unsigned long addr, unsigned long data)
1076 {
1077     int ret;
1078     void __user *addrp = (void __user *) addr;
1079     void __user *datavp = (void __user *) data;
1080     unsigned long __user *datalp = (void __user *) data;
1081 
1082     switch (request) {
1083     /* when I and D space are separate, these will need to be fixed. */
1084     case PTRACE_PEEKTEXT: /* read word at location addr. */
1085     case PTRACE_PEEKDATA:
1086         ret = generic_ptrace_peekdata(child, addr, data);
1087         break;
1088 
1089     /* Read the word at location addr in the USER area. */
1090     case PTRACE_PEEKUSR: {
1091         struct pt_regs *regs;
1092         unsigned long tmp = 0;
1093 
1094         regs = task_pt_regs(child);
1095         ret = 0;  /* Default return value. */
1096 
1097         switch (addr) {
1098         case 0 ... 31:
1099             tmp = regs->regs[addr];
1100             break;
1101 #ifdef CONFIG_MIPS_FP_SUPPORT
1102         case FPR_BASE ... FPR_BASE + 31: {
1103             union fpureg *fregs;
1104 
1105             if (!tsk_used_math(child)) {
1106                 /* FP not yet used */
1107                 tmp = -1;
1108                 break;
1109             }
1110             fregs = get_fpu_regs(child);
1111 
1112 #ifdef CONFIG_32BIT
1113             if (test_tsk_thread_flag(child, TIF_32BIT_FPREGS)) {
1114                 /*
1115                  * The odd registers are actually the high
1116                  * order bits of the values stored in the even
1117                  * registers.
1118                  */
1119                 tmp = get_fpr32(&fregs[(addr & ~1) - FPR_BASE],
1120                         addr & 1);
1121                 break;
1122             }
1123 #endif
1124             tmp = get_fpr64(&fregs[addr - FPR_BASE], 0);
1125             break;
1126         }
1127         case FPC_CSR:
1128             tmp = child->thread.fpu.fcr31;
1129             break;
1130         case FPC_EIR:
1131             /* implementation / version register */
1132             tmp = boot_cpu_data.fpu_id;
1133             break;
1134 #endif
1135         case PC:
1136             tmp = regs->cp0_epc;
1137             break;
1138         case CAUSE:
1139             tmp = regs->cp0_cause;
1140             break;
1141         case BADVADDR:
1142             tmp = regs->cp0_badvaddr;
1143             break;
1144         case MMHI:
1145             tmp = regs->hi;
1146             break;
1147         case MMLO:
1148             tmp = regs->lo;
1149             break;
1150 #ifdef CONFIG_CPU_HAS_SMARTMIPS
1151         case ACX:
1152             tmp = regs->acx;
1153             break;
1154 #endif
1155         case DSP_BASE ... DSP_BASE + 5: {
1156             dspreg_t *dregs;
1157 
1158             if (!cpu_has_dsp) {
1159                 tmp = 0;
1160                 ret = -EIO;
1161                 goto out;
1162             }
1163             dregs = __get_dsp_regs(child);
1164             tmp = dregs[addr - DSP_BASE];
1165             break;
1166         }
1167         case DSP_CONTROL:
1168             if (!cpu_has_dsp) {
1169                 tmp = 0;
1170                 ret = -EIO;
1171                 goto out;
1172             }
1173             tmp = child->thread.dsp.dspcontrol;
1174             break;
1175         default:
1176             tmp = 0;
1177             ret = -EIO;
1178             goto out;
1179         }
1180         ret = put_user(tmp, datalp);
1181         break;
1182     }
1183 
1184     /* when I and D space are separate, this will have to be fixed. */
1185     case PTRACE_POKETEXT: /* write the word at location addr. */
1186     case PTRACE_POKEDATA:
1187         ret = generic_ptrace_pokedata(child, addr, data);
1188         break;
1189 
1190     case PTRACE_POKEUSR: {
1191         struct pt_regs *regs;
1192         ret = 0;
1193         regs = task_pt_regs(child);
1194 
1195         switch (addr) {
1196         case 0 ... 31:
1197             regs->regs[addr] = data;
1198             /* System call number may have been changed */
1199             if (addr == 2)
1200                 mips_syscall_update_nr(child, regs);
1201             else if (addr == 4 &&
1202                  mips_syscall_is_indirect(child, regs))
1203                 mips_syscall_update_nr(child, regs);
1204             break;
1205 #ifdef CONFIG_MIPS_FP_SUPPORT
1206         case FPR_BASE ... FPR_BASE + 31: {
1207             union fpureg *fregs = get_fpu_regs(child);
1208 
1209             init_fp_ctx(child);
1210 #ifdef CONFIG_32BIT
1211             if (test_tsk_thread_flag(child, TIF_32BIT_FPREGS)) {
1212                 /*
1213                  * The odd registers are actually the high
1214                  * order bits of the values stored in the even
1215                  * registers.
1216                  */
1217                 set_fpr32(&fregs[(addr & ~1) - FPR_BASE],
1218                       addr & 1, data);
1219                 break;
1220             }
1221 #endif
1222             set_fpr64(&fregs[addr - FPR_BASE], 0, data);
1223             break;
1224         }
1225         case FPC_CSR:
1226             init_fp_ctx(child);
1227             ptrace_setfcr31(child, data);
1228             break;
1229 #endif
1230         case PC:
1231             regs->cp0_epc = data;
1232             break;
1233         case MMHI:
1234             regs->hi = data;
1235             break;
1236         case MMLO:
1237             regs->lo = data;
1238             break;
1239 #ifdef CONFIG_CPU_HAS_SMARTMIPS
1240         case ACX:
1241             regs->acx = data;
1242             break;
1243 #endif
1244         case DSP_BASE ... DSP_BASE + 5: {
1245             dspreg_t *dregs;
1246 
1247             if (!cpu_has_dsp) {
1248                 ret = -EIO;
1249                 break;
1250             }
1251 
1252             dregs = __get_dsp_regs(child);
1253             dregs[addr - DSP_BASE] = data;
1254             break;
1255         }
1256         case DSP_CONTROL:
1257             if (!cpu_has_dsp) {
1258                 ret = -EIO;
1259                 break;
1260             }
1261             child->thread.dsp.dspcontrol = data;
1262             break;
1263         default:
1264             /* The rest are not allowed. */
1265             ret = -EIO;
1266             break;
1267         }
1268         break;
1269         }
1270 
1271     case PTRACE_GETREGS:
1272         ret = ptrace_getregs(child, datavp);
1273         break;
1274 
1275     case PTRACE_SETREGS:
1276         ret = ptrace_setregs(child, datavp);
1277         break;
1278 
1279 #ifdef CONFIG_MIPS_FP_SUPPORT
1280     case PTRACE_GETFPREGS:
1281         ret = ptrace_getfpregs(child, datavp);
1282         break;
1283 
1284     case PTRACE_SETFPREGS:
1285         ret = ptrace_setfpregs(child, datavp);
1286         break;
1287 #endif
1288     case PTRACE_GET_THREAD_AREA:
1289         ret = put_user(task_thread_info(child)->tp_value, datalp);
1290         break;
1291 
1292     case PTRACE_GET_WATCH_REGS:
1293         ret = ptrace_get_watch_regs(child, addrp);
1294         break;
1295 
1296     case PTRACE_SET_WATCH_REGS:
1297         ret = ptrace_set_watch_regs(child, addrp);
1298         break;
1299 
1300     default:
1301         ret = ptrace_request(child, request, addr, data);
1302         break;
1303     }
1304  out:
1305     return ret;
1306 }
1307 
1308 /*
1309  * Notification of system call entry/exit
1310  * - triggered by current->work.syscall_trace
1311  */
1312 asmlinkage long syscall_trace_enter(struct pt_regs *regs, long syscall)
1313 {
1314     user_exit();
1315 
1316     current_thread_info()->syscall = syscall;
1317 
1318     if (test_thread_flag(TIF_SYSCALL_TRACE)) {
1319         if (ptrace_report_syscall_entry(regs))
1320             return -1;
1321         syscall = current_thread_info()->syscall;
1322     }
1323 
1324 #ifdef CONFIG_SECCOMP
1325     if (unlikely(test_thread_flag(TIF_SECCOMP))) {
1326         int ret, i;
1327         struct seccomp_data sd;
1328         unsigned long args[6];
1329 
1330         sd.nr = syscall;
1331         sd.arch = syscall_get_arch(current);
1332         syscall_get_arguments(current, regs, args);
1333         for (i = 0; i < 6; i++)
1334             sd.args[i] = args[i];
1335         sd.instruction_pointer = KSTK_EIP(current);
1336 
1337         ret = __secure_computing(&sd);
1338         if (ret == -1)
1339             return ret;
1340         syscall = current_thread_info()->syscall;
1341     }
1342 #endif
1343 
1344     if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
1345         trace_sys_enter(regs, regs->regs[2]);
1346 
1347     audit_syscall_entry(syscall, regs->regs[4], regs->regs[5],
1348                 regs->regs[6], regs->regs[7]);
1349 
1350     /*
1351      * Negative syscall numbers are mistaken for rejected syscalls, but
1352      * won't have had the return value set appropriately, so we do so now.
1353      */
1354     if (syscall < 0)
1355         syscall_set_return_value(current, regs, -ENOSYS, 0);
1356     return syscall;
1357 }
1358 
1359 /*
1360  * Notification of system call entry/exit
1361  * - triggered by current->work.syscall_trace
1362  */
1363 asmlinkage void syscall_trace_leave(struct pt_regs *regs)
1364 {
1365         /*
1366      * We may come here right after calling schedule_user()
1367      * or do_notify_resume(), in which case we can be in RCU
1368      * user mode.
1369      */
1370     user_exit();
1371 
1372     audit_syscall_exit(regs);
1373 
1374     if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
1375         trace_sys_exit(regs, regs_return_value(regs));
1376 
1377     if (test_thread_flag(TIF_SYSCALL_TRACE))
1378         ptrace_report_syscall_exit(regs, 0);
1379 
1380     user_enter();
1381 }
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