mips/kernel/mips-mt.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * General MIPS MT support routines, usable in AP/SP and SMVP.
0004  * Copyright (C) 2005 Mips Technologies, Inc
0005  */
0006
0007 #include <linux/device.h>
0008 #include <linux/kernel.h>
0009 #include <linux/sched.h>
0010 #include <linux/export.h>
0011 #include <linux/interrupt.h>
0012 #include <linux/security.h>
0013
0014 #include <asm/cpu.h>
0015 #include <asm/processor.h>
0016 #include <linux/atomic.h>
0017 #include <asm/hardirq.h>
0018 #include <asm/mmu_context.h>
0019 #include <asm/mipsmtregs.h>
0020 #include <asm/r4kcache.h>
0021 #include <asm/cacheflush.h>
0022
0023 int vpelimit;
0024
0025 static int __init maxvpes(char *str)
0026 {
0027     get_option(&str, &vpelimit);
0028
0029     return 1;
0030 }
0031
0032 __setup("maxvpes=", maxvpes);
0033
0034 int tclimit;
0035
0036 static int __init maxtcs(char *str)
0037 {
0038     get_option(&str, &tclimit);
0039
0040     return 1;
0041 }
0042
0043 __setup("maxtcs=", maxtcs);
0044
0045 /*
0046  * Dump new MIPS MT state for the core. Does not leave TCs halted.
0047  * Takes an argument which taken to be a pre-call MVPControl value.
0048  */
0049
0050 void mips_mt_regdump(unsigned long mvpctl)
0051 {
0052     unsigned long flags;
0053     unsigned long vpflags;
0054     unsigned long mvpconf0;
0055     int nvpe;
0056     int ntc;
0057     int i;
0058     int tc;
0059     unsigned long haltval;
0060     unsigned long tcstatval;
0061
0062     local_irq_save(flags);
0063     vpflags = dvpe();
0064     printk("=== MIPS MT State Dump ===\n");
0065     printk("-- Global State --\n");
0066     printk("   MVPControl Passed: %08lx\n", mvpctl);
0067     printk("   MVPControl Read: %08lx\n", vpflags);
0068     printk("   MVPConf0 : %08lx\n", (mvpconf0 = read_c0_mvpconf0()));
0069     nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
0070     ntc = ((mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1;
0071     printk("-- per-VPE State --\n");
0072     for (i = 0; i < nvpe; i++) {
0073         for (tc = 0; tc < ntc; tc++) {
0074             settc(tc);
0075             if ((read_tc_c0_tcbind() & TCBIND_CURVPE) == i) {
0076                 printk("  VPE %d\n", i);
0077                 printk("   VPEControl : %08lx\n",
0078                        read_vpe_c0_vpecontrol());
0079                 printk("   VPEConf0 : %08lx\n",
0080                        read_vpe_c0_vpeconf0());
0081                 printk("   VPE%d.Status : %08lx\n",
0082                        i, read_vpe_c0_status());
0083                 printk("   VPE%d.EPC : %08lx %pS\n",
0084                        i, read_vpe_c0_epc(),
0085                        (void *) read_vpe_c0_epc());
0086                 printk("   VPE%d.Cause : %08lx\n",
0087                        i, read_vpe_c0_cause());
0088                 printk("   VPE%d.Config7 : %08lx\n",
0089                        i, read_vpe_c0_config7());
0090                 break; /* Next VPE */
0091             }
0092         }
0093     }
0094     printk("-- per-TC State --\n");
0095     for (tc = 0; tc < ntc; tc++) {
0096         settc(tc);
0097         if (read_tc_c0_tcbind() == read_c0_tcbind()) {
0098             /* Are we dumping ourself?  */
0099             haltval = 0; /* Then we're not halted, and mustn't be */
0100             tcstatval = flags; /* And pre-dump TCStatus is flags */
0101             printk("  TC %d (current TC with VPE EPC above)\n", tc);
0102         } else {
0103             haltval = read_tc_c0_tchalt();
0104             write_tc_c0_tchalt(1);
0105             tcstatval = read_tc_c0_tcstatus();
0106             printk("  TC %d\n", tc);
0107         }
0108         printk("   TCStatus : %08lx\n", tcstatval);
0109         printk("   TCBind : %08lx\n", read_tc_c0_tcbind());
0110         printk("   TCRestart : %08lx %pS\n",
0111                read_tc_c0_tcrestart(), (void *) read_tc_c0_tcrestart());
0112         printk("   TCHalt : %08lx\n", haltval);
0113         printk("   TCContext : %08lx\n", read_tc_c0_tccontext());
0114         if (!haltval)
0115             write_tc_c0_tchalt(0);
0116     }
0117     printk("===========================\n");
0118     evpe(vpflags);
0119     local_irq_restore(flags);
0120 }
0121
0122 static int mt_opt_rpsctl = -1;
0123 static int mt_opt_nblsu = -1;
0124 static int mt_opt_forceconfig7;
0125 static int mt_opt_config7 = -1;
0126
0127 static int __init rpsctl_set(char *str)
0128 {
0129     get_option(&str, &mt_opt_rpsctl);
0130     return 1;
0131 }
0132 __setup("rpsctl=", rpsctl_set);
0133
0134 static int __init nblsu_set(char *str)
0135 {
0136     get_option(&str, &mt_opt_nblsu);
0137     return 1;
0138 }
0139 __setup("nblsu=", nblsu_set);
0140
0141 static int __init config7_set(char *str)
0142 {
0143     get_option(&str, &mt_opt_config7);
0144     mt_opt_forceconfig7 = 1;
0145     return 1;
0146 }
0147 __setup("config7=", config7_set);
0148
0149 static unsigned int itc_base;
0150
0151 static int __init set_itc_base(char *str)
0152 {
0153     get_option(&str, &itc_base);
0154     return 1;
0155 }
0156
0157 __setup("itcbase=", set_itc_base);
0158
0159 void mips_mt_set_cpuoptions(void)
0160 {
0161     unsigned int oconfig7 = read_c0_config7();
0162     unsigned int nconfig7 = oconfig7;
0163
0164     if (mt_opt_rpsctl >= 0) {
0165         printk("34K return prediction stack override set to %d.\n",
0166             mt_opt_rpsctl);
0167         if (mt_opt_rpsctl)
0168             nconfig7 |= (1 << 2);
0169         else
0170             nconfig7 &= ~(1 << 2);
0171     }
0172     if (mt_opt_nblsu >= 0) {
0173         printk("34K ALU/LSU sync override set to %d.\n", mt_opt_nblsu);
0174         if (mt_opt_nblsu)
0175             nconfig7 |= (1 << 5);
0176         else
0177             nconfig7 &= ~(1 << 5);
0178     }
0179     if (mt_opt_forceconfig7) {
0180         printk("CP0.Config7 forced to 0x%08x.\n", mt_opt_config7);
0181         nconfig7 = mt_opt_config7;
0182     }
0183     if (oconfig7 != nconfig7) {
0184         __asm__ __volatile("sync");
0185         write_c0_config7(nconfig7);
0186         ehb();
0187         printk("Config7: 0x%08x\n", read_c0_config7());
0188     }
0189
0190     if (itc_base != 0) {
0191         /*
0192          * Configure ITC mapping.  This code is very
0193          * specific to the 34K core family, which uses
0194          * a special mode bit ("ITC") in the ErrCtl
0195          * register to enable access to ITC control
0196          * registers via cache "tag" operations.
0197          */
0198         unsigned long ectlval;
0199         unsigned long itcblkgrn;
0200
0201         /* ErrCtl register is known as "ecc" to Linux */
0202         ectlval = read_c0_ecc();
0203         write_c0_ecc(ectlval | (0x1 << 26));
0204         ehb();
0205 #define INDEX_0 (0x80000000)
0206 #define INDEX_8 (0x80000008)
0207         /* Read "cache tag" for Dcache pseudo-index 8 */
0208         cache_op(Index_Load_Tag_D, INDEX_8);
0209         ehb();
0210         itcblkgrn = read_c0_dtaglo();
0211         itcblkgrn &= 0xfffe0000;
0212         /* Set for 128 byte pitch of ITC cells */
0213         itcblkgrn |= 0x00000c00;
0214         /* Stage in Tag register */
0215         write_c0_dtaglo(itcblkgrn);
0216         ehb();
0217         /* Write out to ITU with CACHE op */
0218         cache_op(Index_Store_Tag_D, INDEX_8);
0219         /* Now set base address, and turn ITC on with 0x1 bit */
0220         write_c0_dtaglo((itc_base & 0xfffffc00) | 0x1 );
0221         ehb();
0222         /* Write out to ITU with CACHE op */
0223         cache_op(Index_Store_Tag_D, INDEX_0);
0224         write_c0_ecc(ectlval);
0225         ehb();
0226         printk("Mapped %ld ITC cells starting at 0x%08x\n",
0227             ((itcblkgrn & 0x7fe00000) >> 20), itc_base);
0228     }
0229 }
0230
0231 struct class *mt_class;
0232
0233 static int __init mips_mt_init(void)
0234 {
0235     struct class *mtc;
0236
0237     mtc = class_create(THIS_MODULE, "mt");
0238     if (IS_ERR(mtc))
0239         return PTR_ERR(mtc);
0240
0241     mt_class = mtc;
0242
0243     return 0;
0244 }
0245
0246 subsys_initcall(mips_mt_init);