mips/kernel/irq_txx9.c

0001 /*
0002  * Based on linux/arch/mips/jmr3927/rbhma3100/irq.c,
0003  *      linux/arch/mips/tx4927/common/tx4927_irq.c,
0004  *      linux/arch/mips/tx4938/common/irq.c
0005  *
0006  * Copyright 2001, 2003-2005 MontaVista Software Inc.
0007  * Author: MontaVista Software, Inc.
0008  *     ahennessy@mvista.com
0009  *     source@mvista.com
0010  * Copyright (C) 2000-2001 Toshiba Corporation
0011  *
0012  * This file is subject to the terms and conditions of the GNU General Public
0013  * License.  See the file "COPYING" in the main directory of this archive
0014  * for more details.
0015  */
0016 #include <linux/init.h>
0017 #include <linux/interrupt.h>
0018 #include <linux/types.h>
0019 #include <linux/irq.h>
0020 #include <asm/txx9irq.h>
0021
0022 struct txx9_irc_reg {
0023     u32 cer;
0024     u32 cr[2];
0025     u32 unused0;
0026     u32 ilr[8];
0027     u32 unused1[4];
0028     u32 imr;
0029     u32 unused2[7];
0030     u32 scr;
0031     u32 unused3[7];
0032     u32 ssr;
0033     u32 unused4[7];
0034     u32 csr;
0035 };
0036
0037 /* IRCER : Int. Control Enable */
0038 #define TXx9_IRCER_ICE  0x00000001
0039
0040 /* IRCR : Int. Control */
0041 #define TXx9_IRCR_LOW   0x00000000
0042 #define TXx9_IRCR_HIGH  0x00000001
0043 #define TXx9_IRCR_DOWN  0x00000002
0044 #define TXx9_IRCR_UP    0x00000003
0045 #define TXx9_IRCR_EDGE(cr)  ((cr) & 0x00000002)
0046
0047 /* IRSCR : Int. Status Control */
0048 #define TXx9_IRSCR_EIClrE   0x00000100
0049 #define TXx9_IRSCR_EIClr_MASK   0x0000000f
0050
0051 /* IRCSR : Int. Current Status */
0052 #define TXx9_IRCSR_IF   0x00010000
0053 #define TXx9_IRCSR_ILV_MASK 0x00000700
0054 #define TXx9_IRCSR_IVL_MASK 0x0000001f
0055
0056 #define irc_dlevel  0
0057 #define irc_elevel  1
0058
0059 static struct txx9_irc_reg __iomem *txx9_ircptr __read_mostly;
0060
0061 static struct {
0062     unsigned char level;
0063     unsigned char mode;
0064 } txx9irq[TXx9_MAX_IR] __read_mostly;
0065
0066 static void txx9_irq_unmask(struct irq_data *d)
0067 {
0068     unsigned int irq_nr = d->irq - TXX9_IRQ_BASE;
0069     u32 __iomem *ilrp = &txx9_ircptr->ilr[(irq_nr % 16 ) / 2];
0070     int ofs = irq_nr / 16 * 16 + (irq_nr & 1) * 8;
0071
0072     __raw_writel((__raw_readl(ilrp) & ~(0xff << ofs))
0073              | (txx9irq[irq_nr].level << ofs),
0074              ilrp);
0075 }
0076
0077 static inline void txx9_irq_mask(struct irq_data *d)
0078 {
0079     unsigned int irq_nr = d->irq - TXX9_IRQ_BASE;
0080     u32 __iomem *ilrp = &txx9_ircptr->ilr[(irq_nr % 16) / 2];
0081     int ofs = irq_nr / 16 * 16 + (irq_nr & 1) * 8;
0082
0083     __raw_writel((__raw_readl(ilrp) & ~(0xff << ofs))
0084              | (irc_dlevel << ofs),
0085              ilrp);
0086     mmiowb();
0087 }
0088
0089 static void txx9_irq_mask_ack(struct irq_data *d)
0090 {
0091     unsigned int irq_nr = d->irq - TXX9_IRQ_BASE;
0092
0093     txx9_irq_mask(d);
0094     /* clear edge detection */
0095     if (unlikely(TXx9_IRCR_EDGE(txx9irq[irq_nr].mode)))
0096         __raw_writel(TXx9_IRSCR_EIClrE | irq_nr, &txx9_ircptr->scr);
0097 }
0098
0099 static int txx9_irq_set_type(struct irq_data *d, unsigned int flow_type)
0100 {
0101     unsigned int irq_nr = d->irq - TXX9_IRQ_BASE;
0102     u32 cr;
0103     u32 __iomem *crp;
0104     int ofs;
0105     int mode;
0106
0107     if (flow_type & IRQF_TRIGGER_PROBE)
0108         return 0;
0109     switch (flow_type & IRQF_TRIGGER_MASK) {
0110     case IRQF_TRIGGER_RISING:   mode = TXx9_IRCR_UP;    break;
0111     case IRQF_TRIGGER_FALLING:  mode = TXx9_IRCR_DOWN;  break;
0112     case IRQF_TRIGGER_HIGH: mode = TXx9_IRCR_HIGH;  break;
0113     case IRQF_TRIGGER_LOW:  mode = TXx9_IRCR_LOW;   break;
0114     default:
0115         return -EINVAL;
0116     }
0117     crp = &txx9_ircptr->cr[(unsigned int)irq_nr / 8];
0118     cr = __raw_readl(crp);
0119     ofs = (irq_nr & (8 - 1)) * 2;
0120     cr &= ~(0x3 << ofs);
0121     cr |= (mode & 0x3) << ofs;
0122     __raw_writel(cr, crp);
0123     txx9irq[irq_nr].mode = mode;
0124     return 0;
0125 }
0126
0127 static struct irq_chip txx9_irq_chip = {
0128     .name       = "TXX9",
0129     .irq_ack    = txx9_irq_mask_ack,
0130     .irq_mask   = txx9_irq_mask,
0131     .irq_mask_ack   = txx9_irq_mask_ack,
0132     .irq_unmask = txx9_irq_unmask,
0133     .irq_set_type   = txx9_irq_set_type,
0134 };
0135
0136 void __init txx9_irq_init(unsigned long baseaddr)
0137 {
0138     int i;
0139
0140     txx9_ircptr = ioremap(baseaddr, sizeof(struct txx9_irc_reg));
0141     for (i = 0; i < TXx9_MAX_IR; i++) {
0142         txx9irq[i].level = 4; /* middle level */
0143         txx9irq[i].mode = TXx9_IRCR_LOW;
0144         irq_set_chip_and_handler(TXX9_IRQ_BASE + i, &txx9_irq_chip,
0145                      handle_level_irq);
0146     }
0147
0148     /* mask all IRC interrupts */
0149     __raw_writel(0, &txx9_ircptr->imr);
0150     for (i = 0; i < 8; i++)
0151         __raw_writel(0, &txx9_ircptr->ilr[i]);
0152     /* setup IRC interrupt mode (Low Active) */
0153     for (i = 0; i < 2; i++)
0154         __raw_writel(0, &txx9_ircptr->cr[i]);
0155     /* enable interrupt control */
0156     __raw_writel(TXx9_IRCER_ICE, &txx9_ircptr->cer);
0157     __raw_writel(irc_elevel, &txx9_ircptr->imr);
0158 }
0159
0160 int __init txx9_irq_set_pri(int irc_irq, int new_pri)
0161 {
0162     int old_pri;
0163
0164     if ((unsigned int)irc_irq >= TXx9_MAX_IR)
0165         return 0;
0166     old_pri = txx9irq[irc_irq].level;
0167     txx9irq[irc_irq].level = new_pri;
0168     return old_pri;
0169 }
0170
0171 int txx9_irq(void)
0172 {
0173     u32 csr = __raw_readl(&txx9_ircptr->csr);
0174
0175     if (likely(!(csr & TXx9_IRCSR_IF)))
0176         return TXX9_IRQ_BASE + (csr & (TXx9_MAX_IR - 1));
0177     return -1;
0178 }