mips/kernel/irq-msc01.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  *
0004  * Copyright (c) 2004 MIPS Inc
0005  * Author: chris@mips.com
0006  *
0007  * Copyright (C) 2004, 06 Ralf Baechle <ralf@linux-mips.org>
0008  */
0009 #include <linux/interrupt.h>
0010 #include <linux/kernel.h>
0011 #include <linux/sched.h>
0012 #include <linux/kernel_stat.h>
0013 #include <asm/io.h>
0014 #include <asm/irq.h>
0015 #include <asm/msc01_ic.h>
0016 #include <asm/traps.h>
0017
0018 static unsigned long _icctrl_msc;
0019 #define MSC01_IC_REG_BASE   _icctrl_msc
0020
0021 #define MSCIC_WRITE(reg, data)  do { *(volatile u32 *)(reg) = data; } while (0)
0022 #define MSCIC_READ(reg, data)   do { data = *(volatile u32 *)(reg); } while (0)
0023
0024 static unsigned int irq_base;
0025
0026 /* mask off an interrupt */
0027 static inline void mask_msc_irq(struct irq_data *d)
0028 {
0029     unsigned int irq = d->irq;
0030
0031     if (irq < (irq_base + 32))
0032         MSCIC_WRITE(MSC01_IC_DISL, 1<<(irq - irq_base));
0033     else
0034         MSCIC_WRITE(MSC01_IC_DISH, 1<<(irq - irq_base - 32));
0035 }
0036
0037 /* unmask an interrupt */
0038 static inline void unmask_msc_irq(struct irq_data *d)
0039 {
0040     unsigned int irq = d->irq;
0041
0042     if (irq < (irq_base + 32))
0043         MSCIC_WRITE(MSC01_IC_ENAL, 1<<(irq - irq_base));
0044     else
0045         MSCIC_WRITE(MSC01_IC_ENAH, 1<<(irq - irq_base - 32));
0046 }
0047
0048 /*
0049  * Masks and ACKs an IRQ
0050  */
0051 static void level_mask_and_ack_msc_irq(struct irq_data *d)
0052 {
0053     mask_msc_irq(d);
0054     if (!cpu_has_veic)
0055         MSCIC_WRITE(MSC01_IC_EOI, 0);
0056 }
0057
0058 /*
0059  * Masks and ACKs an IRQ
0060  */
0061 static void edge_mask_and_ack_msc_irq(struct irq_data *d)
0062 {
0063     unsigned int irq = d->irq;
0064
0065     mask_msc_irq(d);
0066     if (!cpu_has_veic)
0067         MSCIC_WRITE(MSC01_IC_EOI, 0);
0068     else {
0069         u32 r;
0070         MSCIC_READ(MSC01_IC_SUP+irq*8, r);
0071         MSCIC_WRITE(MSC01_IC_SUP+irq*8, r | ~MSC01_IC_SUP_EDGE_BIT);
0072         MSCIC_WRITE(MSC01_IC_SUP+irq*8, r);
0073     }
0074 }
0075
0076 /*
0077  * Interrupt handler for interrupts coming from SOC-it.
0078  */
0079 void ll_msc_irq(void)
0080 {
0081     unsigned int irq;
0082
0083     /* read the interrupt vector register */
0084     MSCIC_READ(MSC01_IC_VEC, irq);
0085     if (irq < 64)
0086         do_IRQ(irq + irq_base);
0087     else {
0088         /* Ignore spurious interrupt */
0089     }
0090 }
0091
0092 static void msc_bind_eic_interrupt(int irq, int set)
0093 {
0094     MSCIC_WRITE(MSC01_IC_RAMW,
0095             (irq<<MSC01_IC_RAMW_ADDR_SHF) | (set<<MSC01_IC_RAMW_DATA_SHF));
0096 }
0097
0098 static struct irq_chip msc_levelirq_type = {
0099     .name = "SOC-it-Level",
0100     .irq_ack = level_mask_and_ack_msc_irq,
0101     .irq_mask = mask_msc_irq,
0102     .irq_mask_ack = level_mask_and_ack_msc_irq,
0103     .irq_unmask = unmask_msc_irq,
0104     .irq_eoi = unmask_msc_irq,
0105 };
0106
0107 static struct irq_chip msc_edgeirq_type = {
0108     .name = "SOC-it-Edge",
0109     .irq_ack = edge_mask_and_ack_msc_irq,
0110     .irq_mask = mask_msc_irq,
0111     .irq_mask_ack = edge_mask_and_ack_msc_irq,
0112     .irq_unmask = unmask_msc_irq,
0113     .irq_eoi = unmask_msc_irq,
0114 };
0115
0116
0117 void __init init_msc_irqs(unsigned long icubase, unsigned int irqbase, msc_irqmap_t *imp, int nirq)
0118 {
0119     _icctrl_msc = (unsigned long) ioremap(icubase, 0x40000);
0120
0121     /* Reset interrupt controller - initialises all registers to 0 */
0122     MSCIC_WRITE(MSC01_IC_RST, MSC01_IC_RST_RST_BIT);
0123
0124     board_bind_eic_interrupt = &msc_bind_eic_interrupt;
0125
0126     for (; nirq > 0; nirq--, imp++) {
0127         int n = imp->im_irq;
0128
0129         switch (imp->im_type) {
0130         case MSC01_IRQ_EDGE:
0131             irq_set_chip_and_handler_name(irqbase + n,
0132                               &msc_edgeirq_type,
0133                               handle_edge_irq,
0134                               "edge");
0135             if (cpu_has_veic)
0136                 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT);
0137             else
0138                 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl);
0139             break;
0140         case MSC01_IRQ_LEVEL:
0141             irq_set_chip_and_handler_name(irqbase + n,
0142                               &msc_levelirq_type,
0143                               handle_level_irq,
0144                               "level");
0145             if (cpu_has_veic)
0146                 MSCIC_WRITE(MSC01_IC_SUP+n*8, 0);
0147             else
0148                 MSCIC_WRITE(MSC01_IC_SUP+n*8, imp->im_lvl);
0149         }
0150     }
0151
0152     irq_base = irqbase;
0153
0154     MSCIC_WRITE(MSC01_IC_GENA, MSC01_IC_GENA_GENA_BIT); /* Enable interrupt generation */
0155
0156 }