mips/kernel/elf.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (C) 2014 Imagination Technologies
0004  * Author: Paul Burton <paul.burton@mips.com>
0005  */
0006
0007 #include <linux/binfmts.h>
0008 #include <linux/elf.h>
0009 #include <linux/export.h>
0010 #include <linux/sched.h>
0011
0012 #include <asm/cpu-features.h>
0013 #include <asm/cpu-info.h>
0014
0015 #ifdef CONFIG_MIPS_FP_SUPPORT
0016
0017 /* Whether to accept legacy-NaN and 2008-NaN user binaries.  */
0018 bool mips_use_nan_legacy;
0019 bool mips_use_nan_2008;
0020
0021 /* FPU modes */
0022 enum {
0023     FP_FRE,
0024     FP_FR0,
0025     FP_FR1,
0026 };
0027
0028 /**
0029  * struct mode_req - ABI FPU mode requirements
0030  * @single: The program being loaded needs an FPU but it will only issue
0031  *      single precision instructions meaning that it can execute in
0032  *      either FR0 or FR1.
0033  * @soft:   The soft(-float) requirement means that the program being
0034  *      loaded needs has no FPU dependency at all (i.e. it has no
0035  *      FPU instructions).
0036  * @fr1:    The program being loaded depends on FPU being in FR=1 mode.
0037  * @frdefault:  The program being loaded depends on the default FPU mode.
0038  *      That is FR0 for O32 and FR1 for N32/N64.
0039  * @fre:    The program being loaded depends on FPU with FRE=1. This mode is
0040  *      a bridge which uses FR=1 whilst still being able to maintain
0041  *      full compatibility with pre-existing code using the O32 FP32
0042  *      ABI.
0043  *
0044  * More information about the FP ABIs can be found here:
0045  *
0046  * https://dmz-portal.mips.com/wiki/MIPS_O32_ABI_-_FR0_and_FR1_Interlinking#10.4.1._Basic_mode_set-up
0047  *
0048  */
0049
0050 struct mode_req {
0051     bool single;
0052     bool soft;
0053     bool fr1;
0054     bool frdefault;
0055     bool fre;
0056 };
0057
0058 static const struct mode_req fpu_reqs[] = {
0059     [MIPS_ABI_FP_ANY]    = { true,  true,  true,  true,  true  },
0060     [MIPS_ABI_FP_DOUBLE] = { false, false, false, true,  true  },
0061     [MIPS_ABI_FP_SINGLE] = { true,  false, false, false, false },
0062     [MIPS_ABI_FP_SOFT]   = { false, true,  false, false, false },
0063     [MIPS_ABI_FP_OLD_64] = { false, false, false, false, false },
0064     [MIPS_ABI_FP_XX]     = { false, false, true,  true,  true  },
0065     [MIPS_ABI_FP_64]     = { false, false, true,  false, false },
0066     [MIPS_ABI_FP_64A]    = { false, false, true,  false, true  }
0067 };
0068
0069 /*
0070  * Mode requirements when .MIPS.abiflags is not present in the ELF.
0071  * Not present means that everything is acceptable except FR1.
0072  */
0073 static struct mode_req none_req = { true, true, false, true, true };
0074
0075 int arch_elf_pt_proc(void *_ehdr, void *_phdr, struct file *elf,
0076              bool is_interp, struct arch_elf_state *state)
0077 {
0078     union {
0079         struct elf32_hdr e32;
0080         struct elf64_hdr e64;
0081     } *ehdr = _ehdr;
0082     struct elf32_phdr *phdr32 = _phdr;
0083     struct elf64_phdr *phdr64 = _phdr;
0084     struct mips_elf_abiflags_v0 abiflags;
0085     bool elf32;
0086     u32 flags;
0087     int ret;
0088     loff_t pos;
0089
0090     elf32 = ehdr->e32.e_ident[EI_CLASS] == ELFCLASS32;
0091     flags = elf32 ? ehdr->e32.e_flags : ehdr->e64.e_flags;
0092
0093     /* Let's see if this is an O32 ELF */
0094     if (elf32) {
0095         if (flags & EF_MIPS_FP64) {
0096             /*
0097              * Set MIPS_ABI_FP_OLD_64 for EF_MIPS_FP64. We will override it
0098              * later if needed
0099              */
0100             if (is_interp)
0101                 state->interp_fp_abi = MIPS_ABI_FP_OLD_64;
0102             else
0103                 state->fp_abi = MIPS_ABI_FP_OLD_64;
0104         }
0105         if (phdr32->p_type != PT_MIPS_ABIFLAGS)
0106             return 0;
0107
0108         if (phdr32->p_filesz < sizeof(abiflags))
0109             return -EINVAL;
0110         pos = phdr32->p_offset;
0111     } else {
0112         if (phdr64->p_type != PT_MIPS_ABIFLAGS)
0113             return 0;
0114         if (phdr64->p_filesz < sizeof(abiflags))
0115             return -EINVAL;
0116         pos = phdr64->p_offset;
0117     }
0118
0119     ret = kernel_read(elf, &abiflags, sizeof(abiflags), &pos);
0120     if (ret < 0)
0121         return ret;
0122     if (ret != sizeof(abiflags))
0123         return -EIO;
0124
0125     /* Record the required FP ABIs for use by mips_check_elf */
0126     if (is_interp)
0127         state->interp_fp_abi = abiflags.fp_abi;
0128     else
0129         state->fp_abi = abiflags.fp_abi;
0130
0131     return 0;
0132 }
0133
0134 int arch_check_elf(void *_ehdr, bool has_interpreter, void *_interp_ehdr,
0135            struct arch_elf_state *state)
0136 {
0137     union {
0138         struct elf32_hdr e32;
0139         struct elf64_hdr e64;
0140     } *ehdr = _ehdr;
0141     union {
0142         struct elf32_hdr e32;
0143         struct elf64_hdr e64;
0144     } *iehdr = _interp_ehdr;
0145     struct mode_req prog_req, interp_req;
0146     int fp_abi, interp_fp_abi, abi0, abi1, max_abi;
0147     bool elf32;
0148     u32 flags;
0149
0150     elf32 = ehdr->e32.e_ident[EI_CLASS] == ELFCLASS32;
0151     flags = elf32 ? ehdr->e32.e_flags : ehdr->e64.e_flags;
0152
0153     /*
0154      * Determine the NaN personality, reject the binary if not allowed.
0155      * Also ensure that any interpreter matches the executable.
0156      */
0157     if (flags & EF_MIPS_NAN2008) {
0158         if (mips_use_nan_2008)
0159             state->nan_2008 = 1;
0160         else
0161             return -ENOEXEC;
0162     } else {
0163         if (mips_use_nan_legacy)
0164             state->nan_2008 = 0;
0165         else
0166             return -ENOEXEC;
0167     }
0168     if (has_interpreter) {
0169         bool ielf32;
0170         u32 iflags;
0171
0172         ielf32 = iehdr->e32.e_ident[EI_CLASS] == ELFCLASS32;
0173         iflags = ielf32 ? iehdr->e32.e_flags : iehdr->e64.e_flags;
0174
0175         if ((flags ^ iflags) & EF_MIPS_NAN2008)
0176             return -ELIBBAD;
0177     }
0178
0179     if (!IS_ENABLED(CONFIG_MIPS_O32_FP64_SUPPORT))
0180         return 0;
0181
0182     fp_abi = state->fp_abi;
0183
0184     if (has_interpreter) {
0185         interp_fp_abi = state->interp_fp_abi;
0186
0187         abi0 = min(fp_abi, interp_fp_abi);
0188         abi1 = max(fp_abi, interp_fp_abi);
0189     } else {
0190         abi0 = abi1 = fp_abi;
0191     }
0192
0193     if (elf32 && !(flags & EF_MIPS_ABI2)) {
0194         /* Default to a mode capable of running code expecting FR=0 */
0195         state->overall_fp_mode = cpu_has_mips_r6 ? FP_FRE : FP_FR0;
0196
0197         /* Allow all ABIs we know about */
0198         max_abi = MIPS_ABI_FP_64A;
0199     } else {
0200         /* MIPS64 code always uses FR=1, thus the default is easy */
0201         state->overall_fp_mode = FP_FR1;
0202
0203         /* Disallow access to the various FPXX & FP64 ABIs */
0204         max_abi = MIPS_ABI_FP_SOFT;
0205     }
0206
0207     if ((abi0 > max_abi && abi0 != MIPS_ABI_FP_UNKNOWN) ||
0208         (abi1 > max_abi && abi1 != MIPS_ABI_FP_UNKNOWN))
0209         return -ELIBBAD;
0210
0211     /* It's time to determine the FPU mode requirements */
0212     prog_req = (abi0 == MIPS_ABI_FP_UNKNOWN) ? none_req : fpu_reqs[abi0];
0213     interp_req = (abi1 == MIPS_ABI_FP_UNKNOWN) ? none_req : fpu_reqs[abi1];
0214
0215     /*
0216      * Check whether the program's and interp's ABIs have a matching FPU
0217      * mode requirement.
0218      */
0219     prog_req.single = interp_req.single && prog_req.single;
0220     prog_req.soft = interp_req.soft && prog_req.soft;
0221     prog_req.fr1 = interp_req.fr1 && prog_req.fr1;
0222     prog_req.frdefault = interp_req.frdefault && prog_req.frdefault;
0223     prog_req.fre = interp_req.fre && prog_req.fre;
0224
0225     /*
0226      * Determine the desired FPU mode
0227      *
0228      * Decision making:
0229      *
0230      * - We want FR_FRE if FRE=1 and both FR=1 and FR=0 are false. This
0231      *   means that we have a combination of program and interpreter
0232      *   that inherently require the hybrid FP mode.
0233      * - If FR1 and FRDEFAULT is true, that means we hit the any-abi or
0234      *   fpxx case. This is because, in any-ABI (or no-ABI) we have no FPU
0235      *   instructions so we don't care about the mode. We will simply use
0236      *   the one preferred by the hardware. In fpxx case, that ABI can
0237      *   handle both FR=1 and FR=0, so, again, we simply choose the one
0238      *   preferred by the hardware. Next, if we only use single-precision
0239      *   FPU instructions, and the default ABI FPU mode is not good
0240      *   (ie single + any ABI combination), we set again the FPU mode to the
0241      *   one is preferred by the hardware. Next, if we know that the code
0242      *   will only use single-precision instructions, shown by single being
0243      *   true but frdefault being false, then we again set the FPU mode to
0244      *   the one that is preferred by the hardware.
0245      * - We want FP_FR1 if that's the only matching mode and the default one
0246      *   is not good.
0247      * - Return with -ELIBADD if we can't find a matching FPU mode.
0248      */
0249     if (prog_req.fre && !prog_req.frdefault && !prog_req.fr1)
0250         state->overall_fp_mode = FP_FRE;
0251     else if ((prog_req.fr1 && prog_req.frdefault) ||
0252          (prog_req.single && !prog_req.frdefault))
0253         /* Make sure 64-bit MIPS III/IV/64R1 will not pick FR1 */
0254         state->overall_fp_mode = ((raw_current_cpu_data.fpu_id & MIPS_FPIR_F64) &&
0255                       cpu_has_mips_r2_r6) ?
0256                       FP_FR1 : FP_FR0;
0257     else if (prog_req.fr1)
0258         state->overall_fp_mode = FP_FR1;
0259     else  if (!prog_req.fre && !prog_req.frdefault &&
0260           !prog_req.fr1 && !prog_req.single && !prog_req.soft)
0261         return -ELIBBAD;
0262
0263     return 0;
0264 }
0265
0266 static inline void set_thread_fp_mode(int hybrid, int regs32)
0267 {
0268     if (hybrid)
0269         set_thread_flag(TIF_HYBRID_FPREGS);
0270     else
0271         clear_thread_flag(TIF_HYBRID_FPREGS);
0272     if (regs32)
0273         set_thread_flag(TIF_32BIT_FPREGS);
0274     else
0275         clear_thread_flag(TIF_32BIT_FPREGS);
0276 }
0277
0278 void mips_set_personality_fp(struct arch_elf_state *state)
0279 {
0280     /*
0281      * This function is only ever called for O32 ELFs so we should
0282      * not be worried about N32/N64 binaries.
0283      */
0284
0285     if (!IS_ENABLED(CONFIG_MIPS_O32_FP64_SUPPORT))
0286         return;
0287
0288     switch (state->overall_fp_mode) {
0289     case FP_FRE:
0290         set_thread_fp_mode(1, 0);
0291         break;
0292     case FP_FR0:
0293         set_thread_fp_mode(0, 1);
0294         break;
0295     case FP_FR1:
0296         set_thread_fp_mode(0, 0);
0297         break;
0298     default:
0299         BUG();
0300     }
0301 }
0302
0303 /*
0304  * Select the IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode
0305  * in FCSR according to the ELF NaN personality.
0306  */
0307 void mips_set_personality_nan(struct arch_elf_state *state)
0308 {
0309     struct cpuinfo_mips *c = &boot_cpu_data;
0310     struct task_struct *t = current;
0311
0312     t->thread.fpu.fcr31 = c->fpu_csr31;
0313     switch (state->nan_2008) {
0314     case 0:
0315         break;
0316     case 1:
0317         if (!(c->fpu_msk31 & FPU_CSR_NAN2008))
0318             t->thread.fpu.fcr31 |= FPU_CSR_NAN2008;
0319         if (!(c->fpu_msk31 & FPU_CSR_ABS2008))
0320             t->thread.fpu.fcr31 |= FPU_CSR_ABS2008;
0321         break;
0322     default:
0323         BUG();
0324     }
0325 }
0326
0327 #endif /* CONFIG_MIPS_FP_SUPPORT */
0328
0329 int mips_elf_read_implies_exec(void *elf_ex, int exstack)
0330 {
0331     /*
0332      * Set READ_IMPLIES_EXEC only on non-NX systems that
0333      * do not request a specific state via PT_GNU_STACK.
0334      */
0335     return (!cpu_has_rixi && exstack == EXSTACK_DEFAULT);
0336 }
0337 EXPORT_SYMBOL(mips_elf_read_implies_exec);