mips/kernel/csrc-sb1250.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (C) 2000, 2001 Broadcom Corporation
0004  */
0005 #include <linux/clocksource.h>
0006 #include <linux/sched_clock.h>
0007
0008 #include <asm/addrspace.h>
0009 #include <asm/io.h>
0010 #include <asm/time.h>
0011
0012 #include <asm/sibyte/sb1250.h>
0013 #include <asm/sibyte/sb1250_regs.h>
0014 #include <asm/sibyte/sb1250_int.h>
0015 #include <asm/sibyte/sb1250_scd.h>
0016
0017 #define SB1250_HPT_NUM      3
0018 #define SB1250_HPT_VALUE    M_SCD_TIMER_CNT /* max value */
0019
0020 /*
0021  * The HPT is free running from SB1250_HPT_VALUE down to 0 then starts over
0022  * again.
0023  */
0024 static inline u64 sb1250_hpt_get_cycles(void)
0025 {
0026     unsigned int count;
0027     void __iomem *addr;
0028
0029     addr = IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CNT));
0030     count = G_SCD_TIMER_CNT(__raw_readq(addr));
0031
0032     return SB1250_HPT_VALUE - count;
0033 }
0034
0035 static u64 sb1250_hpt_read(struct clocksource *cs)
0036 {
0037     return sb1250_hpt_get_cycles();
0038 }
0039
0040 struct clocksource bcm1250_clocksource = {
0041     .name   = "bcm1250-counter-3",
0042     .rating = 200,
0043     .read   = sb1250_hpt_read,
0044     .mask   = CLOCKSOURCE_MASK(23),
0045     .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
0046 };
0047
0048 static u64 notrace sb1250_read_sched_clock(void)
0049 {
0050     return sb1250_hpt_get_cycles();
0051 }
0052
0053 void __init sb1250_clocksource_init(void)
0054 {
0055     struct clocksource *cs = &bcm1250_clocksource;
0056
0057     /* Setup hpt using timer #3 but do not enable irq for it */
0058     __raw_writeq(0,
0059              IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM,
0060                          R_SCD_TIMER_CFG)));
0061     __raw_writeq(SB1250_HPT_VALUE,
0062              IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM,
0063                          R_SCD_TIMER_INIT)));
0064     __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
0065              IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM,
0066                          R_SCD_TIMER_CFG)));
0067
0068     clocksource_register_hz(cs, V_SCD_TIMER_FREQ);
0069
0070     sched_clock_register(sb1250_read_sched_clock, 23, V_SCD_TIMER_FREQ);
0071 }