mips/kernel/cevt-sb1250.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (C) 2000, 2001 Broadcom Corporation
0004  */
0005 #include <linux/clockchips.h>
0006 #include <linux/interrupt.h>
0007 #include <linux/irq.h>
0008 #include <linux/percpu.h>
0009 #include <linux/smp.h>
0010
0011 #include <asm/addrspace.h>
0012 #include <asm/io.h>
0013 #include <asm/time.h>
0014
0015 #include <asm/sibyte/sb1250.h>
0016 #include <asm/sibyte/sb1250_regs.h>
0017 #include <asm/sibyte/sb1250_int.h>
0018 #include <asm/sibyte/sb1250_scd.h>
0019
0020 #define IMR_IP2_VAL K_INT_MAP_I0
0021 #define IMR_IP3_VAL K_INT_MAP_I1
0022 #define IMR_IP4_VAL K_INT_MAP_I2
0023
0024 /*
0025  * The general purpose timer ticks at 1MHz independent if
0026  * the rest of the system
0027  */
0028
0029 static int sibyte_shutdown(struct clock_event_device *evt)
0030 {
0031     void __iomem *cfg;
0032
0033     cfg = IOADDR(A_SCD_TIMER_REGISTER(smp_processor_id(), R_SCD_TIMER_CFG));
0034
0035     /* Stop the timer until we actually program a shot */
0036     __raw_writeq(0, cfg);
0037
0038     return 0;
0039 }
0040
0041 static int sibyte_set_periodic(struct clock_event_device *evt)
0042 {
0043     unsigned int cpu = smp_processor_id();
0044     void __iomem *cfg, *init;
0045
0046     cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
0047     init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT));
0048
0049     __raw_writeq(0, cfg);
0050     __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, init);
0051     __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, cfg);
0052
0053     return 0;
0054 }
0055
0056 static int sibyte_next_event(unsigned long delta, struct clock_event_device *cd)
0057 {
0058     unsigned int cpu = smp_processor_id();
0059     void __iomem *cfg, *init;
0060
0061     cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
0062     init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT));
0063
0064     __raw_writeq(0, cfg);
0065     __raw_writeq(delta - 1, init);
0066     __raw_writeq(M_SCD_TIMER_ENABLE, cfg);
0067
0068     return 0;
0069 }
0070
0071 static irqreturn_t sibyte_counter_handler(int irq, void *dev_id)
0072 {
0073     unsigned int cpu = smp_processor_id();
0074     struct clock_event_device *cd = dev_id;
0075     void __iomem *cfg;
0076     unsigned long tmode;
0077
0078     if (clockevent_state_periodic(cd))
0079         tmode = M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS;
0080     else
0081         tmode = 0;
0082
0083     /* ACK interrupt */
0084     cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
0085     ____raw_writeq(tmode, cfg);
0086
0087     cd->event_handler(cd);
0088
0089     return IRQ_HANDLED;
0090 }
0091
0092 static DEFINE_PER_CPU(struct clock_event_device, sibyte_hpt_clockevent);
0093 static DEFINE_PER_CPU(char [18], sibyte_hpt_name);
0094
0095 void sb1250_clockevent_init(void)
0096 {
0097     unsigned int cpu = smp_processor_id();
0098     unsigned int irq = K_INT_TIMER_0 + cpu;
0099     struct clock_event_device *cd = &per_cpu(sibyte_hpt_clockevent, cpu);
0100     unsigned char *name = per_cpu(sibyte_hpt_name, cpu);
0101     unsigned long flags = IRQF_PERCPU | IRQF_TIMER;
0102
0103     /* Only have 4 general purpose timers, and we use last one as hpt */
0104     BUG_ON(cpu > 2);
0105
0106     sprintf(name, "sb1250-counter-%d", cpu);
0107     cd->name        = name;
0108     cd->features        = CLOCK_EVT_FEAT_PERIODIC |
0109                   CLOCK_EVT_FEAT_ONESHOT;
0110     clockevent_set_clock(cd, V_SCD_TIMER_FREQ);
0111     cd->max_delta_ns    = clockevent_delta2ns(0x7fffff, cd);
0112     cd->max_delta_ticks = 0x7fffff;
0113     cd->min_delta_ns    = clockevent_delta2ns(2, cd);
0114     cd->min_delta_ticks = 2;
0115     cd->rating      = 200;
0116     cd->irq         = irq;
0117     cd->cpumask     = cpumask_of(cpu);
0118     cd->set_next_event  = sibyte_next_event;
0119     cd->set_state_shutdown  = sibyte_shutdown;
0120     cd->set_state_periodic  = sibyte_set_periodic;
0121     cd->set_state_oneshot   = sibyte_shutdown;
0122     clockevents_register_device(cd);
0123
0124     sb1250_mask_irq(cpu, irq);
0125
0126     /*
0127      * Map the timer interrupt to IP[4] of this cpu
0128      */
0129     __raw_writeq(IMR_IP4_VAL,
0130              IOADDR(A_IMR_REGISTER(cpu, R_IMR_INTERRUPT_MAP_BASE) +
0131                 (irq << 3)));
0132
0133     sb1250_unmask_irq(cpu, irq);
0134
0135     irq_set_affinity(irq, cpumask_of(cpu));
0136     if (request_irq(irq, sibyte_counter_handler, flags, name, cd))
0137         pr_err("Failed to request irq %d (%s)\n", irq, name);
0138 }