mips/kernel/cevt-gt641xx.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  *  GT641xx clockevent routines.
0004  *
0005  *  Copyright (C) 2007  Yoichi Yuasa <yuasa@linux-mips.org>
0006  */
0007 #include <linux/clockchips.h>
0008 #include <linux/init.h>
0009 #include <linux/interrupt.h>
0010 #include <linux/spinlock.h>
0011 #include <linux/irq.h>
0012
0013 #include <asm/gt64120.h>
0014 #include <asm/time.h>
0015
0016 static DEFINE_RAW_SPINLOCK(gt641xx_timer_lock);
0017 static unsigned int gt641xx_base_clock;
0018
0019 void gt641xx_set_base_clock(unsigned int clock)
0020 {
0021     gt641xx_base_clock = clock;
0022 }
0023
0024 int gt641xx_timer0_state(void)
0025 {
0026     if (GT_READ(GT_TC0_OFS))
0027         return 0;
0028
0029     GT_WRITE(GT_TC0_OFS, gt641xx_base_clock / HZ);
0030     GT_WRITE(GT_TC_CONTROL_OFS, GT_TC_CONTROL_ENTC0_MSK);
0031
0032     return 1;
0033 }
0034
0035 static int gt641xx_timer0_set_next_event(unsigned long delta,
0036                      struct clock_event_device *evt)
0037 {
0038     u32 ctrl;
0039
0040     raw_spin_lock(&gt641xx_timer_lock);
0041
0042     ctrl = GT_READ(GT_TC_CONTROL_OFS);
0043     ctrl &= ~(GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK);
0044     ctrl |= GT_TC_CONTROL_ENTC0_MSK;
0045
0046     GT_WRITE(GT_TC0_OFS, delta);
0047     GT_WRITE(GT_TC_CONTROL_OFS, ctrl);
0048
0049     raw_spin_unlock(&gt641xx_timer_lock);
0050
0051     return 0;
0052 }
0053
0054 static int gt641xx_timer0_shutdown(struct clock_event_device *evt)
0055 {
0056     u32 ctrl;
0057
0058     raw_spin_lock(&gt641xx_timer_lock);
0059
0060     ctrl = GT_READ(GT_TC_CONTROL_OFS);
0061     ctrl &= ~(GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK);
0062     GT_WRITE(GT_TC_CONTROL_OFS, ctrl);
0063
0064     raw_spin_unlock(&gt641xx_timer_lock);
0065     return 0;
0066 }
0067
0068 static int gt641xx_timer0_set_oneshot(struct clock_event_device *evt)
0069 {
0070     u32 ctrl;
0071
0072     raw_spin_lock(&gt641xx_timer_lock);
0073
0074     ctrl = GT_READ(GT_TC_CONTROL_OFS);
0075     ctrl &= ~GT_TC_CONTROL_SELTC0_MSK;
0076     ctrl |= GT_TC_CONTROL_ENTC0_MSK;
0077     GT_WRITE(GT_TC_CONTROL_OFS, ctrl);
0078
0079     raw_spin_unlock(&gt641xx_timer_lock);
0080     return 0;
0081 }
0082
0083 static int gt641xx_timer0_set_periodic(struct clock_event_device *evt)
0084 {
0085     u32 ctrl;
0086
0087     raw_spin_lock(&gt641xx_timer_lock);
0088
0089     ctrl = GT_READ(GT_TC_CONTROL_OFS);
0090     ctrl |= GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK;
0091     GT_WRITE(GT_TC_CONTROL_OFS, ctrl);
0092
0093     raw_spin_unlock(&gt641xx_timer_lock);
0094     return 0;
0095 }
0096
0097 static void gt641xx_timer0_event_handler(struct clock_event_device *dev)
0098 {
0099 }
0100
0101 static struct clock_event_device gt641xx_timer0_clockevent = {
0102     .name           = "gt641xx-timer0",
0103     .features       = CLOCK_EVT_FEAT_PERIODIC |
0104                   CLOCK_EVT_FEAT_ONESHOT,
0105     .irq            = GT641XX_TIMER0_IRQ,
0106     .set_next_event     = gt641xx_timer0_set_next_event,
0107     .set_state_shutdown = gt641xx_timer0_shutdown,
0108     .set_state_periodic = gt641xx_timer0_set_periodic,
0109     .set_state_oneshot  = gt641xx_timer0_set_oneshot,
0110     .tick_resume        = gt641xx_timer0_shutdown,
0111     .event_handler      = gt641xx_timer0_event_handler,
0112 };
0113
0114 static irqreturn_t gt641xx_timer0_interrupt(int irq, void *dev_id)
0115 {
0116     struct clock_event_device *cd = &gt641xx_timer0_clockevent;
0117
0118     cd->event_handler(cd);
0119
0120     return IRQ_HANDLED;
0121 }
0122
0123 static int __init gt641xx_timer0_clockevent_init(void)
0124 {
0125     struct clock_event_device *cd;
0126
0127     if (!gt641xx_base_clock)
0128         return 0;
0129
0130     GT_WRITE(GT_TC0_OFS, gt641xx_base_clock / HZ);
0131
0132     cd = &gt641xx_timer0_clockevent;
0133     cd->rating = 200 + gt641xx_base_clock / 10000000;
0134     clockevent_set_clock(cd, gt641xx_base_clock);
0135     cd->max_delta_ns = clockevent_delta2ns(0x7fffffff, cd);
0136     cd->max_delta_ticks = 0x7fffffff;
0137     cd->min_delta_ns = clockevent_delta2ns(0x300, cd);
0138     cd->min_delta_ticks = 0x300;
0139     cd->cpumask = cpumask_of(0);
0140
0141     clockevents_register_device(&gt641xx_timer0_clockevent);
0142
0143     return request_irq(GT641XX_TIMER0_IRQ, gt641xx_timer0_interrupt,
0144                IRQF_PERCPU | IRQF_TIMER, "gt641xx_timer0", NULL);
0145 }
0146 arch_initcall(gt641xx_timer0_clockevent_init);