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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * asm-offsets.c: Calculate pt_regs and task_struct offsets.
0004  *
0005  * Copyright (C) 1996 David S. Miller
0006  * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002, 2003 Ralf Baechle
0007  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
0008  *
0009  * Kevin Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
0010  * Copyright (C) 2000 MIPS Technologies, Inc.
0011  */
0012 #include <linux/compat.h>
0013 #include <linux/types.h>
0014 #include <linux/sched.h>
0015 #include <linux/mm.h>
0016 #include <linux/kbuild.h>
0017 #include <linux/suspend.h>
0018 #include <asm/cpu-info.h>
0019 #include <asm/pm.h>
0020 #include <asm/ptrace.h>
0021 #include <asm/processor.h>
0022 #include <asm/smp-cps.h>
0023 
0024 #include <linux/kvm_host.h>
0025 
0026 void output_ptreg_defines(void)
0027 {
0028     COMMENT("MIPS pt_regs offsets.");
0029     OFFSET(PT_R0, pt_regs, regs[0]);
0030     OFFSET(PT_R1, pt_regs, regs[1]);
0031     OFFSET(PT_R2, pt_regs, regs[2]);
0032     OFFSET(PT_R3, pt_regs, regs[3]);
0033     OFFSET(PT_R4, pt_regs, regs[4]);
0034     OFFSET(PT_R5, pt_regs, regs[5]);
0035     OFFSET(PT_R6, pt_regs, regs[6]);
0036     OFFSET(PT_R7, pt_regs, regs[7]);
0037     OFFSET(PT_R8, pt_regs, regs[8]);
0038     OFFSET(PT_R9, pt_regs, regs[9]);
0039     OFFSET(PT_R10, pt_regs, regs[10]);
0040     OFFSET(PT_R11, pt_regs, regs[11]);
0041     OFFSET(PT_R12, pt_regs, regs[12]);
0042     OFFSET(PT_R13, pt_regs, regs[13]);
0043     OFFSET(PT_R14, pt_regs, regs[14]);
0044     OFFSET(PT_R15, pt_regs, regs[15]);
0045     OFFSET(PT_R16, pt_regs, regs[16]);
0046     OFFSET(PT_R17, pt_regs, regs[17]);
0047     OFFSET(PT_R18, pt_regs, regs[18]);
0048     OFFSET(PT_R19, pt_regs, regs[19]);
0049     OFFSET(PT_R20, pt_regs, regs[20]);
0050     OFFSET(PT_R21, pt_regs, regs[21]);
0051     OFFSET(PT_R22, pt_regs, regs[22]);
0052     OFFSET(PT_R23, pt_regs, regs[23]);
0053     OFFSET(PT_R24, pt_regs, regs[24]);
0054     OFFSET(PT_R25, pt_regs, regs[25]);
0055     OFFSET(PT_R26, pt_regs, regs[26]);
0056     OFFSET(PT_R27, pt_regs, regs[27]);
0057     OFFSET(PT_R28, pt_regs, regs[28]);
0058     OFFSET(PT_R29, pt_regs, regs[29]);
0059     OFFSET(PT_R30, pt_regs, regs[30]);
0060     OFFSET(PT_R31, pt_regs, regs[31]);
0061     OFFSET(PT_LO, pt_regs, lo);
0062     OFFSET(PT_HI, pt_regs, hi);
0063 #ifdef CONFIG_CPU_HAS_SMARTMIPS
0064     OFFSET(PT_ACX, pt_regs, acx);
0065 #endif
0066     OFFSET(PT_EPC, pt_regs, cp0_epc);
0067     OFFSET(PT_BVADDR, pt_regs, cp0_badvaddr);
0068     OFFSET(PT_STATUS, pt_regs, cp0_status);
0069     OFFSET(PT_CAUSE, pt_regs, cp0_cause);
0070 #ifdef CONFIG_CPU_CAVIUM_OCTEON
0071     OFFSET(PT_MPL, pt_regs, mpl);
0072     OFFSET(PT_MTP, pt_regs, mtp);
0073 #endif /* CONFIG_CPU_CAVIUM_OCTEON */
0074     DEFINE(PT_SIZE, sizeof(struct pt_regs));
0075     BLANK();
0076 }
0077 
0078 void output_task_defines(void)
0079 {
0080     COMMENT("MIPS task_struct offsets.");
0081     OFFSET(TASK_THREAD_INFO, task_struct, stack);
0082     OFFSET(TASK_FLAGS, task_struct, flags);
0083     OFFSET(TASK_MM, task_struct, mm);
0084     OFFSET(TASK_PID, task_struct, pid);
0085 #if defined(CONFIG_STACKPROTECTOR)
0086     OFFSET(TASK_STACK_CANARY, task_struct, stack_canary);
0087 #endif
0088     DEFINE(TASK_STRUCT_SIZE, sizeof(struct task_struct));
0089     BLANK();
0090 }
0091 
0092 void output_thread_info_defines(void)
0093 {
0094     COMMENT("MIPS thread_info offsets.");
0095     OFFSET(TI_TASK, thread_info, task);
0096     OFFSET(TI_FLAGS, thread_info, flags);
0097     OFFSET(TI_TP_VALUE, thread_info, tp_value);
0098     OFFSET(TI_CPU, thread_info, cpu);
0099     OFFSET(TI_PRE_COUNT, thread_info, preempt_count);
0100     OFFSET(TI_REGS, thread_info, regs);
0101     DEFINE(_THREAD_SIZE, THREAD_SIZE);
0102     DEFINE(_THREAD_MASK, THREAD_MASK);
0103     DEFINE(_IRQ_STACK_SIZE, IRQ_STACK_SIZE);
0104     DEFINE(_IRQ_STACK_START, IRQ_STACK_START);
0105     BLANK();
0106 }
0107 
0108 void output_thread_defines(void)
0109 {
0110     COMMENT("MIPS specific thread_struct offsets.");
0111     OFFSET(THREAD_REG16, task_struct, thread.reg16);
0112     OFFSET(THREAD_REG17, task_struct, thread.reg17);
0113     OFFSET(THREAD_REG18, task_struct, thread.reg18);
0114     OFFSET(THREAD_REG19, task_struct, thread.reg19);
0115     OFFSET(THREAD_REG20, task_struct, thread.reg20);
0116     OFFSET(THREAD_REG21, task_struct, thread.reg21);
0117     OFFSET(THREAD_REG22, task_struct, thread.reg22);
0118     OFFSET(THREAD_REG23, task_struct, thread.reg23);
0119     OFFSET(THREAD_REG29, task_struct, thread.reg29);
0120     OFFSET(THREAD_REG30, task_struct, thread.reg30);
0121     OFFSET(THREAD_REG31, task_struct, thread.reg31);
0122     OFFSET(THREAD_STATUS, task_struct,
0123            thread.cp0_status);
0124 
0125     OFFSET(THREAD_BVADDR, task_struct, \
0126            thread.cp0_badvaddr);
0127     OFFSET(THREAD_BUADDR, task_struct, \
0128            thread.cp0_baduaddr);
0129     OFFSET(THREAD_ECODE, task_struct, \
0130            thread.error_code);
0131     OFFSET(THREAD_TRAPNO, task_struct, thread.trap_nr);
0132     BLANK();
0133 }
0134 
0135 #ifdef CONFIG_MIPS_FP_SUPPORT
0136 void output_thread_fpu_defines(void)
0137 {
0138     OFFSET(THREAD_FPU, task_struct, thread.fpu);
0139 
0140     OFFSET(THREAD_FPR0, task_struct, thread.fpu.fpr[0]);
0141     OFFSET(THREAD_FPR1, task_struct, thread.fpu.fpr[1]);
0142     OFFSET(THREAD_FPR2, task_struct, thread.fpu.fpr[2]);
0143     OFFSET(THREAD_FPR3, task_struct, thread.fpu.fpr[3]);
0144     OFFSET(THREAD_FPR4, task_struct, thread.fpu.fpr[4]);
0145     OFFSET(THREAD_FPR5, task_struct, thread.fpu.fpr[5]);
0146     OFFSET(THREAD_FPR6, task_struct, thread.fpu.fpr[6]);
0147     OFFSET(THREAD_FPR7, task_struct, thread.fpu.fpr[7]);
0148     OFFSET(THREAD_FPR8, task_struct, thread.fpu.fpr[8]);
0149     OFFSET(THREAD_FPR9, task_struct, thread.fpu.fpr[9]);
0150     OFFSET(THREAD_FPR10, task_struct, thread.fpu.fpr[10]);
0151     OFFSET(THREAD_FPR11, task_struct, thread.fpu.fpr[11]);
0152     OFFSET(THREAD_FPR12, task_struct, thread.fpu.fpr[12]);
0153     OFFSET(THREAD_FPR13, task_struct, thread.fpu.fpr[13]);
0154     OFFSET(THREAD_FPR14, task_struct, thread.fpu.fpr[14]);
0155     OFFSET(THREAD_FPR15, task_struct, thread.fpu.fpr[15]);
0156     OFFSET(THREAD_FPR16, task_struct, thread.fpu.fpr[16]);
0157     OFFSET(THREAD_FPR17, task_struct, thread.fpu.fpr[17]);
0158     OFFSET(THREAD_FPR18, task_struct, thread.fpu.fpr[18]);
0159     OFFSET(THREAD_FPR19, task_struct, thread.fpu.fpr[19]);
0160     OFFSET(THREAD_FPR20, task_struct, thread.fpu.fpr[20]);
0161     OFFSET(THREAD_FPR21, task_struct, thread.fpu.fpr[21]);
0162     OFFSET(THREAD_FPR22, task_struct, thread.fpu.fpr[22]);
0163     OFFSET(THREAD_FPR23, task_struct, thread.fpu.fpr[23]);
0164     OFFSET(THREAD_FPR24, task_struct, thread.fpu.fpr[24]);
0165     OFFSET(THREAD_FPR25, task_struct, thread.fpu.fpr[25]);
0166     OFFSET(THREAD_FPR26, task_struct, thread.fpu.fpr[26]);
0167     OFFSET(THREAD_FPR27, task_struct, thread.fpu.fpr[27]);
0168     OFFSET(THREAD_FPR28, task_struct, thread.fpu.fpr[28]);
0169     OFFSET(THREAD_FPR29, task_struct, thread.fpu.fpr[29]);
0170     OFFSET(THREAD_FPR30, task_struct, thread.fpu.fpr[30]);
0171     OFFSET(THREAD_FPR31, task_struct, thread.fpu.fpr[31]);
0172 
0173     OFFSET(THREAD_FCR31, task_struct, thread.fpu.fcr31);
0174     OFFSET(THREAD_MSA_CSR, task_struct, thread.fpu.msacsr);
0175     BLANK();
0176 }
0177 #endif
0178 
0179 void output_mm_defines(void)
0180 {
0181     COMMENT("Size of struct page");
0182     DEFINE(STRUCT_PAGE_SIZE, sizeof(struct page));
0183     BLANK();
0184     COMMENT("Linux mm_struct offsets.");
0185     OFFSET(MM_USERS, mm_struct, mm_users);
0186     OFFSET(MM_PGD, mm_struct, pgd);
0187     OFFSET(MM_CONTEXT, mm_struct, context);
0188     BLANK();
0189     DEFINE(_PGD_T_SIZE, sizeof(pgd_t));
0190     DEFINE(_PMD_T_SIZE, sizeof(pmd_t));
0191     DEFINE(_PTE_T_SIZE, sizeof(pte_t));
0192     BLANK();
0193     DEFINE(_PGD_T_LOG2, PGD_T_LOG2);
0194 #ifndef __PAGETABLE_PMD_FOLDED
0195     DEFINE(_PMD_T_LOG2, PMD_T_LOG2);
0196 #endif
0197     DEFINE(_PTE_T_LOG2, PTE_T_LOG2);
0198     BLANK();
0199     BLANK();
0200     DEFINE(_PMD_SHIFT, PMD_SHIFT);
0201     DEFINE(_PGDIR_SHIFT, PGDIR_SHIFT);
0202     BLANK();
0203     DEFINE(_PTRS_PER_PGD, PTRS_PER_PGD);
0204     DEFINE(_PTRS_PER_PMD, PTRS_PER_PMD);
0205     DEFINE(_PTRS_PER_PTE, PTRS_PER_PTE);
0206     BLANK();
0207     DEFINE(_PAGE_SHIFT, PAGE_SHIFT);
0208     DEFINE(_PAGE_SIZE, PAGE_SIZE);
0209     BLANK();
0210 }
0211 
0212 #ifdef CONFIG_32BIT
0213 void output_sc_defines(void)
0214 {
0215     COMMENT("Linux sigcontext offsets.");
0216     OFFSET(SC_REGS, sigcontext, sc_regs);
0217     OFFSET(SC_FPREGS, sigcontext, sc_fpregs);
0218     OFFSET(SC_ACX, sigcontext, sc_acx);
0219     OFFSET(SC_MDHI, sigcontext, sc_mdhi);
0220     OFFSET(SC_MDLO, sigcontext, sc_mdlo);
0221     OFFSET(SC_PC, sigcontext, sc_pc);
0222     OFFSET(SC_FPC_CSR, sigcontext, sc_fpc_csr);
0223     OFFSET(SC_FPC_EIR, sigcontext, sc_fpc_eir);
0224     OFFSET(SC_HI1, sigcontext, sc_hi1);
0225     OFFSET(SC_LO1, sigcontext, sc_lo1);
0226     OFFSET(SC_HI2, sigcontext, sc_hi2);
0227     OFFSET(SC_LO2, sigcontext, sc_lo2);
0228     OFFSET(SC_HI3, sigcontext, sc_hi3);
0229     OFFSET(SC_LO3, sigcontext, sc_lo3);
0230     BLANK();
0231 }
0232 #endif
0233 
0234 #ifdef CONFIG_64BIT
0235 void output_sc_defines(void)
0236 {
0237     COMMENT("Linux sigcontext offsets.");
0238     OFFSET(SC_REGS, sigcontext, sc_regs);
0239     OFFSET(SC_FPREGS, sigcontext, sc_fpregs);
0240     OFFSET(SC_MDHI, sigcontext, sc_mdhi);
0241     OFFSET(SC_MDLO, sigcontext, sc_mdlo);
0242     OFFSET(SC_PC, sigcontext, sc_pc);
0243     OFFSET(SC_FPC_CSR, sigcontext, sc_fpc_csr);
0244     BLANK();
0245 }
0246 #endif
0247 
0248 void output_signal_defined(void)
0249 {
0250     COMMENT("Linux signal numbers.");
0251     DEFINE(_SIGHUP, SIGHUP);
0252     DEFINE(_SIGINT, SIGINT);
0253     DEFINE(_SIGQUIT, SIGQUIT);
0254     DEFINE(_SIGILL, SIGILL);
0255     DEFINE(_SIGTRAP, SIGTRAP);
0256     DEFINE(_SIGIOT, SIGIOT);
0257     DEFINE(_SIGABRT, SIGABRT);
0258     DEFINE(_SIGEMT, SIGEMT);
0259     DEFINE(_SIGFPE, SIGFPE);
0260     DEFINE(_SIGKILL, SIGKILL);
0261     DEFINE(_SIGBUS, SIGBUS);
0262     DEFINE(_SIGSEGV, SIGSEGV);
0263     DEFINE(_SIGSYS, SIGSYS);
0264     DEFINE(_SIGPIPE, SIGPIPE);
0265     DEFINE(_SIGALRM, SIGALRM);
0266     DEFINE(_SIGTERM, SIGTERM);
0267     DEFINE(_SIGUSR1, SIGUSR1);
0268     DEFINE(_SIGUSR2, SIGUSR2);
0269     DEFINE(_SIGCHLD, SIGCHLD);
0270     DEFINE(_SIGPWR, SIGPWR);
0271     DEFINE(_SIGWINCH, SIGWINCH);
0272     DEFINE(_SIGURG, SIGURG);
0273     DEFINE(_SIGIO, SIGIO);
0274     DEFINE(_SIGSTOP, SIGSTOP);
0275     DEFINE(_SIGTSTP, SIGTSTP);
0276     DEFINE(_SIGCONT, SIGCONT);
0277     DEFINE(_SIGTTIN, SIGTTIN);
0278     DEFINE(_SIGTTOU, SIGTTOU);
0279     DEFINE(_SIGVTALRM, SIGVTALRM);
0280     DEFINE(_SIGPROF, SIGPROF);
0281     DEFINE(_SIGXCPU, SIGXCPU);
0282     DEFINE(_SIGXFSZ, SIGXFSZ);
0283     BLANK();
0284 }
0285 
0286 #ifdef CONFIG_CPU_CAVIUM_OCTEON
0287 void output_octeon_cop2_state_defines(void)
0288 {
0289     COMMENT("Octeon specific octeon_cop2_state offsets.");
0290     OFFSET(OCTEON_CP2_CRC_IV,   octeon_cop2_state, cop2_crc_iv);
0291     OFFSET(OCTEON_CP2_CRC_LENGTH,   octeon_cop2_state, cop2_crc_length);
0292     OFFSET(OCTEON_CP2_CRC_POLY, octeon_cop2_state, cop2_crc_poly);
0293     OFFSET(OCTEON_CP2_LLM_DAT,  octeon_cop2_state, cop2_llm_dat);
0294     OFFSET(OCTEON_CP2_3DES_IV,  octeon_cop2_state, cop2_3des_iv);
0295     OFFSET(OCTEON_CP2_3DES_KEY, octeon_cop2_state, cop2_3des_key);
0296     OFFSET(OCTEON_CP2_3DES_RESULT,  octeon_cop2_state, cop2_3des_result);
0297     OFFSET(OCTEON_CP2_AES_INP0, octeon_cop2_state, cop2_aes_inp0);
0298     OFFSET(OCTEON_CP2_AES_IV,   octeon_cop2_state, cop2_aes_iv);
0299     OFFSET(OCTEON_CP2_AES_KEY,  octeon_cop2_state, cop2_aes_key);
0300     OFFSET(OCTEON_CP2_AES_KEYLEN,   octeon_cop2_state, cop2_aes_keylen);
0301     OFFSET(OCTEON_CP2_AES_RESULT,   octeon_cop2_state, cop2_aes_result);
0302     OFFSET(OCTEON_CP2_GFM_MULT, octeon_cop2_state, cop2_gfm_mult);
0303     OFFSET(OCTEON_CP2_GFM_POLY, octeon_cop2_state, cop2_gfm_poly);
0304     OFFSET(OCTEON_CP2_GFM_RESULT,   octeon_cop2_state, cop2_gfm_result);
0305     OFFSET(OCTEON_CP2_HSH_DATW, octeon_cop2_state, cop2_hsh_datw);
0306     OFFSET(OCTEON_CP2_HSH_IVW,  octeon_cop2_state, cop2_hsh_ivw);
0307     OFFSET(OCTEON_CP2_SHA3,     octeon_cop2_state, cop2_sha3);
0308     OFFSET(THREAD_CP2,  task_struct, thread.cp2);
0309     OFFSET(THREAD_CVMSEG,   task_struct, thread.cvmseg.cvmseg);
0310     BLANK();
0311 }
0312 #endif
0313 
0314 #ifdef CONFIG_HIBERNATION
0315 void output_pbe_defines(void)
0316 {
0317     COMMENT(" Linux struct pbe offsets. ");
0318     OFFSET(PBE_ADDRESS, pbe, address);
0319     OFFSET(PBE_ORIG_ADDRESS, pbe, orig_address);
0320     OFFSET(PBE_NEXT, pbe, next);
0321     DEFINE(PBE_SIZE, sizeof(struct pbe));
0322     BLANK();
0323 }
0324 #endif
0325 
0326 #ifdef CONFIG_CPU_PM
0327 void output_pm_defines(void)
0328 {
0329     COMMENT(" PM offsets. ");
0330 #ifdef CONFIG_EVA
0331     OFFSET(SSS_SEGCTL0, mips_static_suspend_state, segctl[0]);
0332     OFFSET(SSS_SEGCTL1, mips_static_suspend_state, segctl[1]);
0333     OFFSET(SSS_SEGCTL2, mips_static_suspend_state, segctl[2]);
0334 #endif
0335     OFFSET(SSS_SP,      mips_static_suspend_state, sp);
0336     BLANK();
0337 }
0338 #endif
0339 
0340 #ifdef CONFIG_MIPS_FP_SUPPORT
0341 void output_kvm_defines(void)
0342 {
0343     COMMENT(" KVM/MIPS Specific offsets. ");
0344 
0345     OFFSET(VCPU_FPR0, kvm_vcpu_arch, fpu.fpr[0]);
0346     OFFSET(VCPU_FPR1, kvm_vcpu_arch, fpu.fpr[1]);
0347     OFFSET(VCPU_FPR2, kvm_vcpu_arch, fpu.fpr[2]);
0348     OFFSET(VCPU_FPR3, kvm_vcpu_arch, fpu.fpr[3]);
0349     OFFSET(VCPU_FPR4, kvm_vcpu_arch, fpu.fpr[4]);
0350     OFFSET(VCPU_FPR5, kvm_vcpu_arch, fpu.fpr[5]);
0351     OFFSET(VCPU_FPR6, kvm_vcpu_arch, fpu.fpr[6]);
0352     OFFSET(VCPU_FPR7, kvm_vcpu_arch, fpu.fpr[7]);
0353     OFFSET(VCPU_FPR8, kvm_vcpu_arch, fpu.fpr[8]);
0354     OFFSET(VCPU_FPR9, kvm_vcpu_arch, fpu.fpr[9]);
0355     OFFSET(VCPU_FPR10, kvm_vcpu_arch, fpu.fpr[10]);
0356     OFFSET(VCPU_FPR11, kvm_vcpu_arch, fpu.fpr[11]);
0357     OFFSET(VCPU_FPR12, kvm_vcpu_arch, fpu.fpr[12]);
0358     OFFSET(VCPU_FPR13, kvm_vcpu_arch, fpu.fpr[13]);
0359     OFFSET(VCPU_FPR14, kvm_vcpu_arch, fpu.fpr[14]);
0360     OFFSET(VCPU_FPR15, kvm_vcpu_arch, fpu.fpr[15]);
0361     OFFSET(VCPU_FPR16, kvm_vcpu_arch, fpu.fpr[16]);
0362     OFFSET(VCPU_FPR17, kvm_vcpu_arch, fpu.fpr[17]);
0363     OFFSET(VCPU_FPR18, kvm_vcpu_arch, fpu.fpr[18]);
0364     OFFSET(VCPU_FPR19, kvm_vcpu_arch, fpu.fpr[19]);
0365     OFFSET(VCPU_FPR20, kvm_vcpu_arch, fpu.fpr[20]);
0366     OFFSET(VCPU_FPR21, kvm_vcpu_arch, fpu.fpr[21]);
0367     OFFSET(VCPU_FPR22, kvm_vcpu_arch, fpu.fpr[22]);
0368     OFFSET(VCPU_FPR23, kvm_vcpu_arch, fpu.fpr[23]);
0369     OFFSET(VCPU_FPR24, kvm_vcpu_arch, fpu.fpr[24]);
0370     OFFSET(VCPU_FPR25, kvm_vcpu_arch, fpu.fpr[25]);
0371     OFFSET(VCPU_FPR26, kvm_vcpu_arch, fpu.fpr[26]);
0372     OFFSET(VCPU_FPR27, kvm_vcpu_arch, fpu.fpr[27]);
0373     OFFSET(VCPU_FPR28, kvm_vcpu_arch, fpu.fpr[28]);
0374     OFFSET(VCPU_FPR29, kvm_vcpu_arch, fpu.fpr[29]);
0375     OFFSET(VCPU_FPR30, kvm_vcpu_arch, fpu.fpr[30]);
0376     OFFSET(VCPU_FPR31, kvm_vcpu_arch, fpu.fpr[31]);
0377 
0378     OFFSET(VCPU_FCR31, kvm_vcpu_arch, fpu.fcr31);
0379     OFFSET(VCPU_MSA_CSR, kvm_vcpu_arch, fpu.msacsr);
0380     BLANK();
0381 }
0382 #endif
0383 
0384 #ifdef CONFIG_MIPS_CPS
0385 void output_cps_defines(void)
0386 {
0387     COMMENT(" MIPS CPS offsets. ");
0388 
0389     OFFSET(COREBOOTCFG_VPEMASK, core_boot_config, vpe_mask);
0390     OFFSET(COREBOOTCFG_VPECONFIG, core_boot_config, vpe_config);
0391     DEFINE(COREBOOTCFG_SIZE, sizeof(struct core_boot_config));
0392 
0393     OFFSET(VPEBOOTCFG_PC, vpe_boot_config, pc);
0394     OFFSET(VPEBOOTCFG_SP, vpe_boot_config, sp);
0395     OFFSET(VPEBOOTCFG_GP, vpe_boot_config, gp);
0396     DEFINE(VPEBOOTCFG_SIZE, sizeof(struct vpe_boot_config));
0397 }
0398 #endif
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