mips/jazz/irq.c

0001 /*
0002  * This file is subject to the terms and conditions of the GNU General Public
0003  * License.  See the file "COPYING" in the main directory of this archive
0004  * for more details.
0005  *
0006  * Copyright (C) 1992 Linus Torvalds
0007  * Copyright (C) 1994 - 2001, 2003, 07 Ralf Baechle
0008  */
0009 #include <linux/clockchips.h>
0010 #include <linux/i8253.h>
0011 #include <linux/init.h>
0012 #include <linux/interrupt.h>
0013 #include <linux/kernel.h>
0014 #include <linux/smp.h>
0015 #include <linux/spinlock.h>
0016 #include <linux/irq.h>
0017 #include <linux/pgtable.h>
0018
0019 #include <asm/irq_cpu.h>
0020 #include <asm/i8259.h>
0021 #include <asm/io.h>
0022 #include <asm/jazz.h>
0023 #include <asm/tlbmisc.h>
0024
0025 static DEFINE_RAW_SPINLOCK(r4030_lock);
0026
0027 static void enable_r4030_irq(struct irq_data *d)
0028 {
0029     unsigned int mask = 1 << (d->irq - JAZZ_IRQ_START);
0030     unsigned long flags;
0031
0032     raw_spin_lock_irqsave(&r4030_lock, flags);
0033     mask |= r4030_read_reg16(JAZZ_IO_IRQ_ENABLE);
0034     r4030_write_reg16(JAZZ_IO_IRQ_ENABLE, mask);
0035     raw_spin_unlock_irqrestore(&r4030_lock, flags);
0036 }
0037
0038 void disable_r4030_irq(struct irq_data *d)
0039 {
0040     unsigned int mask = ~(1 << (d->irq - JAZZ_IRQ_START));
0041     unsigned long flags;
0042
0043     raw_spin_lock_irqsave(&r4030_lock, flags);
0044     mask &= r4030_read_reg16(JAZZ_IO_IRQ_ENABLE);
0045     r4030_write_reg16(JAZZ_IO_IRQ_ENABLE, mask);
0046     raw_spin_unlock_irqrestore(&r4030_lock, flags);
0047 }
0048
0049 static struct irq_chip r4030_irq_type = {
0050     .name = "R4030",
0051     .irq_mask = disable_r4030_irq,
0052     .irq_unmask = enable_r4030_irq,
0053 };
0054
0055 void __init init_r4030_ints(void)
0056 {
0057     int i;
0058
0059     for (i = JAZZ_IRQ_START; i <= JAZZ_IRQ_END; i++)
0060         irq_set_chip_and_handler(i, &r4030_irq_type, handle_level_irq);
0061
0062     r4030_write_reg16(JAZZ_IO_IRQ_ENABLE, 0);
0063     r4030_read_reg16(JAZZ_IO_IRQ_SOURCE);       /* clear pending IRQs */
0064     r4030_read_reg32(JAZZ_R4030_INVAL_ADDR);    /* clear error bits */
0065 }
0066
0067 /*
0068  * On systems with i8259-style interrupt controllers we assume for
0069  * driver compatibility reasons interrupts 0 - 15 to be the i8259
0070  * interrupts even if the hardware uses a different interrupt numbering.
0071  */
0072 void __init arch_init_irq(void)
0073 {
0074     /*
0075      * this is a hack to get back the still needed wired mapping
0076      * killed by init_mm()
0077      */
0078
0079     /* Map 0xe0000000 -> 0x0:800005C0, 0xe0010000 -> 0x1:30000580 */
0080     add_wired_entry(0x02000017, 0x03c00017, 0xe0000000, PM_64K);
0081     /* Map 0xe2000000 -> 0x0:900005C0, 0xe3010000 -> 0x0:910005C0 */
0082     add_wired_entry(0x02400017, 0x02440017, 0xe2000000, PM_16M);
0083     /* Map 0xe4000000 -> 0x0:600005C0, 0xe4100000 -> 400005C0 */
0084     add_wired_entry(0x01800017, 0x01000017, 0xe4000000, PM_4M);
0085
0086     init_i8259_irqs();          /* Integrated i8259  */
0087     mips_cpu_irq_init();
0088     init_r4030_ints();
0089
0090     change_c0_status(ST0_IM, IE_IRQ2 | IE_IRQ1);
0091 }
0092
0093 asmlinkage void plat_irq_dispatch(void)
0094 {
0095     unsigned int pending = read_c0_cause() & read_c0_status();
0096     unsigned int irq;
0097
0098     if (pending & IE_IRQ4) {
0099         r4030_read_reg32(JAZZ_TIMER_REGISTER);
0100         do_IRQ(JAZZ_TIMER_IRQ);
0101     } else if (pending & IE_IRQ2) {
0102         irq = *(volatile u8 *)JAZZ_EISA_IRQ_ACK;
0103         do_IRQ(irq);
0104     } else if (pending & IE_IRQ1) {
0105         irq = *(volatile u8 *)JAZZ_IO_IRQ_SOURCE >> 2;
0106         if (likely(irq > 0))
0107             do_IRQ(irq + JAZZ_IRQ_START - 1);
0108         else
0109             panic("Unimplemented loc_no_irq handler");
0110     }
0111 }
0112
0113 struct clock_event_device r4030_clockevent = {
0114     .name       = "r4030",
0115     .features   = CLOCK_EVT_FEAT_PERIODIC,
0116     .rating     = 300,
0117     .irq        = JAZZ_TIMER_IRQ,
0118 };
0119
0120 static irqreturn_t r4030_timer_interrupt(int irq, void *dev_id)
0121 {
0122     struct clock_event_device *cd = dev_id;
0123
0124     cd->event_handler(cd);
0125     return IRQ_HANDLED;
0126 }
0127
0128 void __init plat_time_init(void)
0129 {
0130     struct clock_event_device *cd = &r4030_clockevent;
0131     unsigned int cpu = smp_processor_id();
0132
0133     BUG_ON(HZ != 100);
0134
0135     cd->cpumask     = cpumask_of(cpu);
0136     clockevents_register_device(cd);
0137     if (request_irq(JAZZ_TIMER_IRQ, r4030_timer_interrupt, IRQF_TIMER,
0138             "R4030 timer", cd))
0139         pr_err("Failed to register R4030 timer interrupt\n");
0140
0141     /*
0142      * Set clock to 100Hz.
0143      *
0144      * The R4030 timer receives an input clock of 1kHz which is divided by
0145      * a programmable 4-bit divider.  This makes it fairly inflexible.
0146      */
0147     r4030_write_reg32(JAZZ_TIMER_INTERVAL, 9);
0148     setup_pit_timer();
0149 }