uapi/asm/kvm.h

0001 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
0002 /*
0003  * This file is subject to the terms and conditions of the GNU General Public
0004  * License.  See the file "COPYING" in the main directory of this archive
0005  * for more details.
0006  *
0007  * Copyright (C) 2012  MIPS Technologies, Inc.  All rights reserved.
0008  * Copyright (C) 2013 Cavium, Inc.
0009  * Authors: Sanjay Lal <sanjayl@kymasys.com>
0010  */
0011
0012 #ifndef __LINUX_KVM_MIPS_H
0013 #define __LINUX_KVM_MIPS_H
0014
0015 #include <linux/types.h>
0016
0017 /*
0018  * KVM MIPS specific structures and definitions.
0019  *
0020  * Some parts derived from the x86 version of this file.
0021  */
0022
0023 #define __KVM_HAVE_READONLY_MEM
0024
0025 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1
0026
0027 /*
0028  * for KVM_GET_REGS and KVM_SET_REGS
0029  *
0030  * If Config[AT] is zero (32-bit CPU), the register contents are
0031  * stored in the lower 32-bits of the struct kvm_regs fields and sign
0032  * extended to 64-bits.
0033  */
0034 struct kvm_regs {
0035     /* out (KVM_GET_REGS) / in (KVM_SET_REGS) */
0036     __u64 gpr[32];
0037     __u64 hi;
0038     __u64 lo;
0039     __u64 pc;
0040 };
0041
0042 /*
0043  * for KVM_GET_FPU and KVM_SET_FPU
0044  */
0045 struct kvm_fpu {
0046 };
0047
0048
0049 /*
0050  * For MIPS, we use KVM_SET_ONE_REG and KVM_GET_ONE_REG to access various
0051  * registers.  The id field is broken down as follows:
0052  *
0053  *  bits[63..52] - As per linux/kvm.h
0054  *  bits[51..32] - Must be zero.
0055  *  bits[31..16] - Register set.
0056  *
0057  * Register set = 0: GP registers from kvm_regs (see definitions below).
0058  *
0059  * Register set = 1: CP0 registers.
0060  *  bits[15..8]  - COP0 register set.
0061  *
0062  *  COP0 register set = 0: Main CP0 registers.
0063  *   bits[7..3]   - Register 'rd'  index.
0064  *   bits[2..0]   - Register 'sel' index.
0065  *
0066  *  COP0 register set = 1: MAARs.
0067  *   bits[7..0]   - MAAR index.
0068  *
0069  * Register set = 2: KVM specific registers (see definitions below).
0070  *
0071  * Register set = 3: FPU / MSA registers (see definitions below).
0072  *
0073  * Other sets registers may be added in the future.  Each set would
0074  * have its own identifier in bits[31..16].
0075  */
0076
0077 #define KVM_REG_MIPS_GP     (KVM_REG_MIPS | 0x0000000000000000ULL)
0078 #define KVM_REG_MIPS_CP0    (KVM_REG_MIPS | 0x0000000000010000ULL)
0079 #define KVM_REG_MIPS_KVM    (KVM_REG_MIPS | 0x0000000000020000ULL)
0080 #define KVM_REG_MIPS_FPU    (KVM_REG_MIPS | 0x0000000000030000ULL)
0081
0082
0083 /*
0084  * KVM_REG_MIPS_GP - General purpose registers from kvm_regs.
0085  */
0086
0087 #define KVM_REG_MIPS_R0     (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 |  0)
0088 #define KVM_REG_MIPS_R1     (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 |  1)
0089 #define KVM_REG_MIPS_R2     (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 |  2)
0090 #define KVM_REG_MIPS_R3     (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 |  3)
0091 #define KVM_REG_MIPS_R4     (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 |  4)
0092 #define KVM_REG_MIPS_R5     (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 |  5)
0093 #define KVM_REG_MIPS_R6     (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 |  6)
0094 #define KVM_REG_MIPS_R7     (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 |  7)
0095 #define KVM_REG_MIPS_R8     (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 |  8)
0096 #define KVM_REG_MIPS_R9     (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 |  9)
0097 #define KVM_REG_MIPS_R10    (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 10)
0098 #define KVM_REG_MIPS_R11    (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 11)
0099 #define KVM_REG_MIPS_R12    (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 12)
0100 #define KVM_REG_MIPS_R13    (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 13)
0101 #define KVM_REG_MIPS_R14    (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 14)
0102 #define KVM_REG_MIPS_R15    (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 15)
0103 #define KVM_REG_MIPS_R16    (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 16)
0104 #define KVM_REG_MIPS_R17    (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 17)
0105 #define KVM_REG_MIPS_R18    (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 18)
0106 #define KVM_REG_MIPS_R19    (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 19)
0107 #define KVM_REG_MIPS_R20    (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 20)
0108 #define KVM_REG_MIPS_R21    (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 21)
0109 #define KVM_REG_MIPS_R22    (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 22)
0110 #define KVM_REG_MIPS_R23    (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 23)
0111 #define KVM_REG_MIPS_R24    (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 24)
0112 #define KVM_REG_MIPS_R25    (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 25)
0113 #define KVM_REG_MIPS_R26    (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 26)
0114 #define KVM_REG_MIPS_R27    (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 27)
0115 #define KVM_REG_MIPS_R28    (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 28)
0116 #define KVM_REG_MIPS_R29    (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 29)
0117 #define KVM_REG_MIPS_R30    (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 30)
0118 #define KVM_REG_MIPS_R31    (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 31)
0119
0120 #define KVM_REG_MIPS_HI     (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 32)
0121 #define KVM_REG_MIPS_LO     (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 33)
0122 #define KVM_REG_MIPS_PC     (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 34)
0123
0124
0125 /*
0126  * KVM_REG_MIPS_CP0 - Coprocessor 0 registers.
0127  */
0128
0129 #define KVM_REG_MIPS_MAAR   (KVM_REG_MIPS_CP0 | (1 << 8))
0130 #define KVM_REG_MIPS_CP0_MAAR(n)    (KVM_REG_MIPS_MAAR | \
0131                      KVM_REG_SIZE_U64 | (n))
0132
0133
0134 /*
0135  * KVM_REG_MIPS_KVM - KVM specific control registers.
0136  */
0137
0138 /*
0139  * CP0_Count control
0140  * DC:    Set 0: Master disable CP0_Count and set COUNT_RESUME to now
0141  *        Set 1: Master re-enable CP0_Count with unchanged bias, handling timer
0142  *               interrupts since COUNT_RESUME
0143  *        This can be used to freeze the timer to get a consistent snapshot of
0144  *        the CP0_Count and timer interrupt pending state, while also resuming
0145  *        safely without losing time or guest timer interrupts.
0146  * Other: Reserved, do not change.
0147  */
0148 #define KVM_REG_MIPS_COUNT_CTL      (KVM_REG_MIPS_KVM | KVM_REG_SIZE_U64 | 0)
0149 #define KVM_REG_MIPS_COUNT_CTL_DC   0x00000001
0150
0151 /*
0152  * CP0_Count resume monotonic nanoseconds
0153  * The monotonic nanosecond time of the last set of COUNT_CTL.DC (master
0154  * disable). Any reads and writes of Count related registers while
0155  * COUNT_CTL.DC=1 will appear to occur at this time. When COUNT_CTL.DC is
0156  * cleared again (master enable) any timer interrupts since this time will be
0157  * emulated.
0158  * Modifications to times in the future are rejected.
0159  */
0160 #define KVM_REG_MIPS_COUNT_RESUME   (KVM_REG_MIPS_KVM | KVM_REG_SIZE_U64 | 1)
0161 /*
0162  * CP0_Count rate in Hz
0163  * Specifies the rate of the CP0_Count timer in Hz. Modifications occur without
0164  * discontinuities in CP0_Count.
0165  */
0166 #define KVM_REG_MIPS_COUNT_HZ       (KVM_REG_MIPS_KVM | KVM_REG_SIZE_U64 | 2)
0167
0168
0169 /*
0170  * KVM_REG_MIPS_FPU - Floating Point and MIPS SIMD Architecture (MSA) registers.
0171  *
0172  *  bits[15..8]  - Register subset (see definitions below).
0173  *  bits[7..5]   - Must be zero.
0174  *  bits[4..0]   - Register number within register subset.
0175  */
0176
0177 #define KVM_REG_MIPS_FPR    (KVM_REG_MIPS_FPU | 0x0000000000000000ULL)
0178 #define KVM_REG_MIPS_FCR    (KVM_REG_MIPS_FPU | 0x0000000000000100ULL)
0179 #define KVM_REG_MIPS_MSACR  (KVM_REG_MIPS_FPU | 0x0000000000000200ULL)
0180
0181 /*
0182  * KVM_REG_MIPS_FPR - Floating point / Vector registers.
0183  */
0184 #define KVM_REG_MIPS_FPR_32(n)  (KVM_REG_MIPS_FPR | KVM_REG_SIZE_U32  | (n))
0185 #define KVM_REG_MIPS_FPR_64(n)  (KVM_REG_MIPS_FPR | KVM_REG_SIZE_U64  | (n))
0186 #define KVM_REG_MIPS_VEC_128(n) (KVM_REG_MIPS_FPR | KVM_REG_SIZE_U128 | (n))
0187
0188 /*
0189  * KVM_REG_MIPS_FCR - Floating point control registers.
0190  */
0191 #define KVM_REG_MIPS_FCR_IR (KVM_REG_MIPS_FCR | KVM_REG_SIZE_U32 |  0)
0192 #define KVM_REG_MIPS_FCR_CSR    (KVM_REG_MIPS_FCR | KVM_REG_SIZE_U32 | 31)
0193
0194 /*
0195  * KVM_REG_MIPS_MSACR - MIPS SIMD Architecture (MSA) control registers.
0196  */
0197 #define KVM_REG_MIPS_MSA_IR  (KVM_REG_MIPS_MSACR | KVM_REG_SIZE_U32 |  0)
0198 #define KVM_REG_MIPS_MSA_CSR     (KVM_REG_MIPS_MSACR | KVM_REG_SIZE_U32 |  1)
0199
0200
0201 /*
0202  * KVM MIPS specific structures and definitions
0203  *
0204  */
0205 struct kvm_debug_exit_arch {
0206     __u64 epc;
0207 };
0208
0209 /* for KVM_SET_GUEST_DEBUG */
0210 struct kvm_guest_debug_arch {
0211 };
0212
0213 /* definition of registers in kvm_run */
0214 struct kvm_sync_regs {
0215 };
0216
0217 /* dummy definition */
0218 struct kvm_sregs {
0219 };
0220
0221 struct kvm_mips_interrupt {
0222     /* in */
0223     __u32 cpu;
0224     __u32 irq;
0225 };
0226
0227 #endif /* __LINUX_KVM_MIPS_H */