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0001 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
0002 /*
0003  * Format of an instruction in memory.
0004  *
0005  * This file is subject to the terms and conditions of the GNU General Public
0006  * License.  See the file "COPYING" in the main directory of this archive
0007  * for more details.
0008  *
0009  * Copyright (C) 1996, 2000 by Ralf Baechle
0010  * Copyright (C) 2006 by Thiemo Seufer
0011  * Copyright (C) 2012 MIPS Technologies, Inc.  All rights reserved.
0012  * Copyright (C) 2014 Imagination Technologies Ltd.
0013  */
0014 #ifndef _UAPI_ASM_INST_H
0015 #define _UAPI_ASM_INST_H
0016 
0017 #include <asm/bitfield.h>
0018 
0019 /*
0020  * Major opcodes; before MIPS IV cop1x was called cop3.
0021  */
0022 enum major_op {
0023     spec_op, bcond_op, j_op, jal_op,
0024     beq_op, bne_op, blez_op, bgtz_op,
0025     addi_op, pop10_op = addi_op, addiu_op, slti_op, sltiu_op,
0026     andi_op, ori_op, xori_op, lui_op,
0027     cop0_op, cop1_op, cop2_op, cop1x_op,
0028     beql_op, bnel_op, blezl_op, bgtzl_op,
0029     daddi_op, pop30_op = daddi_op, daddiu_op, ldl_op, ldr_op,
0030     spec2_op, jalx_op, mdmx_op, msa_op = mdmx_op, spec3_op,
0031     lb_op, lh_op, lwl_op, lw_op,
0032     lbu_op, lhu_op, lwr_op, lwu_op,
0033     sb_op, sh_op, swl_op, sw_op,
0034     sdl_op, sdr_op, swr_op, cache_op,
0035     ll_op, lwc1_op, lwc2_op, bc6_op = lwc2_op, pref_op,
0036     lld_op, ldc1_op, ldc2_op, pop66_op = ldc2_op, ld_op,
0037     sc_op, swc1_op, swc2_op, balc6_op = swc2_op, major_3b_op,
0038     scd_op, sdc1_op, sdc2_op, pop76_op = sdc2_op, sd_op
0039 };
0040 
0041 /*
0042  * func field of spec opcode.
0043  */
0044 enum spec_op {
0045     sll_op, movc_op, srl_op, sra_op,
0046     sllv_op, pmon_op, srlv_op, srav_op,
0047     jr_op, jalr_op, movz_op, movn_op,
0048     syscall_op, break_op, spim_op, sync_op,
0049     mfhi_op, mthi_op, mflo_op, mtlo_op,
0050     dsllv_op, spec2_unused_op, dsrlv_op, dsrav_op,
0051     mult_op, multu_op, div_op, divu_op,
0052     dmult_op, dmultu_op, ddiv_op, ddivu_op,
0053     add_op, addu_op, sub_op, subu_op,
0054     and_op, or_op, xor_op, nor_op,
0055     spec3_unused_op, spec4_unused_op, slt_op, sltu_op,
0056     dadd_op, daddu_op, dsub_op, dsubu_op,
0057     tge_op, tgeu_op, tlt_op, tltu_op,
0058     teq_op, seleqz_op, tne_op, selnez_op,
0059     dsll_op, spec5_unused_op, dsrl_op, dsra_op,
0060     dsll32_op, spec6_unused_op, dsrl32_op, dsra32_op
0061 };
0062 
0063 /*
0064  * func field of spec2 opcode.
0065  */
0066 enum spec2_op {
0067     madd_op, maddu_op, mul_op, spec2_3_unused_op,
0068     msub_op, msubu_op, /* more unused ops */
0069     clz_op = 0x20, clo_op,
0070     dclz_op = 0x24, dclo_op,
0071     sdbpp_op = 0x3f
0072 };
0073 
0074 /*
0075  * func field of spec3 opcode.
0076  */
0077 enum spec3_op {
0078     ext_op, dextm_op, dextu_op, dext_op,
0079     ins_op, dinsm_op, dinsu_op, dins_op,
0080     yield_op  = 0x09, lx_op     = 0x0a,
0081     lwle_op   = 0x19, lwre_op   = 0x1a,
0082     cachee_op = 0x1b, sbe_op    = 0x1c,
0083     she_op    = 0x1d, sce_op    = 0x1e,
0084     swe_op    = 0x1f, bshfl_op  = 0x20,
0085     swle_op   = 0x21, swre_op   = 0x22,
0086     prefe_op  = 0x23, dbshfl_op = 0x24,
0087     cache6_op = 0x25, sc6_op    = 0x26,
0088     scd6_op   = 0x27, lbue_op   = 0x28,
0089     lhue_op   = 0x29, lbe_op    = 0x2c,
0090     lhe_op    = 0x2d, lle_op    = 0x2e,
0091     lwe_op    = 0x2f, pref6_op  = 0x35,
0092     ll6_op    = 0x36, lld6_op   = 0x37,
0093     rdhwr_op  = 0x3b
0094 };
0095 
0096 /*
0097  * Bits 10-6 minor opcode for r6 spec mult/div encodings
0098  */
0099 enum mult_op {
0100     mult_mult_op = 0x0,
0101     mult_mul_op = 0x2,
0102     mult_muh_op = 0x3,
0103 };
0104 enum multu_op {
0105     multu_multu_op = 0x0,
0106     multu_mulu_op = 0x2,
0107     multu_muhu_op = 0x3,
0108 };
0109 enum div_op {
0110     div_div_op = 0x0,
0111     div_div6_op = 0x2,
0112     div_mod_op = 0x3,
0113 };
0114 enum divu_op {
0115     divu_divu_op = 0x0,
0116     divu_divu6_op = 0x2,
0117     divu_modu_op = 0x3,
0118 };
0119 enum dmult_op {
0120     dmult_dmult_op = 0x0,
0121     dmult_dmul_op = 0x2,
0122     dmult_dmuh_op = 0x3,
0123 };
0124 enum dmultu_op {
0125     dmultu_dmultu_op = 0x0,
0126     dmultu_dmulu_op = 0x2,
0127     dmultu_dmuhu_op = 0x3,
0128 };
0129 enum ddiv_op {
0130     ddiv_ddiv_op = 0x0,
0131     ddiv_ddiv6_op = 0x2,
0132     ddiv_dmod_op = 0x3,
0133 };
0134 enum ddivu_op {
0135     ddivu_ddivu_op = 0x0,
0136     ddivu_ddivu6_op = 0x2,
0137     ddivu_dmodu_op = 0x3,
0138 };
0139 
0140 /*
0141  * rt field of bcond opcodes.
0142  */
0143 enum rt_op {
0144     bltz_op, bgez_op, bltzl_op, bgezl_op,
0145     spimi_op, unused_rt_op_0x05, unused_rt_op_0x06, unused_rt_op_0x07,
0146     tgei_op, tgeiu_op, tlti_op, tltiu_op,
0147     teqi_op, unused_0x0d_rt_op, tnei_op, unused_0x0f_rt_op,
0148     bltzal_op, bgezal_op, bltzall_op, bgezall_op,
0149     rt_op_0x14, rt_op_0x15, rt_op_0x16, rt_op_0x17,
0150     rt_op_0x18, rt_op_0x19, rt_op_0x1a, rt_op_0x1b,
0151     bposge32_op, rt_op_0x1d, rt_op_0x1e, synci_op
0152 };
0153 
0154 /*
0155  * rs field of cop opcodes.
0156  */
0157 enum cop_op {
0158     mfc_op        = 0x00, dmfc_op       = 0x01,
0159     cfc_op        = 0x02, mfhc0_op      = 0x02,
0160     mfhc_op       = 0x03, mtc_op        = 0x04,
0161     dmtc_op       = 0x05, ctc_op        = 0x06,
0162     mthc0_op      = 0x06, mthc_op       = 0x07,
0163     bc_op         = 0x08, bc1eqz_op     = 0x09,
0164     mfmc0_op      = 0x0b, bc1nez_op     = 0x0d,
0165     wrpgpr_op     = 0x0e, cop_op        = 0x10,
0166     copm_op       = 0x18
0167 };
0168 
0169 /*
0170  * rt field of cop.bc_op opcodes
0171  */
0172 enum bcop_op {
0173     bcf_op, bct_op, bcfl_op, bctl_op
0174 };
0175 
0176 /*
0177  * func field of cop0 coi opcodes.
0178  */
0179 enum cop0_coi_func {
0180     tlbr_op       = 0x01, tlbwi_op      = 0x02,
0181     tlbwr_op      = 0x06, tlbp_op       = 0x08,
0182     rfe_op        = 0x10, eret_op       = 0x18,
0183     wait_op       = 0x20, hypcall_op    = 0x28
0184 };
0185 
0186 /*
0187  * func field of cop0 com opcodes.
0188  */
0189 enum cop0_com_func {
0190     tlbr1_op      = 0x01, tlbw_op       = 0x02,
0191     tlbp1_op      = 0x08, dctr_op       = 0x09,
0192     dctw_op       = 0x0a
0193 };
0194 
0195 /*
0196  * fmt field of cop1 opcodes.
0197  */
0198 enum cop1_fmt {
0199     s_fmt, d_fmt, e_fmt, q_fmt,
0200     w_fmt, l_fmt
0201 };
0202 
0203 /*
0204  * func field of cop1 instructions using d, s or w format.
0205  */
0206 enum cop1_sdw_func {
0207     fadd_op      =  0x00, fsub_op      =  0x01,
0208     fmul_op      =  0x02, fdiv_op      =  0x03,
0209     fsqrt_op     =  0x04, fabs_op      =  0x05,
0210     fmov_op      =  0x06, fneg_op      =  0x07,
0211     froundl_op   =  0x08, ftruncl_op   =  0x09,
0212     fceill_op    =  0x0a, ffloorl_op   =  0x0b,
0213     fround_op    =  0x0c, ftrunc_op    =  0x0d,
0214     fceil_op     =  0x0e, ffloor_op    =  0x0f,
0215     fsel_op      =  0x10,
0216     fmovc_op     =  0x11, fmovz_op     =  0x12,
0217     fmovn_op     =  0x13, fseleqz_op   =  0x14,
0218     frecip_op    =  0x15, frsqrt_op    =  0x16,
0219     fselnez_op   =  0x17, fmaddf_op    =  0x18,
0220     fmsubf_op    =  0x19, frint_op     =  0x1a,
0221     fclass_op    =  0x1b, fmin_op      =  0x1c,
0222     fmina_op     =  0x1d, fmax_op      =  0x1e,
0223     fmaxa_op     =  0x1f, fcvts_op     =  0x20,
0224     fcvtd_op     =  0x21, fcvte_op     =  0x22,
0225     fcvtw_op     =  0x24, fcvtl_op     =  0x25,
0226     fcmp_op      =  0x30
0227 };
0228 
0229 /*
0230  * func field of cop1x opcodes (MIPS IV).
0231  */
0232 enum cop1x_func {
0233     lwxc1_op     =  0x00, ldxc1_op     =  0x01,
0234     swxc1_op     =  0x08, sdxc1_op     =  0x09,
0235     pfetch_op    =  0x0f, madd_s_op    =  0x20,
0236     madd_d_op    =  0x21, madd_e_op    =  0x22,
0237     msub_s_op    =  0x28, msub_d_op    =  0x29,
0238     msub_e_op    =  0x2a, nmadd_s_op   =  0x30,
0239     nmadd_d_op   =  0x31, nmadd_e_op   =  0x32,
0240     nmsub_s_op   =  0x38, nmsub_d_op   =  0x39,
0241     nmsub_e_op   =  0x3a
0242 };
0243 
0244 /*
0245  * func field for mad opcodes (MIPS IV).
0246  */
0247 enum mad_func {
0248     madd_fp_op  = 0x08, msub_fp_op  = 0x0a,
0249     nmadd_fp_op = 0x0c, nmsub_fp_op = 0x0e
0250 };
0251 
0252 /*
0253  * func field for page table walker (Loongson-3).
0254  */
0255 enum ptw_func {
0256     lwdir_op = 0x00,
0257     lwpte_op = 0x01,
0258     lddir_op = 0x02,
0259     ldpte_op = 0x03,
0260 };
0261 
0262 /*
0263  * func field for special3 lx opcodes (Cavium Octeon).
0264  */
0265 enum lx_func {
0266     lwx_op  = 0x00,
0267     lhx_op  = 0x04,
0268     lbux_op = 0x06,
0269     ldx_op  = 0x08,
0270     lwux_op = 0x10,
0271     lhux_op = 0x14,
0272     lbx_op  = 0x16,
0273 };
0274 
0275 /*
0276  * BSHFL opcodes
0277  */
0278 enum bshfl_func {
0279     wsbh_op = 0x2,
0280     seb_op  = 0x10,
0281     seh_op  = 0x18,
0282 };
0283 
0284 /*
0285  * DBSHFL opcodes
0286  */
0287 enum dbshfl_func {
0288     dsbh_op = 0x2,
0289     dshd_op = 0x5,
0290 };
0291 
0292 /*
0293  * MSA minor opcodes.
0294  */
0295 enum msa_func {
0296     msa_elm_op = 0x19,
0297 };
0298 
0299 /*
0300  * MSA ELM opcodes.
0301  */
0302 enum msa_elm {
0303     msa_ctc_op = 0x3e,
0304     msa_cfc_op = 0x7e,
0305 };
0306 
0307 /*
0308  * func field for MSA MI10 format.
0309  */
0310 enum msa_mi10_func {
0311     msa_ld_op = 8,
0312     msa_st_op = 9,
0313 };
0314 
0315 /*
0316  * MSA 2 bit format fields.
0317  */
0318 enum msa_2b_fmt {
0319     msa_fmt_b = 0,
0320     msa_fmt_h = 1,
0321     msa_fmt_w = 2,
0322     msa_fmt_d = 3,
0323 };
0324 
0325 /*
0326  * (microMIPS) Major opcodes.
0327  */
0328 enum mm_major_op {
0329     mm_pool32a_op, mm_pool16a_op, mm_lbu16_op, mm_move16_op,
0330     mm_addi32_op, mm_lbu32_op, mm_sb32_op, mm_lb32_op,
0331     mm_pool32b_op, mm_pool16b_op, mm_lhu16_op, mm_andi16_op,
0332     mm_addiu32_op, mm_lhu32_op, mm_sh32_op, mm_lh32_op,
0333     mm_pool32i_op, mm_pool16c_op, mm_lwsp16_op, mm_pool16d_op,
0334     mm_ori32_op, mm_pool32f_op, mm_pool32s_op, mm_reserved2_op,
0335     mm_pool32c_op, mm_lwgp16_op, mm_lw16_op, mm_pool16e_op,
0336     mm_xori32_op, mm_jals32_op, mm_addiupc_op, mm_reserved3_op,
0337     mm_reserved4_op, mm_pool16f_op, mm_sb16_op, mm_beqz16_op,
0338     mm_slti32_op, mm_beq32_op, mm_swc132_op, mm_lwc132_op,
0339     mm_reserved5_op, mm_reserved6_op, mm_sh16_op, mm_bnez16_op,
0340     mm_sltiu32_op, mm_bne32_op, mm_sdc132_op, mm_ldc132_op,
0341     mm_reserved7_op, mm_reserved8_op, mm_swsp16_op, mm_b16_op,
0342     mm_andi32_op, mm_j32_op, mm_sd32_op, mm_ld32_op,
0343     mm_reserved11_op, mm_reserved12_op, mm_sw16_op, mm_li16_op,
0344     mm_jalx32_op, mm_jal32_op, mm_sw32_op, mm_lw32_op,
0345 };
0346 
0347 /*
0348  * (microMIPS) POOL32I minor opcodes.
0349  */
0350 enum mm_32i_minor_op {
0351     mm_bltz_op, mm_bltzal_op, mm_bgez_op, mm_bgezal_op,
0352     mm_blez_op, mm_bnezc_op, mm_bgtz_op, mm_beqzc_op,
0353     mm_tlti_op, mm_tgei_op, mm_tltiu_op, mm_tgeiu_op,
0354     mm_tnei_op, mm_lui_op, mm_teqi_op, mm_reserved13_op,
0355     mm_synci_op, mm_bltzals_op, mm_reserved14_op, mm_bgezals_op,
0356     mm_bc2f_op, mm_bc2t_op, mm_reserved15_op, mm_reserved16_op,
0357     mm_reserved17_op, mm_reserved18_op, mm_bposge64_op, mm_bposge32_op,
0358     mm_bc1f_op, mm_bc1t_op, mm_reserved19_op, mm_reserved20_op,
0359     mm_bc1any2f_op, mm_bc1any2t_op, mm_bc1any4f_op, mm_bc1any4t_op,
0360 };
0361 
0362 /*
0363  * (microMIPS) POOL32A minor opcodes.
0364  */
0365 enum mm_32a_minor_op {
0366     mm_sll32_op = 0x000,
0367     mm_ins_op = 0x00c,
0368     mm_sllv32_op = 0x010,
0369     mm_ext_op = 0x02c,
0370     mm_pool32axf_op = 0x03c,
0371     mm_srl32_op = 0x040,
0372     mm_srlv32_op = 0x050,
0373     mm_sra_op = 0x080,
0374     mm_srav_op = 0x090,
0375     mm_rotr_op = 0x0c0,
0376     mm_lwxs_op = 0x118,
0377     mm_addu32_op = 0x150,
0378     mm_subu32_op = 0x1d0,
0379     mm_wsbh_op = 0x1ec,
0380     mm_mul_op = 0x210,
0381     mm_and_op = 0x250,
0382     mm_or32_op = 0x290,
0383     mm_xor32_op = 0x310,
0384     mm_slt_op = 0x350,
0385     mm_sltu_op = 0x390,
0386 };
0387 
0388 /*
0389  * (microMIPS) POOL32B functions.
0390  */
0391 enum mm_32b_func {
0392     mm_lwc2_func = 0x0,
0393     mm_lwp_func = 0x1,
0394     mm_ldc2_func = 0x2,
0395     mm_ldp_func = 0x4,
0396     mm_lwm32_func = 0x5,
0397     mm_cache_func = 0x6,
0398     mm_ldm_func = 0x7,
0399     mm_swc2_func = 0x8,
0400     mm_swp_func = 0x9,
0401     mm_sdc2_func = 0xa,
0402     mm_sdp_func = 0xc,
0403     mm_swm32_func = 0xd,
0404     mm_sdm_func = 0xf,
0405 };
0406 
0407 /*
0408  * (microMIPS) POOL32C functions.
0409  */
0410 enum mm_32c_func {
0411     mm_pref_func = 0x2,
0412     mm_ll_func = 0x3,
0413     mm_swr_func = 0x9,
0414     mm_sc_func = 0xb,
0415     mm_lwu_func = 0xe,
0416 };
0417 
0418 /*
0419  * (microMIPS) POOL32AXF minor opcodes.
0420  */
0421 enum mm_32axf_minor_op {
0422     mm_mfc0_op = 0x003,
0423     mm_mtc0_op = 0x00b,
0424     mm_tlbp_op = 0x00d,
0425     mm_mfhi32_op = 0x035,
0426     mm_jalr_op = 0x03c,
0427     mm_tlbr_op = 0x04d,
0428     mm_mflo32_op = 0x075,
0429     mm_jalrhb_op = 0x07c,
0430     mm_tlbwi_op = 0x08d,
0431     mm_mthi32_op = 0x0b5,
0432     mm_tlbwr_op = 0x0cd,
0433     mm_mtlo32_op = 0x0f5,
0434     mm_di_op = 0x11d,
0435     mm_jalrs_op = 0x13c,
0436     mm_jalrshb_op = 0x17c,
0437     mm_sync_op = 0x1ad,
0438     mm_syscall_op = 0x22d,
0439     mm_wait_op = 0x24d,
0440     mm_eret_op = 0x3cd,
0441     mm_divu_op = 0x5dc,
0442 };
0443 
0444 /*
0445  * (microMIPS) POOL32F minor opcodes.
0446  */
0447 enum mm_32f_minor_op {
0448     mm_32f_00_op = 0x00,
0449     mm_32f_01_op = 0x01,
0450     mm_32f_02_op = 0x02,
0451     mm_32f_10_op = 0x08,
0452     mm_32f_11_op = 0x09,
0453     mm_32f_12_op = 0x0a,
0454     mm_32f_20_op = 0x10,
0455     mm_32f_30_op = 0x18,
0456     mm_32f_40_op = 0x20,
0457     mm_32f_41_op = 0x21,
0458     mm_32f_42_op = 0x22,
0459     mm_32f_50_op = 0x28,
0460     mm_32f_51_op = 0x29,
0461     mm_32f_52_op = 0x2a,
0462     mm_32f_60_op = 0x30,
0463     mm_32f_70_op = 0x38,
0464     mm_32f_73_op = 0x3b,
0465     mm_32f_74_op = 0x3c,
0466 };
0467 
0468 /*
0469  * (microMIPS) POOL32F secondary minor opcodes.
0470  */
0471 enum mm_32f_10_minor_op {
0472     mm_lwxc1_op = 0x1,
0473     mm_swxc1_op,
0474     mm_ldxc1_op,
0475     mm_sdxc1_op,
0476     mm_luxc1_op,
0477     mm_suxc1_op,
0478 };
0479 
0480 enum mm_32f_func {
0481     mm_lwxc1_func = 0x048,
0482     mm_swxc1_func = 0x088,
0483     mm_ldxc1_func = 0x0c8,
0484     mm_sdxc1_func = 0x108,
0485 };
0486 
0487 /*
0488  * (microMIPS) POOL32F secondary minor opcodes.
0489  */
0490 enum mm_32f_40_minor_op {
0491     mm_fmovf_op,
0492     mm_fmovt_op,
0493 };
0494 
0495 /*
0496  * (microMIPS) POOL32F secondary minor opcodes.
0497  */
0498 enum mm_32f_60_minor_op {
0499     mm_fadd_op,
0500     mm_fsub_op,
0501     mm_fmul_op,
0502     mm_fdiv_op,
0503 };
0504 
0505 /*
0506  * (microMIPS) POOL32F secondary minor opcodes.
0507  */
0508 enum mm_32f_70_minor_op {
0509     mm_fmovn_op,
0510     mm_fmovz_op,
0511 };
0512 
0513 /*
0514  * (microMIPS) POOL32FXF secondary minor opcodes for POOL32F.
0515  */
0516 enum mm_32f_73_minor_op {
0517     mm_fmov0_op = 0x01,
0518     mm_fcvtl_op = 0x04,
0519     mm_movf0_op = 0x05,
0520     mm_frsqrt_op = 0x08,
0521     mm_ffloorl_op = 0x0c,
0522     mm_fabs0_op = 0x0d,
0523     mm_fcvtw_op = 0x24,
0524     mm_movt0_op = 0x25,
0525     mm_fsqrt_op = 0x28,
0526     mm_ffloorw_op = 0x2c,
0527     mm_fneg0_op = 0x2d,
0528     mm_cfc1_op = 0x40,
0529     mm_frecip_op = 0x48,
0530     mm_fceill_op = 0x4c,
0531     mm_fcvtd0_op = 0x4d,
0532     mm_ctc1_op = 0x60,
0533     mm_fceilw_op = 0x6c,
0534     mm_fcvts0_op = 0x6d,
0535     mm_mfc1_op = 0x80,
0536     mm_fmov1_op = 0x81,
0537     mm_movf1_op = 0x85,
0538     mm_ftruncl_op = 0x8c,
0539     mm_fabs1_op = 0x8d,
0540     mm_mtc1_op = 0xa0,
0541     mm_movt1_op = 0xa5,
0542     mm_ftruncw_op = 0xac,
0543     mm_fneg1_op = 0xad,
0544     mm_mfhc1_op = 0xc0,
0545     mm_froundl_op = 0xcc,
0546     mm_fcvtd1_op = 0xcd,
0547     mm_mthc1_op = 0xe0,
0548     mm_froundw_op = 0xec,
0549     mm_fcvts1_op = 0xed,
0550 };
0551 
0552 /*
0553  * (microMIPS) POOL32S minor opcodes.
0554  */
0555 enum mm_32s_minor_op {
0556     mm_32s_elm_op = 0x16,
0557 };
0558 
0559 /*
0560  * (microMIPS) POOL16C minor opcodes.
0561  */
0562 enum mm_16c_minor_op {
0563     mm_lwm16_op = 0x04,
0564     mm_swm16_op = 0x05,
0565     mm_jr16_op = 0x0c,
0566     mm_jrc_op = 0x0d,
0567     mm_jalr16_op = 0x0e,
0568     mm_jalrs16_op = 0x0f,
0569     mm_jraddiusp_op = 0x18,
0570 };
0571 
0572 /*
0573  * (microMIPS) POOL16D minor opcodes.
0574  */
0575 enum mm_16d_minor_op {
0576     mm_addius5_func,
0577     mm_addiusp_func,
0578 };
0579 
0580 /*
0581  * (MIPS16e) opcodes.
0582  */
0583 enum MIPS16e_ops {
0584     MIPS16e_jal_op = 003,
0585     MIPS16e_ld_op = 007,
0586     MIPS16e_i8_op = 014,
0587     MIPS16e_sd_op = 017,
0588     MIPS16e_lb_op = 020,
0589     MIPS16e_lh_op = 021,
0590     MIPS16e_lwsp_op = 022,
0591     MIPS16e_lw_op = 023,
0592     MIPS16e_lbu_op = 024,
0593     MIPS16e_lhu_op = 025,
0594     MIPS16e_lwpc_op = 026,
0595     MIPS16e_lwu_op = 027,
0596     MIPS16e_sb_op = 030,
0597     MIPS16e_sh_op = 031,
0598     MIPS16e_swsp_op = 032,
0599     MIPS16e_sw_op = 033,
0600     MIPS16e_rr_op = 035,
0601     MIPS16e_extend_op = 036,
0602     MIPS16e_i64_op = 037,
0603 };
0604 
0605 enum MIPS16e_i64_func {
0606     MIPS16e_ldsp_func,
0607     MIPS16e_sdsp_func,
0608     MIPS16e_sdrasp_func,
0609     MIPS16e_dadjsp_func,
0610     MIPS16e_ldpc_func,
0611 };
0612 
0613 enum MIPS16e_rr_func {
0614     MIPS16e_jr_func,
0615 };
0616 
0617 enum MIPS6e_i8_func {
0618     MIPS16e_swrasp_func = 02,
0619 };
0620 
0621 /*
0622  * (microMIPS) NOP instruction.
0623  */
0624 #define MM_NOP16    0x0c00
0625 
0626 struct j_format {
0627     __BITFIELD_FIELD(unsigned int opcode : 6, /* Jump format */
0628     __BITFIELD_FIELD(unsigned int target : 26,
0629     ;))
0630 };
0631 
0632 struct i_format {           /* signed immediate format */
0633     __BITFIELD_FIELD(unsigned int opcode : 6,
0634     __BITFIELD_FIELD(unsigned int rs : 5,
0635     __BITFIELD_FIELD(unsigned int rt : 5,
0636     __BITFIELD_FIELD(signed int simmediate : 16,
0637     ;))))
0638 };
0639 
0640 struct u_format {           /* unsigned immediate format */
0641     __BITFIELD_FIELD(unsigned int opcode : 6,
0642     __BITFIELD_FIELD(unsigned int rs : 5,
0643     __BITFIELD_FIELD(unsigned int rt : 5,
0644     __BITFIELD_FIELD(unsigned int uimmediate : 16,
0645     ;))))
0646 };
0647 
0648 struct c_format {           /* Cache (>= R6000) format */
0649     __BITFIELD_FIELD(unsigned int opcode : 6,
0650     __BITFIELD_FIELD(unsigned int rs : 5,
0651     __BITFIELD_FIELD(unsigned int c_op : 3,
0652     __BITFIELD_FIELD(unsigned int cache : 2,
0653     __BITFIELD_FIELD(unsigned int simmediate : 16,
0654     ;)))))
0655 };
0656 
0657 struct r_format {           /* Register format */
0658     __BITFIELD_FIELD(unsigned int opcode : 6,
0659     __BITFIELD_FIELD(unsigned int rs : 5,
0660     __BITFIELD_FIELD(unsigned int rt : 5,
0661     __BITFIELD_FIELD(unsigned int rd : 5,
0662     __BITFIELD_FIELD(unsigned int re : 5,
0663     __BITFIELD_FIELD(unsigned int func : 6,
0664     ;))))))
0665 };
0666 
0667 struct c0r_format {         /* C0 register format */
0668     __BITFIELD_FIELD(unsigned int opcode : 6,
0669     __BITFIELD_FIELD(unsigned int rs : 5,
0670     __BITFIELD_FIELD(unsigned int rt : 5,
0671     __BITFIELD_FIELD(unsigned int rd : 5,
0672     __BITFIELD_FIELD(unsigned int z: 8,
0673     __BITFIELD_FIELD(unsigned int sel : 3,
0674     ;))))))
0675 };
0676 
0677 struct mfmc0_format {           /* MFMC0 register format */
0678     __BITFIELD_FIELD(unsigned int opcode : 6,
0679     __BITFIELD_FIELD(unsigned int rs : 5,
0680     __BITFIELD_FIELD(unsigned int rt : 5,
0681     __BITFIELD_FIELD(unsigned int rd : 5,
0682     __BITFIELD_FIELD(unsigned int re : 5,
0683     __BITFIELD_FIELD(unsigned int sc : 1,
0684     __BITFIELD_FIELD(unsigned int : 2,
0685     __BITFIELD_FIELD(unsigned int sel : 3,
0686     ;))))))))
0687 };
0688 
0689 struct co_format {          /* C0 CO format */
0690     __BITFIELD_FIELD(unsigned int opcode : 6,
0691     __BITFIELD_FIELD(unsigned int co : 1,
0692     __BITFIELD_FIELD(unsigned int code : 19,
0693     __BITFIELD_FIELD(unsigned int func : 6,
0694     ;))))
0695 };
0696 
0697 struct p_format {       /* Performance counter format (R10000) */
0698     __BITFIELD_FIELD(unsigned int opcode : 6,
0699     __BITFIELD_FIELD(unsigned int rs : 5,
0700     __BITFIELD_FIELD(unsigned int rt : 5,
0701     __BITFIELD_FIELD(unsigned int rd : 5,
0702     __BITFIELD_FIELD(unsigned int re : 5,
0703     __BITFIELD_FIELD(unsigned int func : 6,
0704     ;))))))
0705 };
0706 
0707 struct f_format {           /* FPU register format */
0708     __BITFIELD_FIELD(unsigned int opcode : 6,
0709     __BITFIELD_FIELD(unsigned int : 1,
0710     __BITFIELD_FIELD(unsigned int fmt : 4,
0711     __BITFIELD_FIELD(unsigned int rt : 5,
0712     __BITFIELD_FIELD(unsigned int rd : 5,
0713     __BITFIELD_FIELD(unsigned int re : 5,
0714     __BITFIELD_FIELD(unsigned int func : 6,
0715     ;)))))))
0716 };
0717 
0718 struct ma_format {      /* FPU multiply and add format (MIPS IV) */
0719     __BITFIELD_FIELD(unsigned int opcode : 6,
0720     __BITFIELD_FIELD(unsigned int fr : 5,
0721     __BITFIELD_FIELD(unsigned int ft : 5,
0722     __BITFIELD_FIELD(unsigned int fs : 5,
0723     __BITFIELD_FIELD(unsigned int fd : 5,
0724     __BITFIELD_FIELD(unsigned int func : 4,
0725     __BITFIELD_FIELD(unsigned int fmt : 2,
0726     ;)))))))
0727 };
0728 
0729 struct b_format {           /* BREAK and SYSCALL */
0730     __BITFIELD_FIELD(unsigned int opcode : 6,
0731     __BITFIELD_FIELD(unsigned int code : 20,
0732     __BITFIELD_FIELD(unsigned int func : 6,
0733     ;)))
0734 };
0735 
0736 struct ps_format {          /* MIPS-3D / paired single format */
0737     __BITFIELD_FIELD(unsigned int opcode : 6,
0738     __BITFIELD_FIELD(unsigned int rs : 5,
0739     __BITFIELD_FIELD(unsigned int ft : 5,
0740     __BITFIELD_FIELD(unsigned int fs : 5,
0741     __BITFIELD_FIELD(unsigned int fd : 5,
0742     __BITFIELD_FIELD(unsigned int func : 6,
0743     ;))))))
0744 };
0745 
0746 struct v_format {               /* MDMX vector format */
0747     __BITFIELD_FIELD(unsigned int opcode : 6,
0748     __BITFIELD_FIELD(unsigned int sel : 4,
0749     __BITFIELD_FIELD(unsigned int fmt : 1,
0750     __BITFIELD_FIELD(unsigned int vt : 5,
0751     __BITFIELD_FIELD(unsigned int vs : 5,
0752     __BITFIELD_FIELD(unsigned int vd : 5,
0753     __BITFIELD_FIELD(unsigned int func : 6,
0754     ;)))))))
0755 };
0756 
0757 struct msa_mi10_format {        /* MSA MI10 */
0758     __BITFIELD_FIELD(unsigned int opcode : 6,
0759     __BITFIELD_FIELD(signed int s10 : 10,
0760     __BITFIELD_FIELD(unsigned int rs : 5,
0761     __BITFIELD_FIELD(unsigned int wd : 5,
0762     __BITFIELD_FIELD(unsigned int func : 4,
0763     __BITFIELD_FIELD(unsigned int df : 2,
0764     ;))))))
0765 };
0766 
0767 struct dsp_format {     /* SPEC3 DSP format instructions */
0768     __BITFIELD_FIELD(unsigned int opcode : 6,
0769     __BITFIELD_FIELD(unsigned int base : 5,
0770     __BITFIELD_FIELD(unsigned int index : 5,
0771     __BITFIELD_FIELD(unsigned int rd : 5,
0772     __BITFIELD_FIELD(unsigned int op : 5,
0773     __BITFIELD_FIELD(unsigned int func : 6,
0774     ;))))))
0775 };
0776 
0777 struct spec3_format {   /* SPEC3 */
0778     __BITFIELD_FIELD(unsigned int opcode:6,
0779     __BITFIELD_FIELD(unsigned int rs:5,
0780     __BITFIELD_FIELD(unsigned int rt:5,
0781     __BITFIELD_FIELD(signed int simmediate:9,
0782     __BITFIELD_FIELD(unsigned int func:7,
0783     ;)))))
0784 };
0785 
0786 /*
0787  * microMIPS instruction formats (32-bit length)
0788  *
0789  * NOTE:
0790  *  Parenthesis denote whether the format is a microMIPS instruction or
0791  *  if it is MIPS32 instruction re-encoded for use in the microMIPS ASE.
0792  */
0793 struct fb_format {      /* FPU branch format (MIPS32) */
0794     __BITFIELD_FIELD(unsigned int opcode : 6,
0795     __BITFIELD_FIELD(unsigned int bc : 5,
0796     __BITFIELD_FIELD(unsigned int cc : 3,
0797     __BITFIELD_FIELD(unsigned int flag : 2,
0798     __BITFIELD_FIELD(signed int simmediate : 16,
0799     ;)))))
0800 };
0801 
0802 struct fp0_format {     /* FPU multiply and add format (MIPS32) */
0803     __BITFIELD_FIELD(unsigned int opcode : 6,
0804     __BITFIELD_FIELD(unsigned int fmt : 5,
0805     __BITFIELD_FIELD(unsigned int ft : 5,
0806     __BITFIELD_FIELD(unsigned int fs : 5,
0807     __BITFIELD_FIELD(unsigned int fd : 5,
0808     __BITFIELD_FIELD(unsigned int func : 6,
0809     ;))))))
0810 };
0811 
0812 struct mm_fp0_format {      /* FPU multiply and add format (microMIPS) */
0813     __BITFIELD_FIELD(unsigned int opcode : 6,
0814     __BITFIELD_FIELD(unsigned int ft : 5,
0815     __BITFIELD_FIELD(unsigned int fs : 5,
0816     __BITFIELD_FIELD(unsigned int fd : 5,
0817     __BITFIELD_FIELD(unsigned int fmt : 3,
0818     __BITFIELD_FIELD(unsigned int op : 2,
0819     __BITFIELD_FIELD(unsigned int func : 6,
0820     ;)))))))
0821 };
0822 
0823 struct fp1_format {     /* FPU mfc1 and cfc1 format (MIPS32) */
0824     __BITFIELD_FIELD(unsigned int opcode : 6,
0825     __BITFIELD_FIELD(unsigned int op : 5,
0826     __BITFIELD_FIELD(unsigned int rt : 5,
0827     __BITFIELD_FIELD(unsigned int fs : 5,
0828     __BITFIELD_FIELD(unsigned int fd : 5,
0829     __BITFIELD_FIELD(unsigned int func : 6,
0830     ;))))))
0831 };
0832 
0833 struct mm_fp1_format {      /* FPU mfc1 and cfc1 format (microMIPS) */
0834     __BITFIELD_FIELD(unsigned int opcode : 6,
0835     __BITFIELD_FIELD(unsigned int rt : 5,
0836     __BITFIELD_FIELD(unsigned int fs : 5,
0837     __BITFIELD_FIELD(unsigned int fmt : 2,
0838     __BITFIELD_FIELD(unsigned int op : 8,
0839     __BITFIELD_FIELD(unsigned int func : 6,
0840     ;))))))
0841 };
0842 
0843 struct mm_fp2_format {      /* FPU movt and movf format (microMIPS) */
0844     __BITFIELD_FIELD(unsigned int opcode : 6,
0845     __BITFIELD_FIELD(unsigned int fd : 5,
0846     __BITFIELD_FIELD(unsigned int fs : 5,
0847     __BITFIELD_FIELD(unsigned int cc : 3,
0848     __BITFIELD_FIELD(unsigned int zero : 2,
0849     __BITFIELD_FIELD(unsigned int fmt : 2,
0850     __BITFIELD_FIELD(unsigned int op : 3,
0851     __BITFIELD_FIELD(unsigned int func : 6,
0852     ;))))))))
0853 };
0854 
0855 struct mm_fp3_format {      /* FPU abs and neg format (microMIPS) */
0856     __BITFIELD_FIELD(unsigned int opcode : 6,
0857     __BITFIELD_FIELD(unsigned int rt : 5,
0858     __BITFIELD_FIELD(unsigned int fs : 5,
0859     __BITFIELD_FIELD(unsigned int fmt : 3,
0860     __BITFIELD_FIELD(unsigned int op : 7,
0861     __BITFIELD_FIELD(unsigned int func : 6,
0862     ;))))))
0863 };
0864 
0865 struct mm_fp4_format {      /* FPU c.cond format (microMIPS) */
0866     __BITFIELD_FIELD(unsigned int opcode : 6,
0867     __BITFIELD_FIELD(unsigned int rt : 5,
0868     __BITFIELD_FIELD(unsigned int fs : 5,
0869     __BITFIELD_FIELD(unsigned int cc : 3,
0870     __BITFIELD_FIELD(unsigned int fmt : 3,
0871     __BITFIELD_FIELD(unsigned int cond : 4,
0872     __BITFIELD_FIELD(unsigned int func : 6,
0873     ;)))))))
0874 };
0875 
0876 struct mm_fp5_format {      /* FPU lwxc1 and swxc1 format (microMIPS) */
0877     __BITFIELD_FIELD(unsigned int opcode : 6,
0878     __BITFIELD_FIELD(unsigned int index : 5,
0879     __BITFIELD_FIELD(unsigned int base : 5,
0880     __BITFIELD_FIELD(unsigned int fd : 5,
0881     __BITFIELD_FIELD(unsigned int op : 5,
0882     __BITFIELD_FIELD(unsigned int func : 6,
0883     ;))))))
0884 };
0885 
0886 struct fp6_format {     /* FPU madd and msub format (MIPS IV) */
0887     __BITFIELD_FIELD(unsigned int opcode : 6,
0888     __BITFIELD_FIELD(unsigned int fr : 5,
0889     __BITFIELD_FIELD(unsigned int ft : 5,
0890     __BITFIELD_FIELD(unsigned int fs : 5,
0891     __BITFIELD_FIELD(unsigned int fd : 5,
0892     __BITFIELD_FIELD(unsigned int func : 6,
0893     ;))))))
0894 };
0895 
0896 struct mm_fp6_format {      /* FPU madd and msub format (microMIPS) */
0897     __BITFIELD_FIELD(unsigned int opcode : 6,
0898     __BITFIELD_FIELD(unsigned int ft : 5,
0899     __BITFIELD_FIELD(unsigned int fs : 5,
0900     __BITFIELD_FIELD(unsigned int fd : 5,
0901     __BITFIELD_FIELD(unsigned int fr : 5,
0902     __BITFIELD_FIELD(unsigned int func : 6,
0903     ;))))))
0904 };
0905 
0906 struct mm_i_format {        /* Immediate format (microMIPS) */
0907     __BITFIELD_FIELD(unsigned int opcode : 6,
0908     __BITFIELD_FIELD(unsigned int rt : 5,
0909     __BITFIELD_FIELD(unsigned int rs : 5,
0910     __BITFIELD_FIELD(signed int simmediate : 16,
0911     ;))))
0912 };
0913 
0914 struct mm_m_format {        /* Multi-word load/store format (microMIPS) */
0915     __BITFIELD_FIELD(unsigned int opcode : 6,
0916     __BITFIELD_FIELD(unsigned int rd : 5,
0917     __BITFIELD_FIELD(unsigned int base : 5,
0918     __BITFIELD_FIELD(unsigned int func : 4,
0919     __BITFIELD_FIELD(signed int simmediate : 12,
0920     ;)))))
0921 };
0922 
0923 struct mm_x_format {        /* Scaled indexed load format (microMIPS) */
0924     __BITFIELD_FIELD(unsigned int opcode : 6,
0925     __BITFIELD_FIELD(unsigned int index : 5,
0926     __BITFIELD_FIELD(unsigned int base : 5,
0927     __BITFIELD_FIELD(unsigned int rd : 5,
0928     __BITFIELD_FIELD(unsigned int func : 11,
0929     ;)))))
0930 };
0931 
0932 struct mm_a_format {        /* ADDIUPC format (microMIPS) */
0933     __BITFIELD_FIELD(unsigned int opcode : 6,
0934     __BITFIELD_FIELD(unsigned int rs : 3,
0935     __BITFIELD_FIELD(signed int simmediate : 23,
0936     ;)))
0937 };
0938 
0939 /*
0940  * microMIPS instruction formats (16-bit length)
0941  */
0942 struct mm_b0_format {       /* Unconditional branch format (microMIPS) */
0943     __BITFIELD_FIELD(unsigned int opcode : 6,
0944     __BITFIELD_FIELD(signed int simmediate : 10,
0945     __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
0946     ;)))
0947 };
0948 
0949 struct mm_b1_format {       /* Conditional branch format (microMIPS) */
0950     __BITFIELD_FIELD(unsigned int opcode : 6,
0951     __BITFIELD_FIELD(unsigned int rs : 3,
0952     __BITFIELD_FIELD(signed int simmediate : 7,
0953     __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
0954     ;))))
0955 };
0956 
0957 struct mm16_m_format {      /* Multi-word load/store format */
0958     __BITFIELD_FIELD(unsigned int opcode : 6,
0959     __BITFIELD_FIELD(unsigned int func : 4,
0960     __BITFIELD_FIELD(unsigned int rlist : 2,
0961     __BITFIELD_FIELD(unsigned int imm : 4,
0962     __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
0963     ;)))))
0964 };
0965 
0966 struct mm16_rb_format {     /* Signed immediate format */
0967     __BITFIELD_FIELD(unsigned int opcode : 6,
0968     __BITFIELD_FIELD(unsigned int rt : 3,
0969     __BITFIELD_FIELD(unsigned int base : 3,
0970     __BITFIELD_FIELD(signed int simmediate : 4,
0971     __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
0972     ;)))))
0973 };
0974 
0975 struct mm16_r3_format {     /* Load from global pointer format */
0976     __BITFIELD_FIELD(unsigned int opcode : 6,
0977     __BITFIELD_FIELD(unsigned int rt : 3,
0978     __BITFIELD_FIELD(signed int simmediate : 7,
0979     __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
0980     ;))))
0981 };
0982 
0983 struct mm16_r5_format {     /* Load/store from stack pointer format */
0984     __BITFIELD_FIELD(unsigned int opcode : 6,
0985     __BITFIELD_FIELD(unsigned int rt : 5,
0986     __BITFIELD_FIELD(unsigned int imm : 5,
0987     __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
0988     ;))))
0989 };
0990 
0991 /*
0992  * Loongson-3 overridden COP2 instruction formats (32-bit length)
0993  */
0994 struct loongson3_lswc2_format { /* Loongson-3 overridden lwc2/swc2 Load/Store format */
0995     __BITFIELD_FIELD(unsigned int opcode : 6,
0996     __BITFIELD_FIELD(unsigned int base : 5,
0997     __BITFIELD_FIELD(unsigned int rt : 5,
0998     __BITFIELD_FIELD(unsigned int fr : 1,
0999     __BITFIELD_FIELD(unsigned int offset : 9,
1000     __BITFIELD_FIELD(unsigned int ls : 1,
1001     __BITFIELD_FIELD(unsigned int rq : 5,
1002     ;)))))))
1003 };
1004 
1005 struct loongson3_lsdc2_format { /* Loongson-3 overridden ldc2/sdc2 Load/Store format */
1006     __BITFIELD_FIELD(unsigned int opcode : 6,
1007     __BITFIELD_FIELD(unsigned int base : 5,
1008     __BITFIELD_FIELD(unsigned int rt : 5,
1009     __BITFIELD_FIELD(unsigned int index : 5,
1010     __BITFIELD_FIELD(unsigned int offset : 8,
1011     __BITFIELD_FIELD(unsigned int opcode1 : 3,
1012     ;))))))
1013 };
1014 
1015 struct loongson3_lscsr_format { /* Loongson-3 CPUCFG&CSR read/write format */
1016     __BITFIELD_FIELD(unsigned int opcode : 6,
1017     __BITFIELD_FIELD(unsigned int rs : 5,
1018     __BITFIELD_FIELD(unsigned int fr : 5,
1019     __BITFIELD_FIELD(unsigned int rd : 5,
1020     __BITFIELD_FIELD(unsigned int fd : 5,
1021     __BITFIELD_FIELD(unsigned int func : 6,
1022     ;))))))
1023 };
1024 
1025 /*
1026  * MIPS16e instruction formats (16-bit length)
1027  */
1028 struct m16e_rr {
1029     __BITFIELD_FIELD(unsigned int opcode : 5,
1030     __BITFIELD_FIELD(unsigned int rx : 3,
1031     __BITFIELD_FIELD(unsigned int nd : 1,
1032     __BITFIELD_FIELD(unsigned int l : 1,
1033     __BITFIELD_FIELD(unsigned int ra : 1,
1034     __BITFIELD_FIELD(unsigned int func : 5,
1035     ;))))))
1036 };
1037 
1038 struct m16e_jal {
1039     __BITFIELD_FIELD(unsigned int opcode : 5,
1040     __BITFIELD_FIELD(unsigned int x : 1,
1041     __BITFIELD_FIELD(unsigned int imm20_16 : 5,
1042     __BITFIELD_FIELD(signed int imm25_21 : 5,
1043     ;))))
1044 };
1045 
1046 struct m16e_i64 {
1047     __BITFIELD_FIELD(unsigned int opcode : 5,
1048     __BITFIELD_FIELD(unsigned int func : 3,
1049     __BITFIELD_FIELD(unsigned int imm : 8,
1050     ;)))
1051 };
1052 
1053 struct m16e_ri64 {
1054     __BITFIELD_FIELD(unsigned int opcode : 5,
1055     __BITFIELD_FIELD(unsigned int func : 3,
1056     __BITFIELD_FIELD(unsigned int ry : 3,
1057     __BITFIELD_FIELD(unsigned int imm : 5,
1058     ;))))
1059 };
1060 
1061 struct m16e_ri {
1062     __BITFIELD_FIELD(unsigned int opcode : 5,
1063     __BITFIELD_FIELD(unsigned int rx : 3,
1064     __BITFIELD_FIELD(unsigned int imm : 8,
1065     ;)))
1066 };
1067 
1068 struct m16e_rri {
1069     __BITFIELD_FIELD(unsigned int opcode : 5,
1070     __BITFIELD_FIELD(unsigned int rx : 3,
1071     __BITFIELD_FIELD(unsigned int ry : 3,
1072     __BITFIELD_FIELD(unsigned int imm : 5,
1073     ;))))
1074 };
1075 
1076 struct m16e_i8 {
1077     __BITFIELD_FIELD(unsigned int opcode : 5,
1078     __BITFIELD_FIELD(unsigned int func : 3,
1079     __BITFIELD_FIELD(unsigned int imm : 8,
1080     ;)))
1081 };
1082 
1083 union mips_instruction {
1084     unsigned int word;
1085     unsigned short halfword[2];
1086     unsigned char byte[4];
1087     struct j_format j_format;
1088     struct i_format i_format;
1089     struct u_format u_format;
1090     struct c_format c_format;
1091     struct r_format r_format;
1092     struct c0r_format c0r_format;
1093     struct mfmc0_format mfmc0_format;
1094     struct co_format co_format;
1095     struct p_format p_format;
1096     struct f_format f_format;
1097     struct ma_format ma_format;
1098     struct msa_mi10_format msa_mi10_format;
1099     struct b_format b_format;
1100     struct ps_format ps_format;
1101     struct v_format v_format;
1102     struct dsp_format dsp_format;
1103     struct spec3_format spec3_format;
1104     struct fb_format fb_format;
1105     struct fp0_format fp0_format;
1106     struct mm_fp0_format mm_fp0_format;
1107     struct fp1_format fp1_format;
1108     struct mm_fp1_format mm_fp1_format;
1109     struct mm_fp2_format mm_fp2_format;
1110     struct mm_fp3_format mm_fp3_format;
1111     struct mm_fp4_format mm_fp4_format;
1112     struct mm_fp5_format mm_fp5_format;
1113     struct fp6_format fp6_format;
1114     struct mm_fp6_format mm_fp6_format;
1115     struct mm_i_format mm_i_format;
1116     struct mm_m_format mm_m_format;
1117     struct mm_x_format mm_x_format;
1118     struct mm_a_format mm_a_format;
1119     struct mm_b0_format mm_b0_format;
1120     struct mm_b1_format mm_b1_format;
1121     struct mm16_m_format mm16_m_format ;
1122     struct mm16_rb_format mm16_rb_format;
1123     struct mm16_r3_format mm16_r3_format;
1124     struct mm16_r5_format mm16_r5_format;
1125     struct loongson3_lswc2_format loongson3_lswc2_format;
1126     struct loongson3_lsdc2_format loongson3_lsdc2_format;
1127     struct loongson3_lscsr_format loongson3_lscsr_format;
1128 };
1129 
1130 union mips16e_instruction {
1131     unsigned int full : 16;
1132     struct m16e_rr rr;
1133     struct m16e_jal jal;
1134     struct m16e_i64 i64;
1135     struct m16e_ri64 ri64;
1136     struct m16e_ri ri;
1137     struct m16e_rri rri;
1138     struct m16e_i8 i8;
1139 };
1140 
1141 #endif /* _UAPI_ASM_INST_H */
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