asm/txx9/tx4938.h

0001 /*
0002  * Definitions for TX4937/TX4938
0003  * Copyright (C) 2000-2001 Toshiba Corporation
0004  *
0005  * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
0006  * terms of the GNU General Public License version 2. This program is
0007  * licensed "as is" without any warranty of any kind, whether express
0008  * or implied.
0009  *
0010  * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
0011  */
0012 #ifndef __ASM_TXX9_TX4938_H
0013 #define __ASM_TXX9_TX4938_H
0014
0015 /* some controllers are compatible with 4927 */
0016 #include <asm/txx9/tx4927.h>
0017
0018 #ifdef CONFIG_64BIT
0019 #define TX4938_REG_BASE 0xffffffffff1f0000UL /* == TX4937_REG_BASE */
0020 #else
0021 #define TX4938_REG_BASE 0xff1f0000UL /* == TX4937_REG_BASE */
0022 #endif
0023 #define TX4938_REG_SIZE 0x00010000 /* == TX4937_REG_SIZE */
0024
0025 /* NDFMC, SRAMC, PCIC1, SPIC: TX4938 only */
0026 #define TX4938_NDFMC_REG    (TX4938_REG_BASE + 0x5000)
0027 #define TX4938_SRAMC_REG    (TX4938_REG_BASE + 0x6000)
0028 #define TX4938_PCIC1_REG    (TX4938_REG_BASE + 0x7000)
0029 #define TX4938_SDRAMC_REG   (TX4938_REG_BASE + 0x8000)
0030 #define TX4938_EBUSC_REG    (TX4938_REG_BASE + 0x9000)
0031 #define TX4938_DMA_REG(ch)  (TX4938_REG_BASE + 0xb000 + (ch) * 0x800)
0032 #define TX4938_PCIC_REG     (TX4938_REG_BASE + 0xd000)
0033 #define TX4938_CCFG_REG     (TX4938_REG_BASE + 0xe000)
0034 #define TX4938_NR_TMR   3
0035 #define TX4938_TMR_REG(ch)  ((TX4938_REG_BASE + 0xf000) + (ch) * 0x100)
0036 #define TX4938_NR_SIO   2
0037 #define TX4938_SIO_REG(ch)  ((TX4938_REG_BASE + 0xf300) + (ch) * 0x100)
0038 #define TX4938_PIO_REG      (TX4938_REG_BASE + 0xf500)
0039 #define TX4938_IRC_REG      (TX4938_REG_BASE + 0xf600)
0040 #define TX4938_ACLC_REG     (TX4938_REG_BASE + 0xf700)
0041 #define TX4938_SPI_REG      (TX4938_REG_BASE + 0xf800)
0042
0043 struct tx4938_sramc_reg {
0044     u64 cr;
0045 };
0046
0047 struct tx4938_ccfg_reg {
0048     u64 ccfg;
0049     u64 crir;
0050     u64 pcfg;
0051     u64 toea;
0052     u64 clkctr;
0053     u64 unused0;
0054     u64 garbc;
0055     u64 unused1;
0056     u64 unused2;
0057     u64 ramp;
0058     u64 unused3;
0059     u64 jmpadr;
0060 };
0061
0062 /*
0063  * IRC
0064  */
0065
0066 #define TX4938_IR_ECCERR    0
0067 #define TX4938_IR_WTOERR    1
0068 #define TX4938_NUM_IR_INT   6
0069 #define TX4938_IR_INT(n)    (2 + (n))
0070 #define TX4938_NUM_IR_SIO   2
0071 #define TX4938_IR_SIO(n)    (8 + (n))
0072 #define TX4938_NUM_IR_DMA   4
0073 #define TX4938_IR_DMA(ch, n)    ((ch ? 27 : 10) + (n)) /* 10-13, 27-30 */
0074 #define TX4938_IR_PIO   14
0075 #define TX4938_IR_PDMAC 15
0076 #define TX4938_IR_PCIC  16
0077 #define TX4938_NUM_IR_TMR   3
0078 #define TX4938_IR_TMR(n)    (17 + (n))
0079 #define TX4938_IR_NDFMC 21
0080 #define TX4938_IR_PCIERR    22
0081 #define TX4938_IR_PCIPME    23
0082 #define TX4938_IR_ACLC  24
0083 #define TX4938_IR_ACLCPME   25
0084 #define TX4938_IR_PCIC1 26
0085 #define TX4938_IR_SPI   31
0086 #define TX4938_NUM_IR   32
0087 /* multiplex */
0088 #define TX4938_IR_ETH0  TX4938_IR_INT(4)
0089 #define TX4938_IR_ETH1  TX4938_IR_INT(3)
0090
0091 #define TX4938_IRC_INT  2   /* IP[2] in Status register */
0092
0093 #define TX4938_NUM_PIO  16
0094
0095 /*
0096  * CCFG
0097  */
0098 /* CCFG : Chip Configuration */
0099 #define TX4938_CCFG_WDRST   0x0000020000000000ULL
0100 #define TX4938_CCFG_WDREXEN 0x0000010000000000ULL
0101 #define TX4938_CCFG_BCFG_MASK   0x000000ff00000000ULL
0102 #define TX4938_CCFG_TINTDIS 0x01000000
0103 #define TX4938_CCFG_PCI66   0x00800000
0104 #define TX4938_CCFG_PCIMODE 0x00400000
0105 #define TX4938_CCFG_PCI1_66 0x00200000
0106 #define TX4938_CCFG_DIVMODE_MASK    0x001e0000
0107 #define TX4938_CCFG_DIVMODE_2   (0x4 << 17)
0108 #define TX4938_CCFG_DIVMODE_2_5 (0xf << 17)
0109 #define TX4938_CCFG_DIVMODE_3   (0x5 << 17)
0110 #define TX4938_CCFG_DIVMODE_4   (0x6 << 17)
0111 #define TX4938_CCFG_DIVMODE_4_5 (0xd << 17)
0112 #define TX4938_CCFG_DIVMODE_8   (0x0 << 17)
0113 #define TX4938_CCFG_DIVMODE_10  (0xb << 17)
0114 #define TX4938_CCFG_DIVMODE_12  (0x1 << 17)
0115 #define TX4938_CCFG_DIVMODE_16  (0x2 << 17)
0116 #define TX4938_CCFG_DIVMODE_18  (0x9 << 17)
0117 #define TX4938_CCFG_BEOW    0x00010000
0118 #define TX4938_CCFG_WR  0x00008000
0119 #define TX4938_CCFG_TOE 0x00004000
0120 #define TX4938_CCFG_PCIARB  0x00002000
0121 #define TX4938_CCFG_PCIDIVMODE_MASK 0x00001c00
0122 #define TX4938_CCFG_PCIDIVMODE_4    (0x1 << 10)
0123 #define TX4938_CCFG_PCIDIVMODE_4_5  (0x3 << 10)
0124 #define TX4938_CCFG_PCIDIVMODE_5    (0x5 << 10)
0125 #define TX4938_CCFG_PCIDIVMODE_5_5  (0x7 << 10)
0126 #define TX4938_CCFG_PCIDIVMODE_8    (0x0 << 10)
0127 #define TX4938_CCFG_PCIDIVMODE_9    (0x2 << 10)
0128 #define TX4938_CCFG_PCIDIVMODE_10   (0x4 << 10)
0129 #define TX4938_CCFG_PCIDIVMODE_11   (0x6 << 10)
0130 #define TX4938_CCFG_PCI1DMD 0x00000100
0131 #define TX4938_CCFG_SYSSP_MASK  0x000000c0
0132 #define TX4938_CCFG_ENDIAN  0x00000004
0133 #define TX4938_CCFG_HALT    0x00000002
0134 #define TX4938_CCFG_ACEHOLD 0x00000001
0135
0136 /* PCFG : Pin Configuration */
0137 #define TX4938_PCFG_ETH0_SEL    0x8000000000000000ULL
0138 #define TX4938_PCFG_ETH1_SEL    0x4000000000000000ULL
0139 #define TX4938_PCFG_ATA_SEL 0x2000000000000000ULL
0140 #define TX4938_PCFG_ISA_SEL 0x1000000000000000ULL
0141 #define TX4938_PCFG_SPI_SEL 0x0800000000000000ULL
0142 #define TX4938_PCFG_NDF_SEL 0x0400000000000000ULL
0143 #define TX4938_PCFG_SDCLKDLY_MASK   0x30000000
0144 #define TX4938_PCFG_SDCLKDLY(d) ((d)<<28)
0145 #define TX4938_PCFG_SYSCLKEN    0x08000000
0146 #define TX4938_PCFG_SDCLKEN_ALL 0x07800000
0147 #define TX4938_PCFG_SDCLKEN(ch) (0x00800000<<(ch))
0148 #define TX4938_PCFG_PCICLKEN_ALL    0x003f0000
0149 #define TX4938_PCFG_PCICLKEN(ch)    (0x00010000<<(ch))
0150 #define TX4938_PCFG_SEL2    0x00000200
0151 #define TX4938_PCFG_SEL1    0x00000100
0152 #define TX4938_PCFG_DMASEL_ALL  0x0000000f
0153 #define TX4938_PCFG_DMASEL0_DRQ0    0x00000000
0154 #define TX4938_PCFG_DMASEL0_SIO1    0x00000001
0155 #define TX4938_PCFG_DMASEL1_DRQ1    0x00000000
0156 #define TX4938_PCFG_DMASEL1_SIO1    0x00000002
0157 #define TX4938_PCFG_DMASEL2_DRQ2    0x00000000
0158 #define TX4938_PCFG_DMASEL2_SIO0    0x00000004
0159 #define TX4938_PCFG_DMASEL3_DRQ3    0x00000000
0160 #define TX4938_PCFG_DMASEL3_SIO0    0x00000008
0161
0162 /* CLKCTR : Clock Control */
0163 #define TX4938_CLKCTR_NDFCKD    0x0001000000000000ULL
0164 #define TX4938_CLKCTR_NDFRST    0x0000000100000000ULL
0165 #define TX4938_CLKCTR_ETH1CKD   0x80000000
0166 #define TX4938_CLKCTR_ETH0CKD   0x40000000
0167 #define TX4938_CLKCTR_SPICKD    0x20000000
0168 #define TX4938_CLKCTR_SRAMCKD   0x10000000
0169 #define TX4938_CLKCTR_PCIC1CKD  0x08000000
0170 #define TX4938_CLKCTR_DMA1CKD   0x04000000
0171 #define TX4938_CLKCTR_ACLCKD    0x02000000
0172 #define TX4938_CLKCTR_PIOCKD    0x01000000
0173 #define TX4938_CLKCTR_DMACKD    0x00800000
0174 #define TX4938_CLKCTR_PCICKD    0x00400000
0175 #define TX4938_CLKCTR_TM0CKD    0x00100000
0176 #define TX4938_CLKCTR_TM1CKD    0x00080000
0177 #define TX4938_CLKCTR_TM2CKD    0x00040000
0178 #define TX4938_CLKCTR_SIO0CKD   0x00020000
0179 #define TX4938_CLKCTR_SIO1CKD   0x00010000
0180 #define TX4938_CLKCTR_ETH1RST   0x00008000
0181 #define TX4938_CLKCTR_ETH0RST   0x00004000
0182 #define TX4938_CLKCTR_SPIRST    0x00002000
0183 #define TX4938_CLKCTR_SRAMRST   0x00001000
0184 #define TX4938_CLKCTR_PCIC1RST  0x00000800
0185 #define TX4938_CLKCTR_DMA1RST   0x00000400
0186 #define TX4938_CLKCTR_ACLRST    0x00000200
0187 #define TX4938_CLKCTR_PIORST    0x00000100
0188 #define TX4938_CLKCTR_DMARST    0x00000080
0189 #define TX4938_CLKCTR_PCIRST    0x00000040
0190 #define TX4938_CLKCTR_TM0RST    0x00000010
0191 #define TX4938_CLKCTR_TM1RST    0x00000008
0192 #define TX4938_CLKCTR_TM2RST    0x00000004
0193 #define TX4938_CLKCTR_SIO0RST   0x00000002
0194 #define TX4938_CLKCTR_SIO1RST   0x00000001
0195
0196 /*
0197  * DMA
0198  */
0199 /* bits for MCR */
0200 #define TX4938_DMA_MCR_EIS(ch)  (0x10000000<<(ch))
0201 #define TX4938_DMA_MCR_DIS(ch)  (0x01000000<<(ch))
0202 #define TX4938_DMA_MCR_RSFIF    0x00000080
0203 #define TX4938_DMA_MCR_FIFUM(ch)    (0x00000008<<(ch))
0204 #define TX4938_DMA_MCR_RPRT 0x00000002
0205 #define TX4938_DMA_MCR_MSTEN    0x00000001
0206
0207 /* bits for CCRn */
0208 #define TX4938_DMA_CCR_IMMCHN   0x20000000
0209 #define TX4938_DMA_CCR_USEXFSZ  0x10000000
0210 #define TX4938_DMA_CCR_LE   0x08000000
0211 #define TX4938_DMA_CCR_DBINH    0x04000000
0212 #define TX4938_DMA_CCR_SBINH    0x02000000
0213 #define TX4938_DMA_CCR_CHRST    0x01000000
0214 #define TX4938_DMA_CCR_RVBYTE   0x00800000
0215 #define TX4938_DMA_CCR_ACKPOL   0x00400000
0216 #define TX4938_DMA_CCR_REQPL    0x00200000
0217 #define TX4938_DMA_CCR_EGREQ    0x00100000
0218 #define TX4938_DMA_CCR_CHDN 0x00080000
0219 #define TX4938_DMA_CCR_DNCTL    0x00060000
0220 #define TX4938_DMA_CCR_EXTRQ    0x00010000
0221 #define TX4938_DMA_CCR_INTRQD   0x0000e000
0222 #define TX4938_DMA_CCR_INTENE   0x00001000
0223 #define TX4938_DMA_CCR_INTENC   0x00000800
0224 #define TX4938_DMA_CCR_INTENT   0x00000400
0225 #define TX4938_DMA_CCR_CHNEN    0x00000200
0226 #define TX4938_DMA_CCR_XFACT    0x00000100
0227 #define TX4938_DMA_CCR_SMPCHN   0x00000020
0228 #define TX4938_DMA_CCR_XFSZ(order)  (((order) << 2) & 0x0000001c)
0229 #define TX4938_DMA_CCR_XFSZ_1W  TX4938_DMA_CCR_XFSZ(2)
0230 #define TX4938_DMA_CCR_XFSZ_2W  TX4938_DMA_CCR_XFSZ(3)
0231 #define TX4938_DMA_CCR_XFSZ_4W  TX4938_DMA_CCR_XFSZ(4)
0232 #define TX4938_DMA_CCR_XFSZ_8W  TX4938_DMA_CCR_XFSZ(5)
0233 #define TX4938_DMA_CCR_XFSZ_16W TX4938_DMA_CCR_XFSZ(6)
0234 #define TX4938_DMA_CCR_XFSZ_32W TX4938_DMA_CCR_XFSZ(7)
0235 #define TX4938_DMA_CCR_MEMIO    0x00000002
0236 #define TX4938_DMA_CCR_SNGAD    0x00000001
0237
0238 /* bits for CSRn */
0239 #define TX4938_DMA_CSR_CHNEN    0x00000400
0240 #define TX4938_DMA_CSR_STLXFER  0x00000200
0241 #define TX4938_DMA_CSR_CHNACT   0x00000100
0242 #define TX4938_DMA_CSR_ABCHC    0x00000080
0243 #define TX4938_DMA_CSR_NCHNC    0x00000040
0244 #define TX4938_DMA_CSR_NTRNFC   0x00000020
0245 #define TX4938_DMA_CSR_EXTDN    0x00000010
0246 #define TX4938_DMA_CSR_CFERR    0x00000008
0247 #define TX4938_DMA_CSR_CHERR    0x00000004
0248 #define TX4938_DMA_CSR_DESERR   0x00000002
0249 #define TX4938_DMA_CSR_SORERR   0x00000001
0250
0251 #define tx4938_sdramcptr    tx4927_sdramcptr
0252 #define tx4938_ebuscptr     tx4927_ebuscptr
0253 #define tx4938_pcicptr      tx4927_pcicptr
0254 #define tx4938_pcic1ptr \
0255         ((struct tx4927_pcic_reg __iomem *)TX4938_PCIC1_REG)
0256 #define tx4938_ccfgptr \
0257         ((struct tx4938_ccfg_reg __iomem *)TX4938_CCFG_REG)
0258 #define tx4938_pioptr       ((struct txx9_pio_reg __iomem *)TX4938_PIO_REG)
0259 #define tx4938_sramcptr \
0260         ((struct tx4938_sramc_reg __iomem *)TX4938_SRAMC_REG)
0261
0262
0263 #define TX4938_REV_PCODE()  \
0264     ((__u32)__raw_readq(&tx4938_ccfgptr->crir) >> 16)
0265
0266 #define tx4938_ccfg_clear(bits) tx4927_ccfg_clear(bits)
0267 #define tx4938_ccfg_set(bits)   tx4927_ccfg_set(bits)
0268 #define tx4938_ccfg_change(change, new) tx4927_ccfg_change(change, new)
0269
0270 #define TX4938_SDRAMC_CR(ch)    TX4927_SDRAMC_CR(ch)
0271 #define TX4938_SDRAMC_BA(ch)    TX4927_SDRAMC_BA(ch)
0272 #define TX4938_SDRAMC_SIZE(ch)  TX4927_SDRAMC_SIZE(ch)
0273
0274 #define TX4938_EBUSC_CR(ch) TX4927_EBUSC_CR(ch)
0275 #define TX4938_EBUSC_BA(ch) TX4927_EBUSC_BA(ch)
0276 #define TX4938_EBUSC_SIZE(ch)   TX4927_EBUSC_SIZE(ch)
0277 #define TX4938_EBUSC_WIDTH(ch)  TX4927_EBUSC_WIDTH(ch)
0278
0279 #define tx4938_get_mem_size() tx4927_get_mem_size()
0280 void tx4938_wdt_init(void);
0281 void tx4938_setup(void);
0282 void tx4938_time_init(unsigned int tmrnr);
0283 void tx4938_sio_init(unsigned int sclk, unsigned int cts_mask);
0284 void tx4938_spi_init(int busid);
0285 void tx4938_ethaddr_init(unsigned char *addr0, unsigned char *addr1);
0286 int tx4938_report_pciclk(void);
0287 void tx4938_report_pci1clk(void);
0288 int tx4938_pciclk66_setup(void);
0289 struct pci_dev;
0290 int tx4938_pcic1_map_irq(const struct pci_dev *dev, u8 slot);
0291 void tx4938_setup_pcierr_irq(void);
0292 void tx4938_irq_init(void);
0293 void tx4938_mtd_init(int ch);
0294 void tx4938_ndfmc_init(unsigned int hold, unsigned int spw);
0295
0296 struct tx4938ide_platform_info {
0297     /*
0298      * I/O port shift, for platforms with ports that are
0299      * constantly spaced and need larger than the 1-byte
0300      * spacing used by ata_std_ports().
0301      */
0302     unsigned int ioport_shift;
0303     unsigned int gbus_clock;    /*  0 means no PIO mode tuning. */
0304     unsigned int ebus_ch;
0305 };
0306
0307 void tx4938_ata_init(unsigned int irq, unsigned int shift, int tune);
0308 void tx4938_dmac_init(int memcpy_chan0, int memcpy_chan1);
0309 void tx4938_aclc_init(void);
0310 void tx4938_sramc_init(void);
0311
0312 #endif