asm/txx9/tx4927pcic.h

0001 /*
0002  * include/asm-mips/txx9/tx4927pcic.h
0003  * TX4927 PCI controller definitions.
0004  *
0005  * This file is subject to the terms and conditions of the GNU General Public
0006  * License.  See the file "COPYING" in the main directory of this archive
0007  * for more details.
0008  */
0009 #ifndef __ASM_TXX9_TX4927PCIC_H
0010 #define __ASM_TXX9_TX4927PCIC_H
0011
0012 #include <linux/pci.h>
0013 #include <linux/irqreturn.h>
0014
0015 struct tx4927_pcic_reg {
0016     u32 pciid;
0017     u32 pcistatus;
0018     u32 pciccrev;
0019     u32 pcicfg1;
0020     u32 p2gm0plbase;        /* +10 */
0021     u32 p2gm0pubase;
0022     u32 p2gm1plbase;
0023     u32 p2gm1pubase;
0024     u32 p2gm2pbase;     /* +20 */
0025     u32 p2giopbase;
0026     u32 unused0;
0027     u32 pcisid;
0028     u32 unused1;        /* +30 */
0029     u32 pcicapptr;
0030     u32 unused2;
0031     u32 pcicfg2;
0032     u32 g2ptocnt;       /* +40 */
0033     u32 unused3[15];
0034     u32 g2pstatus;      /* +80 */
0035     u32 g2pmask;
0036     u32 pcisstatus;
0037     u32 pcimask;
0038     u32 p2gcfg;     /* +90 */
0039     u32 p2gstatus;
0040     u32 p2gmask;
0041     u32 p2gccmd;
0042     u32 unused4[24];        /* +a0 */
0043     u32 pbareqport;     /* +100 */
0044     u32 pbacfg;
0045     u32 pbastatus;
0046     u32 pbamask;
0047     u32 pbabm;      /* +110 */
0048     u32 pbacreq;
0049     u32 pbacgnt;
0050     u32 pbacstate;
0051     u64 g2pmgbase[3];       /* +120 */
0052     u64 g2piogbase;
0053     u32 g2pmmask[3];        /* +140 */
0054     u32 g2piomask;
0055     u64 g2pmpbase[3];       /* +150 */
0056     u64 g2piopbase;
0057     u32 pciccfg;        /* +170 */
0058     u32 pcicstatus;
0059     u32 pcicmask;
0060     u32 unused5;
0061     u64 p2gmgbase[3];       /* +180 */
0062     u64 p2giogbase;
0063     u32 g2pcfgadrs;     /* +1a0 */
0064     u32 g2pcfgdata;
0065     u32 unused6[8];
0066     u32 g2pintack;
0067     u32 g2pspc;
0068     u32 unused7[12];        /* +1d0 */
0069     u64 pdmca;      /* +200 */
0070     u64 pdmga;
0071     u64 pdmpa;
0072     u64 pdmctr;
0073     u64 pdmcfg;     /* +220 */
0074     u64 pdmsts;
0075 };
0076
0077 /* bits for PCICMD */
0078 /* see PCI_COMMAND_XXX in linux/pci_regs.h */
0079
0080 /* bits for PCISTAT */
0081 /* see PCI_STATUS_XXX in linux/pci_regs.h */
0082
0083 /* bits for IOBA/MBA */
0084 /* see PCI_BASE_ADDRESS_XXX in linux/pci_regs.h */
0085
0086 /* bits for G2PSTATUS/G2PMASK */
0087 #define TX4927_PCIC_G2PSTATUS_ALL   0x00000003
0088 #define TX4927_PCIC_G2PSTATUS_TTOE  0x00000002
0089 #define TX4927_PCIC_G2PSTATUS_RTOE  0x00000001
0090
0091 /* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci_regs.h */
0092 #define TX4927_PCIC_PCISTATUS_ALL   0x0000f900
0093
0094 /* bits for PBACFG */
0095 #define TX4927_PCIC_PBACFG_FIXPA    0x00000008
0096 #define TX4927_PCIC_PBACFG_RPBA 0x00000004
0097 #define TX4927_PCIC_PBACFG_PBAEN    0x00000002
0098 #define TX4927_PCIC_PBACFG_BMCEN    0x00000001
0099
0100 /* bits for PBASTATUS/PBAMASK */
0101 #define TX4927_PCIC_PBASTATUS_ALL   0x00000001
0102 #define TX4927_PCIC_PBASTATUS_BM    0x00000001
0103
0104 /* bits for G2PMnGBASE */
0105 #define TX4927_PCIC_G2PMnGBASE_BSDIS    0x0000002000000000ULL
0106 #define TX4927_PCIC_G2PMnGBASE_ECHG 0x0000001000000000ULL
0107
0108 /* bits for G2PIOGBASE */
0109 #define TX4927_PCIC_G2PIOGBASE_BSDIS    0x0000002000000000ULL
0110 #define TX4927_PCIC_G2PIOGBASE_ECHG 0x0000001000000000ULL
0111
0112 /* bits for PCICSTATUS/PCICMASK */
0113 #define TX4927_PCIC_PCICSTATUS_ALL  0x000007b8
0114 #define TX4927_PCIC_PCICSTATUS_PME  0x00000400
0115 #define TX4927_PCIC_PCICSTATUS_TLB  0x00000200
0116 #define TX4927_PCIC_PCICSTATUS_NIB  0x00000100
0117 #define TX4927_PCIC_PCICSTATUS_ZIB  0x00000080
0118 #define TX4927_PCIC_PCICSTATUS_PERR 0x00000020
0119 #define TX4927_PCIC_PCICSTATUS_SERR 0x00000010
0120 #define TX4927_PCIC_PCICSTATUS_GBE  0x00000008
0121 #define TX4927_PCIC_PCICSTATUS_IWB  0x00000002
0122 #define TX4927_PCIC_PCICSTATUS_E2PDONE  0x00000001
0123
0124 /* bits for PCICCFG */
0125 #define TX4927_PCIC_PCICCFG_GBWC_MASK   0x0fff0000
0126 #define TX4927_PCIC_PCICCFG_HRST    0x00000800
0127 #define TX4927_PCIC_PCICCFG_SRST    0x00000400
0128 #define TX4927_PCIC_PCICCFG_IRBER   0x00000200
0129 #define TX4927_PCIC_PCICCFG_G2PMEN(ch)  (0x00000100>>(ch))
0130 #define TX4927_PCIC_PCICCFG_G2PM0EN 0x00000100
0131 #define TX4927_PCIC_PCICCFG_G2PM1EN 0x00000080
0132 #define TX4927_PCIC_PCICCFG_G2PM2EN 0x00000040
0133 #define TX4927_PCIC_PCICCFG_G2PIOEN 0x00000020
0134 #define TX4927_PCIC_PCICCFG_TCAR    0x00000010
0135 #define TX4927_PCIC_PCICCFG_ICAEN   0x00000008
0136
0137 /* bits for P2GMnGBASE */
0138 #define TX4927_PCIC_P2GMnGBASE_TMEMEN   0x0000004000000000ULL
0139 #define TX4927_PCIC_P2GMnGBASE_TBSDIS   0x0000002000000000ULL
0140 #define TX4927_PCIC_P2GMnGBASE_TECHG    0x0000001000000000ULL
0141
0142 /* bits for P2GIOGBASE */
0143 #define TX4927_PCIC_P2GIOGBASE_TIOEN    0x0000004000000000ULL
0144 #define TX4927_PCIC_P2GIOGBASE_TBSDIS   0x0000002000000000ULL
0145 #define TX4927_PCIC_P2GIOGBASE_TECHG    0x0000001000000000ULL
0146
0147 #define TX4927_PCIC_IDSEL_AD_TO_SLOT(ad)    ((ad) - 11)
0148 #define TX4927_PCIC_MAX_DEVNU   TX4927_PCIC_IDSEL_AD_TO_SLOT(32)
0149
0150 /* bits for PDMCFG */
0151 #define TX4927_PCIC_PDMCFG_RSTFIFO  0x00200000
0152 #define TX4927_PCIC_PDMCFG_EXFER    0x00100000
0153 #define TX4927_PCIC_PDMCFG_REQDLY_MASK  0x00003800
0154 #define TX4927_PCIC_PDMCFG_REQDLY_NONE  (0 << 11)
0155 #define TX4927_PCIC_PDMCFG_REQDLY_16    (1 << 11)
0156 #define TX4927_PCIC_PDMCFG_REQDLY_32    (2 << 11)
0157 #define TX4927_PCIC_PDMCFG_REQDLY_64    (3 << 11)
0158 #define TX4927_PCIC_PDMCFG_REQDLY_128   (4 << 11)
0159 #define TX4927_PCIC_PDMCFG_REQDLY_256   (5 << 11)
0160 #define TX4927_PCIC_PDMCFG_REQDLY_512   (6 << 11)
0161 #define TX4927_PCIC_PDMCFG_REQDLY_1024  (7 << 11)
0162 #define TX4927_PCIC_PDMCFG_ERRIE    0x00000400
0163 #define TX4927_PCIC_PDMCFG_NCCMPIE  0x00000200
0164 #define TX4927_PCIC_PDMCFG_NTCMPIE  0x00000100
0165 #define TX4927_PCIC_PDMCFG_CHNEN    0x00000080
0166 #define TX4927_PCIC_PDMCFG_XFRACT   0x00000040
0167 #define TX4927_PCIC_PDMCFG_BSWAP    0x00000020
0168 #define TX4927_PCIC_PDMCFG_XFRSIZE_MASK 0x0000000c
0169 #define TX4927_PCIC_PDMCFG_XFRSIZE_1DW  0x00000000
0170 #define TX4927_PCIC_PDMCFG_XFRSIZE_1QW  0x00000004
0171 #define TX4927_PCIC_PDMCFG_XFRSIZE_4QW  0x00000008
0172 #define TX4927_PCIC_PDMCFG_XFRDIRC  0x00000002
0173 #define TX4927_PCIC_PDMCFG_CHRST    0x00000001
0174
0175 /* bits for PDMSTS */
0176 #define TX4927_PCIC_PDMSTS_REQCNT_MASK  0x3f000000
0177 #define TX4927_PCIC_PDMSTS_FIFOCNT_MASK 0x00f00000
0178 #define TX4927_PCIC_PDMSTS_FIFOWP_MASK  0x000c0000
0179 #define TX4927_PCIC_PDMSTS_FIFORP_MASK  0x00030000
0180 #define TX4927_PCIC_PDMSTS_ERRINT   0x00000800
0181 #define TX4927_PCIC_PDMSTS_DONEINT  0x00000400
0182 #define TX4927_PCIC_PDMSTS_CHNEN    0x00000200
0183 #define TX4927_PCIC_PDMSTS_XFRACT   0x00000100
0184 #define TX4927_PCIC_PDMSTS_ACCMP    0x00000080
0185 #define TX4927_PCIC_PDMSTS_NCCMP    0x00000040
0186 #define TX4927_PCIC_PDMSTS_NTCMP    0x00000020
0187 #define TX4927_PCIC_PDMSTS_CFGERR   0x00000008
0188 #define TX4927_PCIC_PDMSTS_PCIERR   0x00000004
0189 #define TX4927_PCIC_PDMSTS_CHNERR   0x00000002
0190 #define TX4927_PCIC_PDMSTS_DATAERR  0x00000001
0191 #define TX4927_PCIC_PDMSTS_ALL_CMP  0x000000e0
0192 #define TX4927_PCIC_PDMSTS_ALL_ERR  0x0000000f
0193
0194 struct tx4927_pcic_reg __iomem *get_tx4927_pcicptr(
0195     struct pci_controller *channel);
0196 void tx4927_pcic_setup(struct tx4927_pcic_reg __iomem *pcicptr,
0197                struct pci_controller *channel, int extarb);
0198 void tx4927_report_pcic_status(void);
0199 char *tx4927_pcibios_setup(char *str);
0200 void tx4927_dump_pcic_settings(void);
0201 irqreturn_t tx4927_pcierr_interrupt(int irq, void *dev_id);
0202
0203 #endif /* __ASM_TXX9_TX4927PCIC_H */