asm/txx9/tx4927.h

0001 /*
0002  * Author: MontaVista Software, Inc.
0003  *     source@mvista.com
0004  *
0005  * Copyright 2001-2006 MontaVista Software Inc.
0006  *
0007  *  This program is free software; you can redistribute it and/or modify it
0008  *  under the terms of the GNU General Public License as published by the
0009  *  Free Software Foundation; either version 2 of the License, or (at your
0010  *  option) any later version.
0011  *
0012  *  THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
0013  *  WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
0014  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
0015  *  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
0016  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
0017  *  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
0018  *  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
0019  *  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
0020  *  TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
0021  *  USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0022  *
0023  *  You should have received a copy of the GNU General Public License along
0024  *  with this program; if not, write to the Free Software Foundation, Inc.,
0025  *  675 Mass Ave, Cambridge, MA 02139, USA.
0026  */
0027 #ifndef __ASM_TXX9_TX4927_H
0028 #define __ASM_TXX9_TX4927_H
0029
0030 #include <linux/types.h>
0031 #include <linux/io.h>
0032 #include <asm/txx9irq.h>
0033 #include <asm/txx9/tx4927pcic.h>
0034
0035 #ifdef CONFIG_64BIT
0036 #define TX4927_REG_BASE 0xffffffffff1f0000UL
0037 #else
0038 #define TX4927_REG_BASE 0xff1f0000UL
0039 #endif
0040 #define TX4927_REG_SIZE 0x00010000
0041
0042 #define TX4927_SDRAMC_REG   (TX4927_REG_BASE + 0x8000)
0043 #define TX4927_EBUSC_REG    (TX4927_REG_BASE + 0x9000)
0044 #define TX4927_DMA_REG      (TX4927_REG_BASE + 0xb000)
0045 #define TX4927_PCIC_REG     (TX4927_REG_BASE + 0xd000)
0046 #define TX4927_CCFG_REG     (TX4927_REG_BASE + 0xe000)
0047 #define TX4927_IRC_REG      (TX4927_REG_BASE + 0xf600)
0048 #define TX4927_NR_TMR   3
0049 #define TX4927_TMR_REG(ch)  (TX4927_REG_BASE + 0xf000 + (ch) * 0x100)
0050 #define TX4927_NR_SIO   2
0051 #define TX4927_SIO_REG(ch)  (TX4927_REG_BASE + 0xf300 + (ch) * 0x100)
0052 #define TX4927_PIO_REG      (TX4927_REG_BASE + 0xf500)
0053 #define TX4927_ACLC_REG     (TX4927_REG_BASE + 0xf700)
0054
0055 #define TX4927_IR_ECCERR    0
0056 #define TX4927_IR_WTOERR    1
0057 #define TX4927_NUM_IR_INT   6
0058 #define TX4927_IR_INT(n)    (2 + (n))
0059 #define TX4927_NUM_IR_SIO   2
0060 #define TX4927_IR_SIO(n)    (8 + (n))
0061 #define TX4927_NUM_IR_DMA   4
0062 #define TX4927_IR_DMA(n)    (10 + (n))
0063 #define TX4927_IR_PIO       14
0064 #define TX4927_IR_PDMAC     15
0065 #define TX4927_IR_PCIC      16
0066 #define TX4927_NUM_IR_TMR   3
0067 #define TX4927_IR_TMR(n)    (17 + (n))
0068 #define TX4927_IR_PCIERR    22
0069 #define TX4927_IR_PCIPME    23
0070 #define TX4927_IR_ACLC      24
0071 #define TX4927_IR_ACLCPME   25
0072 #define TX4927_NUM_IR   32
0073
0074 #define TX4927_IRC_INT  2   /* IP[2] in Status register */
0075
0076 #define TX4927_NUM_PIO  16
0077
0078 struct tx4927_sdramc_reg {
0079     u64 cr[4];
0080     u64 unused0[4];
0081     u64 tr;
0082     u64 unused1[2];
0083     u64 cmd;
0084 };
0085
0086 struct tx4927_ebusc_reg {
0087     u64 cr[8];
0088 };
0089
0090 struct tx4927_ccfg_reg {
0091     u64 ccfg;
0092     u64 crir;
0093     u64 pcfg;
0094     u64 toea;
0095     u64 clkctr;
0096     u64 unused0;
0097     u64 garbc;
0098     u64 unused1;
0099     u64 unused2;
0100     u64 ramp;
0101 };
0102
0103 /*
0104  * CCFG
0105  */
0106 /* CCFG : Chip Configuration */
0107 #define TX4927_CCFG_WDRST   0x0000020000000000ULL
0108 #define TX4927_CCFG_WDREXEN 0x0000010000000000ULL
0109 #define TX4927_CCFG_BCFG_MASK   0x000000ff00000000ULL
0110 #define TX4927_CCFG_TINTDIS 0x01000000
0111 #define TX4927_CCFG_PCI66   0x00800000
0112 #define TX4927_CCFG_PCIMODE 0x00400000
0113 #define TX4927_CCFG_DIVMODE_MASK    0x000e0000
0114 #define TX4927_CCFG_DIVMODE_8   (0x0 << 17)
0115 #define TX4927_CCFG_DIVMODE_12  (0x1 << 17)
0116 #define TX4927_CCFG_DIVMODE_16  (0x2 << 17)
0117 #define TX4927_CCFG_DIVMODE_10  (0x3 << 17)
0118 #define TX4927_CCFG_DIVMODE_2   (0x4 << 17)
0119 #define TX4927_CCFG_DIVMODE_3   (0x5 << 17)
0120 #define TX4927_CCFG_DIVMODE_4   (0x6 << 17)
0121 #define TX4927_CCFG_DIVMODE_2_5 (0x7 << 17)
0122 #define TX4927_CCFG_BEOW    0x00010000
0123 #define TX4927_CCFG_WR  0x00008000
0124 #define TX4927_CCFG_TOE 0x00004000
0125 #define TX4927_CCFG_PCIARB  0x00002000
0126 #define TX4927_CCFG_PCIDIVMODE_MASK 0x00001800
0127 #define TX4927_CCFG_PCIDIVMODE_2_5  0x00000000
0128 #define TX4927_CCFG_PCIDIVMODE_3    0x00000800
0129 #define TX4927_CCFG_PCIDIVMODE_5    0x00001000
0130 #define TX4927_CCFG_PCIDIVMODE_6    0x00001800
0131 #define TX4927_CCFG_SYSSP_MASK  0x000000c0
0132 #define TX4927_CCFG_ENDIAN  0x00000004
0133 #define TX4927_CCFG_HALT    0x00000002
0134 #define TX4927_CCFG_ACEHOLD 0x00000001
0135 #define TX4927_CCFG_W1CBITS (TX4927_CCFG_WDRST | TX4927_CCFG_BEOW)
0136
0137 /* PCFG : Pin Configuration */
0138 #define TX4927_PCFG_SDCLKDLY_MASK   0x30000000
0139 #define TX4927_PCFG_SDCLKDLY(d) ((d)<<28)
0140 #define TX4927_PCFG_SYSCLKEN    0x08000000
0141 #define TX4927_PCFG_SDCLKEN_ALL 0x07800000
0142 #define TX4927_PCFG_SDCLKEN(ch) (0x00800000<<(ch))
0143 #define TX4927_PCFG_PCICLKEN_ALL    0x003f0000
0144 #define TX4927_PCFG_PCICLKEN(ch)    (0x00010000<<(ch))
0145 #define TX4927_PCFG_SEL2    0x00000200
0146 #define TX4927_PCFG_SEL1    0x00000100
0147 #define TX4927_PCFG_DMASEL_ALL  0x000000ff
0148 #define TX4927_PCFG_DMASEL0_MASK    0x00000003
0149 #define TX4927_PCFG_DMASEL1_MASK    0x0000000c
0150 #define TX4927_PCFG_DMASEL2_MASK    0x00000030
0151 #define TX4927_PCFG_DMASEL3_MASK    0x000000c0
0152 #define TX4927_PCFG_DMASEL0_DRQ0    0x00000000
0153 #define TX4927_PCFG_DMASEL0_SIO1    0x00000001
0154 #define TX4927_PCFG_DMASEL0_ACL0    0x00000002
0155 #define TX4927_PCFG_DMASEL0_ACL2    0x00000003
0156 #define TX4927_PCFG_DMASEL1_DRQ1    0x00000000
0157 #define TX4927_PCFG_DMASEL1_SIO1    0x00000004
0158 #define TX4927_PCFG_DMASEL1_ACL1    0x00000008
0159 #define TX4927_PCFG_DMASEL1_ACL3    0x0000000c
0160 #define TX4927_PCFG_DMASEL2_DRQ2    0x00000000  /* SEL2=0 */
0161 #define TX4927_PCFG_DMASEL2_SIO0    0x00000010  /* SEL2=0 */
0162 #define TX4927_PCFG_DMASEL2_ACL1    0x00000000  /* SEL2=1 */
0163 #define TX4927_PCFG_DMASEL2_ACL2    0x00000020  /* SEL2=1 */
0164 #define TX4927_PCFG_DMASEL2_ACL0    0x00000030  /* SEL2=1 */
0165 #define TX4927_PCFG_DMASEL3_DRQ3    0x00000000
0166 #define TX4927_PCFG_DMASEL3_SIO0    0x00000040
0167 #define TX4927_PCFG_DMASEL3_ACL3    0x00000080
0168 #define TX4927_PCFG_DMASEL3_ACL1    0x000000c0
0169
0170 /* CLKCTR : Clock Control */
0171 #define TX4927_CLKCTR_ACLCKD    0x02000000
0172 #define TX4927_CLKCTR_PIOCKD    0x01000000
0173 #define TX4927_CLKCTR_DMACKD    0x00800000
0174 #define TX4927_CLKCTR_PCICKD    0x00400000
0175 #define TX4927_CLKCTR_TM0CKD    0x00100000
0176 #define TX4927_CLKCTR_TM1CKD    0x00080000
0177 #define TX4927_CLKCTR_TM2CKD    0x00040000
0178 #define TX4927_CLKCTR_SIO0CKD   0x00020000
0179 #define TX4927_CLKCTR_SIO1CKD   0x00010000
0180 #define TX4927_CLKCTR_ACLRST    0x00000200
0181 #define TX4927_CLKCTR_PIORST    0x00000100
0182 #define TX4927_CLKCTR_DMARST    0x00000080
0183 #define TX4927_CLKCTR_PCIRST    0x00000040
0184 #define TX4927_CLKCTR_TM0RST    0x00000010
0185 #define TX4927_CLKCTR_TM1RST    0x00000008
0186 #define TX4927_CLKCTR_TM2RST    0x00000004
0187 #define TX4927_CLKCTR_SIO0RST   0x00000002
0188 #define TX4927_CLKCTR_SIO1RST   0x00000001
0189
0190 #define tx4927_sdramcptr \
0191         ((struct tx4927_sdramc_reg __iomem *)TX4927_SDRAMC_REG)
0192 #define tx4927_pcicptr \
0193         ((struct tx4927_pcic_reg __iomem *)TX4927_PCIC_REG)
0194 #define tx4927_ccfgptr \
0195         ((struct tx4927_ccfg_reg __iomem *)TX4927_CCFG_REG)
0196 #define tx4927_ebuscptr \
0197         ((struct tx4927_ebusc_reg __iomem *)TX4927_EBUSC_REG)
0198 #define tx4927_pioptr       ((struct txx9_pio_reg __iomem *)TX4927_PIO_REG)
0199
0200 #define TX4927_REV_PCODE()  \
0201     ((__u32)__raw_readq(&tx4927_ccfgptr->crir) >> 16)
0202
0203 #define TX4927_SDRAMC_CR(ch)    __raw_readq(&tx4927_sdramcptr->cr[(ch)])
0204 #define TX4927_SDRAMC_BA(ch)    ((TX4927_SDRAMC_CR(ch) >> 49) << 21)
0205 #define TX4927_SDRAMC_SIZE(ch)  \
0206     ((((TX4927_SDRAMC_CR(ch) >> 33) & 0x7fff) + 1) << 21)
0207
0208 #define TX4927_EBUSC_CR(ch) __raw_readq(&tx4927_ebuscptr->cr[(ch)])
0209 #define TX4927_EBUSC_BA(ch) ((TX4927_EBUSC_CR(ch) >> 48) << 20)
0210 #define TX4927_EBUSC_SIZE(ch)   \
0211     (0x00100000 << ((unsigned long)(TX4927_EBUSC_CR(ch) >> 8) & 0xf))
0212 #define TX4927_EBUSC_WIDTH(ch)  \
0213     (64 >> ((__u32)(TX4927_EBUSC_CR(ch) >> 20) & 0x3))
0214
0215 /* utilities */
0216 static inline void txx9_clear64(__u64 __iomem *adr, __u64 bits)
0217 {
0218 #ifdef CONFIG_32BIT
0219     unsigned long flags;
0220     local_irq_save(flags);
0221 #endif
0222     ____raw_writeq(____raw_readq(adr) & ~bits, adr);
0223 #ifdef CONFIG_32BIT
0224     local_irq_restore(flags);
0225 #endif
0226 }
0227 static inline void txx9_set64(__u64 __iomem *adr, __u64 bits)
0228 {
0229 #ifdef CONFIG_32BIT
0230     unsigned long flags;
0231     local_irq_save(flags);
0232 #endif
0233     ____raw_writeq(____raw_readq(adr) | bits, adr);
0234 #ifdef CONFIG_32BIT
0235     local_irq_restore(flags);
0236 #endif
0237 }
0238
0239 /* These functions are not interrupt safe. */
0240 static inline void tx4927_ccfg_clear(__u64 bits)
0241 {
0242     ____raw_writeq(____raw_readq(&tx4927_ccfgptr->ccfg)
0243                & ~(TX4927_CCFG_W1CBITS | bits),
0244                &tx4927_ccfgptr->ccfg);
0245 }
0246 static inline void tx4927_ccfg_set(__u64 bits)
0247 {
0248     ____raw_writeq((____raw_readq(&tx4927_ccfgptr->ccfg)
0249             & ~TX4927_CCFG_W1CBITS) | bits,
0250                &tx4927_ccfgptr->ccfg);
0251 }
0252 static inline void tx4927_ccfg_change(__u64 change, __u64 new)
0253 {
0254     ____raw_writeq((____raw_readq(&tx4927_ccfgptr->ccfg)
0255             & ~(TX4927_CCFG_W1CBITS | change)) |
0256                new,
0257                &tx4927_ccfgptr->ccfg);
0258 }
0259
0260 unsigned int tx4927_get_mem_size(void);
0261 void tx4927_wdt_init(void);
0262 void tx4927_setup(void);
0263 void tx4927_time_init(unsigned int tmrnr);
0264 void tx4927_sio_init(unsigned int sclk, unsigned int cts_mask);
0265 int tx4927_report_pciclk(void);
0266 int tx4927_pciclk66_setup(void);
0267 void tx4927_setup_pcierr_irq(void);
0268 void tx4927_irq_init(void);
0269 void tx4927_mtd_init(int ch);
0270 void tx4927_dmac_init(int memcpy_chan);
0271 void tx4927_aclc_init(unsigned int dma_chan_out, unsigned int dma_chan_in);
0272
0273 #endif /* __ASM_TXX9_TX4927_H */