include/asm/sni.h

0001 /*
0002  * SNI specific definitions
0003  *
0004  * This file is subject to the terms and conditions of the GNU General Public
0005  * License.  See the file "COPYING" in the main directory of this archive
0006  * for more details.
0007  *
0008  * Copyright (C) 1997, 1998 by Ralf Baechle
0009  * Copyright (C) 2006 Thomas Bogendoerfer (tsbogend@alpha.franken.de)
0010  */
0011 #ifndef __ASM_SNI_H
0012 #define __ASM_SNI_H
0013
0014 #include <linux/irqreturn.h>
0015
0016 extern unsigned int sni_brd_type;
0017
0018 #define SNI_BRD_10         2
0019 #define SNI_BRD_10NEW          3
0020 #define SNI_BRD_TOWER_OASIC    4
0021 #define SNI_BRD_MINITOWER      5
0022 #define SNI_BRD_PCI_TOWER      6
0023 #define SNI_BRD_RM200          7
0024 #define SNI_BRD_PCI_MTOWER     8
0025 #define SNI_BRD_PCI_DESKTOP    9
0026 #define SNI_BRD_PCI_TOWER_CPLUS   10
0027 #define SNI_BRD_PCI_MTOWER_CPLUS  11
0028
0029 /* RM400 cpu types */
0030 #define SNI_CPU_M8021       0x01
0031 #define SNI_CPU_M8030       0x04
0032 #define SNI_CPU_M8031       0x06
0033 #define SNI_CPU_M8034       0x0f
0034 #define SNI_CPU_M8037       0x07
0035 #define SNI_CPU_M8040       0x05
0036 #define SNI_CPU_M8043       0x09
0037 #define SNI_CPU_M8050       0x0b
0038 #define SNI_CPU_M8053       0x0d
0039
0040 #define SNI_PORT_BASE       CKSEG1ADDR(0xb4000000)
0041
0042 #ifndef __MIPSEL__
0043 /*
0044  * ASIC PCI registers for big endian configuration.
0045  */
0046 #define PCIMT_UCONF     CKSEG1ADDR(0xbfff0004)
0047 #define PCIMT_IOADTIMEOUT2  CKSEG1ADDR(0xbfff000c)
0048 #define PCIMT_IOMEMCONF     CKSEG1ADDR(0xbfff0014)
0049 #define PCIMT_IOMMU     CKSEG1ADDR(0xbfff001c)
0050 #define PCIMT_IOADTIMEOUT1  CKSEG1ADDR(0xbfff0024)
0051 #define PCIMT_DMAACCESS     CKSEG1ADDR(0xbfff002c)
0052 #define PCIMT_DMAHIT        CKSEG1ADDR(0xbfff0034)
0053 #define PCIMT_ERRSTATUS     CKSEG1ADDR(0xbfff003c)
0054 #define PCIMT_ERRADDR       CKSEG1ADDR(0xbfff0044)
0055 #define PCIMT_SYNDROME      CKSEG1ADDR(0xbfff004c)
0056 #define PCIMT_ITPEND        CKSEG1ADDR(0xbfff0054)
0057 #define  IT_INT2        0x01
0058 #define  IT_INTD        0x02
0059 #define  IT_INTC        0x04
0060 #define  IT_INTB        0x08
0061 #define  IT_INTA        0x10
0062 #define  IT_EISA        0x20
0063 #define  IT_SCSI        0x40
0064 #define  IT_ETH         0x80
0065 #define PCIMT_IRQSEL        CKSEG1ADDR(0xbfff005c)
0066 #define PCIMT_TESTMEM       CKSEG1ADDR(0xbfff0064)
0067 #define PCIMT_ECCREG        CKSEG1ADDR(0xbfff006c)
0068 #define PCIMT_CONFIG_ADDRESS    CKSEG1ADDR(0xbfff0074)
0069 #define PCIMT_ASIC_ID       CKSEG1ADDR(0xbfff007c)  /* read */
0070 #define PCIMT_SOFT_RESET    CKSEG1ADDR(0xbfff007c)  /* write */
0071 #define PCIMT_PIA_OE        CKSEG1ADDR(0xbfff0084)
0072 #define PCIMT_PIA_DATAOUT   CKSEG1ADDR(0xbfff008c)
0073 #define PCIMT_PIA_DATAIN    CKSEG1ADDR(0xbfff0094)
0074 #define PCIMT_CACHECONF     CKSEG1ADDR(0xbfff009c)
0075 #define PCIMT_INVSPACE      CKSEG1ADDR(0xbfff00a4)
0076 #else
0077 /*
0078  * ASIC PCI registers for little endian configuration.
0079  */
0080 #define PCIMT_UCONF     CKSEG1ADDR(0xbfff0000)
0081 #define PCIMT_IOADTIMEOUT2  CKSEG1ADDR(0xbfff0008)
0082 #define PCIMT_IOMEMCONF     CKSEG1ADDR(0xbfff0010)
0083 #define PCIMT_IOMMU     CKSEG1ADDR(0xbfff0018)
0084 #define PCIMT_IOADTIMEOUT1  CKSEG1ADDR(0xbfff0020)
0085 #define PCIMT_DMAACCESS     CKSEG1ADDR(0xbfff0028)
0086 #define PCIMT_DMAHIT        CKSEG1ADDR(0xbfff0030)
0087 #define PCIMT_ERRSTATUS     CKSEG1ADDR(0xbfff0038)
0088 #define PCIMT_ERRADDR       CKSEG1ADDR(0xbfff0040)
0089 #define PCIMT_SYNDROME      CKSEG1ADDR(0xbfff0048)
0090 #define PCIMT_ITPEND        CKSEG1ADDR(0xbfff0050)
0091 #define  IT_INT2        0x01
0092 #define  IT_INTD        0x02
0093 #define  IT_INTC        0x04
0094 #define  IT_INTB        0x08
0095 #define  IT_INTA        0x10
0096 #define  IT_EISA        0x20
0097 #define  IT_SCSI        0x40
0098 #define  IT_ETH         0x80
0099 #define PCIMT_IRQSEL        CKSEG1ADDR(0xbfff0058)
0100 #define PCIMT_TESTMEM       CKSEG1ADDR(0xbfff0060)
0101 #define PCIMT_ECCREG        CKSEG1ADDR(0xbfff0068)
0102 #define PCIMT_CONFIG_ADDRESS    CKSEG1ADDR(0xbfff0070)
0103 #define PCIMT_ASIC_ID       CKSEG1ADDR(0xbfff0078)  /* read */
0104 #define PCIMT_SOFT_RESET    CKSEG1ADDR(0xbfff0078)  /* write */
0105 #define PCIMT_PIA_OE        CKSEG1ADDR(0xbfff0080)
0106 #define PCIMT_PIA_DATAOUT   CKSEG1ADDR(0xbfff0088)
0107 #define PCIMT_PIA_DATAIN    CKSEG1ADDR(0xbfff0090)
0108 #define PCIMT_CACHECONF     CKSEG1ADDR(0xbfff0098)
0109 #define PCIMT_INVSPACE      CKSEG1ADDR(0xbfff00a0)
0110 #endif
0111
0112 #define PCIMT_PCI_CONF      CKSEG1ADDR(0xbfff0100)
0113
0114 /*
0115  * Data port for the PCI bus in IO space
0116  */
0117 #define PCIMT_CONFIG_DATA   0x0cfc
0118
0119 /*
0120  * Board specific registers
0121  */
0122 #define PCIMT_CSMSR     CKSEG1ADDR(0xbfd00000)
0123 #define PCIMT_CSSWITCH      CKSEG1ADDR(0xbfd10000)
0124 #define PCIMT_CSITPEND      CKSEG1ADDR(0xbfd20000)
0125 #define PCIMT_AUTO_PO_EN    CKSEG1ADDR(0xbfd30000)
0126 #define PCIMT_CLR_TEMP      CKSEG1ADDR(0xbfd40000)
0127 #define PCIMT_AUTO_PO_DIS   CKSEG1ADDR(0xbfd50000)
0128 #define PCIMT_EXMSR     CKSEG1ADDR(0xbfd60000)
0129 #define PCIMT_UNUSED1       CKSEG1ADDR(0xbfd70000)
0130 #define PCIMT_CSWCSM        CKSEG1ADDR(0xbfd80000)
0131 #define PCIMT_UNUSED2       CKSEG1ADDR(0xbfd90000)
0132 #define PCIMT_CSLED     CKSEG1ADDR(0xbfda0000)
0133 #define PCIMT_CSMAPISA      CKSEG1ADDR(0xbfdb0000)
0134 #define PCIMT_CSRSTBP       CKSEG1ADDR(0xbfdc0000)
0135 #define PCIMT_CLRPOFF       CKSEG1ADDR(0xbfdd0000)
0136 #define PCIMT_CSTIMER       CKSEG1ADDR(0xbfde0000)
0137 #define PCIMT_PWDN      CKSEG1ADDR(0xbfdf0000)
0138
0139 /*
0140  * A20R based boards
0141  */
0142 #define A20R_PT_CLOCK_BASE  CKSEG1ADDR(0xbc040000)
0143 #define A20R_PT_TIM0_ACK    CKSEG1ADDR(0xbc050000)
0144 #define A20R_PT_TIM1_ACK    CKSEG1ADDR(0xbc060000)
0145
0146 #define SNI_A20R_IRQ_BASE   MIPS_CPU_IRQ_BASE
0147 #define SNI_A20R_IRQ_TIMER  (SNI_A20R_IRQ_BASE+5)
0148
0149 #define SNI_PCIT_INT_REG    CKSEG1ADDR(0xbfff000c)
0150
0151 #define SNI_PCIT_INT_START  24
0152 #define SNI_PCIT_INT_END    30
0153
0154 #define PCIT_IRQ_ETHERNET   (MIPS_CPU_IRQ_BASE + 5)
0155 #define PCIT_IRQ_INTA       (SNI_PCIT_INT_START + 0)
0156 #define PCIT_IRQ_INTB       (SNI_PCIT_INT_START + 1)
0157 #define PCIT_IRQ_INTC       (SNI_PCIT_INT_START + 2)
0158 #define PCIT_IRQ_INTD       (SNI_PCIT_INT_START + 3)
0159 #define PCIT_IRQ_SCSI0      (SNI_PCIT_INT_START + 4)
0160 #define PCIT_IRQ_SCSI1      (SNI_PCIT_INT_START + 5)
0161
0162
0163 /*
0164  * Interrupt 0-16 are EISA interrupts.  Interrupts from 16 on are assigned
0165  * to the other interrupts generated by ASIC PCI.
0166  *
0167  * INT2 is a wired-or of the push button interrupt, high temperature interrupt
0168  * ASIC PCI interrupt.
0169  */
0170 #define PCIMT_KEYBOARD_IRQ   1
0171 #define PCIMT_IRQ_INT2      24
0172 #define PCIMT_IRQ_INTD      25
0173 #define PCIMT_IRQ_INTC      26
0174 #define PCIMT_IRQ_INTB      27
0175 #define PCIMT_IRQ_INTA      28
0176 #define PCIMT_IRQ_EISA      29
0177 #define PCIMT_IRQ_SCSI      30
0178
0179 #define PCIMT_IRQ_ETHERNET  (MIPS_CPU_IRQ_BASE+6)
0180
0181 #if 0
0182 #define PCIMT_IRQ_TEMPERATURE   24
0183 #define PCIMT_IRQ_EISA_NMI  25
0184 #define PCIMT_IRQ_POWER_OFF 26
0185 #define PCIMT_IRQ_BUTTON    27
0186 #endif
0187
0188 /*
0189  * Base address for the mapped 16mb EISA bus segment.
0190  */
0191 #define PCIMT_EISA_BASE     CKSEG1ADDR(0xb0000000)
0192
0193 /* PCI EISA Interrupt acknowledge  */
0194 #define PCIMT_INT_ACKNOWLEDGE   CKSEG1ADDR(0xba000000)
0195
0196 /*
0197  *  SNI ID PROM
0198  *
0199  * SNI_IDPROM_MEMSIZE  Memsize in 16MB quantities
0200  * SNI_IDPROM_BRDTYPE  Board Type
0201  * SNI_IDPROM_CPUTYPE  CPU Type on RM400
0202  */
0203 #ifdef CONFIG_CPU_BIG_ENDIAN
0204 #define __SNI_END 0
0205 #endif
0206 #ifdef CONFIG_CPU_LITTLE_ENDIAN
0207 #define __SNI_END 3
0208 #endif
0209 #define SNI_IDPROM_BASE        CKSEG1ADDR(0x1ff00000)
0210 #define SNI_IDPROM_MEMSIZE     (SNI_IDPROM_BASE + (0x28 ^ __SNI_END))
0211 #define SNI_IDPROM_BRDTYPE     (SNI_IDPROM_BASE + (0x29 ^ __SNI_END))
0212 #define SNI_IDPROM_CPUTYPE     (SNI_IDPROM_BASE + (0x30 ^ __SNI_END))
0213
0214 #define SNI_IDPROM_SIZE 0x1000
0215
0216 /* board specific init functions */
0217 extern void sni_a20r_init(void);
0218 extern void sni_pcit_init(void);
0219 extern void sni_rm200_init(void);
0220 extern void sni_pcimt_init(void);
0221
0222 /* board specific irq init functions */
0223 extern void sni_a20r_irq_init(void);
0224 extern void sni_pcit_irq_init(void);
0225 extern void sni_pcit_cplus_irq_init(void);
0226 extern void sni_rm200_irq_init(void);
0227 extern void sni_pcimt_irq_init(void);
0228
0229 /* timer inits */
0230 extern void sni_cpu_time_init(void);
0231
0232 /* eisa init for RM200/400 */
0233 #ifdef CONFIG_EISA
0234 extern int sni_eisa_root_init(void);
0235 #else
0236 static inline int sni_eisa_root_init(void)
0237 {
0238     return 0;
0239 }
0240 #endif
0241
0242 /* common irq stuff */
0243 extern void (*sni_hwint)(void);
0244 extern irqreturn_t sni_isa_irq_handler(int dummy, void *p);
0245
0246 #endif /* __ASM_SNI_H */