sn/sn0/hubni.h

0001 /*
0002  * This file is subject to the terms and conditions of the GNU General Public
0003  * License.  See the file "COPYING" in the main directory of this archive
0004  * for more details.
0005  *
0006  * Derived from IRIX <sys/SN/SN0/hubni.h>, Revision 1.27.
0007  *
0008  * Copyright (C) 1992-1997, 1999 Silicon Graphics, Inc.
0009  * Copyright (C) 1999 by Ralf Baechle
0010  */
0011 #ifndef _ASM_SGI_SN0_HUBNI_H
0012 #define _ASM_SGI_SN0_HUBNI_H
0013
0014 #ifndef __ASSEMBLY__
0015 #include <linux/types.h>
0016 #endif
0017
0018 /*
0019  * Hub Network Interface registers
0020  *
0021  * All registers in this file are subject to change until Hub chip tapeout.
0022  */
0023
0024 #define NI_BASE         0x600000
0025 #define NI_BASE_TABLES      0x630000
0026
0027 #define NI_STATUS_REV_ID    0x600000 /* Hub network status, rev, and ID */
0028 #define NI_PORT_RESET       0x600008 /* Reset the network interface     */
0029 #define NI_PROTECTION       0x600010 /* NI register access permissions  */
0030 #define NI_GLOBAL_PARMS     0x600018 /* LLP parameters          */
0031 #define NI_SCRATCH_REG0     0x600100 /* Scratch register 0 (64 bits)    */
0032 #define NI_SCRATCH_REG1     0x600108 /* Scratch register 1 (64 bits)    */
0033 #define NI_DIAG_PARMS       0x600110 /* Parameters for diags        */
0034
0035 #define NI_VECTOR_PARMS     0x600200 /* Vector PIO routing parameters   */
0036 #define NI_VECTOR       0x600208 /* Vector PIO route            */
0037 #define NI_VECTOR_DATA      0x600210 /* Vector PIO data         */
0038 #define NI_VECTOR_STATUS    0x600300 /* Vector PIO return status        */
0039 #define NI_RETURN_VECTOR    0x600308 /* Vector PIO return vector        */
0040 #define NI_VECTOR_READ_DATA 0x600310 /* Vector PIO read data        */
0041 #define NI_VECTOR_CLEAR     0x600380 /* Vector PIO read & clear status  */
0042
0043 #define NI_IO_PROTECT       0x600400 /* PIO protection bits         */
0044 #define NI_IO_PROT_OVRRD    0x600408 /* PIO protection bit override     */
0045
0046 #define NI_AGE_CPU0_MEMORY  0x600500 /* CPU 0 memory age control        */
0047 #define NI_AGE_CPU0_PIO     0x600508 /* CPU 0 PIO age control       */
0048 #define NI_AGE_CPU1_MEMORY  0x600510 /* CPU 1 memory age control        */
0049 #define NI_AGE_CPU1_PIO     0x600518 /* CPU 1 PIO age control       */
0050 #define NI_AGE_GBR_MEMORY   0x600520 /* GBR memory age control      */
0051 #define NI_AGE_GBR_PIO      0x600528 /* GBR PIO age control         */
0052 #define NI_AGE_IO_MEMORY    0x600530 /* IO memory age control       */
0053 #define NI_AGE_IO_PIO       0x600538 /* IO PIO age control          */
0054 #define NI_AGE_REG_MIN      NI_AGE_CPU0_MEMORY
0055 #define NI_AGE_REG_MAX      NI_AGE_IO_PIO
0056
0057 #define NI_PORT_PARMS       0x608000 /* LLP Parameters          */
0058 #define NI_PORT_ERROR       0x608008 /* LLP Errors              */
0059 #define NI_PORT_ERROR_CLEAR 0x608088 /* Clear the error bits        */
0060
0061 #define NI_META_TABLE0      0x638000 /* First meta routing table entry  */
0062 #define NI_META_TABLE(_x)   (NI_META_TABLE0 + (8 * (_x)))
0063 #define NI_META_ENTRIES     32
0064
0065 #define NI_LOCAL_TABLE0     0x638100 /* First local routing table entry */
0066 #define NI_LOCAL_TABLE(_x)  (NI_LOCAL_TABLE0 + (8 * (_x)))
0067 #define NI_LOCAL_ENTRIES    16
0068
0069 /*
0070  * NI_STATUS_REV_ID mask and shift definitions
0071  * Have to use UINT64_CAST instead of 'L' suffix, for assembler.
0072  */
0073
0074 #define NSRI_8BITMODE_SHFT  30
0075 #define NSRI_8BITMODE_MASK  (UINT64_CAST 0x1 << 30)
0076 #define NSRI_LINKUP_SHFT    29
0077 #define NSRI_LINKUP_MASK    (UINT64_CAST 0x1 << 29)
0078 #define NSRI_DOWNREASON_SHFT    28      /* 0=failed, 1=never came   */
0079 #define NSRI_DOWNREASON_MASK    (UINT64_CAST 0x1 << 28) /*    out of reset. */
0080 #define NSRI_MORENODES_SHFT 18
0081 #define NSRI_MORENODES_MASK (UINT64_CAST 1 << 18)   /* Max. # of nodes  */
0082 #define  MORE_MEMORY        0
0083 #define  MORE_NODES     1
0084 #define NSRI_REGIONSIZE_SHFT    17
0085 #define NSRI_REGIONSIZE_MASK    (UINT64_CAST 1 << 17)   /* Granularity      */
0086 #define  REGIONSIZE_FINE    1
0087 #define  REGIONSIZE_COARSE  0
0088 #define NSRI_NODEID_SHFT    8
0089 #define NSRI_NODEID_MASK    (UINT64_CAST 0x1ff << 8)/* Node (Hub) ID    */
0090 #define NSRI_REV_SHFT       4
0091 #define NSRI_REV_MASK       (UINT64_CAST 0xf << 4)  /* Chip Revision    */
0092 #define NSRI_CHIPID_SHFT    0
0093 #define NSRI_CHIPID_MASK    (UINT64_CAST 0xf)   /* Chip type ID     */
0094
0095 /*
0096  * In fine mode, each node is a region.  In coarse mode, there are
0097  * eight nodes per region.
0098  */
0099 #define NASID_TO_FINEREG_SHFT   0
0100 #define NASID_TO_COARSEREG_SHFT 3
0101
0102 /* NI_PORT_RESET mask definitions */
0103
0104 #define NPR_PORTRESET       (UINT64_CAST 1 << 7)    /* Send warm reset  */
0105 #define NPR_LINKRESET       (UINT64_CAST 1 << 1)    /* Send link reset  */
0106 #define NPR_LOCALRESET      (UINT64_CAST 1)     /* Reset entire hub */
0107
0108 /* NI_PROTECTION mask and shift definitions */
0109
0110 #define NPROT_RESETOK       (UINT64_CAST 1)
0111
0112 /* NI_GLOBAL_PARMS mask and shift definitions */
0113
0114 #define NGP_MAXRETRY_SHFT   48      /* Maximum retries      */
0115 #define NGP_MAXRETRY_MASK   (UINT64_CAST 0x3ff << 48)
0116 #define NGP_TAILTOWRAP_SHFT 32      /* Tail timeout wrap        */
0117 #define NGP_TAILTOWRAP_MASK (UINT64_CAST 0xffff << 32)
0118
0119 #define NGP_CREDITTOVAL_SHFT    16      /* Tail timeout wrap        */
0120 #define NGP_CREDITTOVAL_MASK    (UINT64_CAST 0xf << 16)
0121 #define NGP_TAILTOVAL_SHFT  4       /* Tail timeout value       */
0122 #define NGP_TAILTOVAL_MASK  (UINT64_CAST 0xf << 4)
0123
0124 /* NI_DIAG_PARMS mask and shift definitions */
0125
0126 #define NDP_PORTTORESET     (UINT64_CAST 1 << 18)   /* Port tmout reset */
0127 #define NDP_LLP8BITMODE     (UINT64_CAST 1 << 12)   /* LLP 8-bit mode   */
0128 #define NDP_PORTDISABLE     (UINT64_CAST 1 <<  6)   /* Port disable     */
0129 #define NDP_SENDERROR       (UINT64_CAST 1)     /* Send data error  */
0130
0131 /*
0132  * NI_VECTOR_PARMS mask and shift definitions.
0133  * TYPE may be any of the first four PIOTYPEs defined under NI_VECTOR_STATUS.
0134  */
0135
0136 #define NVP_PIOID_SHFT      40
0137 #define NVP_PIOID_MASK      (UINT64_CAST 0x3ff << 40)
0138 #define NVP_WRITEID_SHFT    32
0139 #define NVP_WRITEID_MASK    (UINT64_CAST 0xff << 32)
0140 #define NVP_ADDRESS_MASK    (UINT64_CAST 0xffff8)   /* Bits 19:3        */
0141 #define NVP_TYPE_SHFT       0
0142 #define NVP_TYPE_MASK       (UINT64_CAST 0x3)
0143
0144 /* NI_VECTOR_STATUS mask and shift definitions */
0145
0146 #define NVS_VALID       (UINT64_CAST 1 << 63)
0147 #define NVS_OVERRUN     (UINT64_CAST 1 << 62)
0148 #define NVS_TARGET_SHFT     51
0149 #define NVS_TARGET_MASK     (UINT64_CAST 0x3ff << 51)
0150 #define NVS_PIOID_SHFT      40
0151 #define NVS_PIOID_MASK      (UINT64_CAST 0x3ff << 40)
0152 #define NVS_WRITEID_SHFT    32
0153 #define NVS_WRITEID_MASK    (UINT64_CAST 0xff << 32)
0154 #define NVS_ADDRESS_MASK    (UINT64_CAST 0xfffffff8)   /* Bits 31:3     */
0155 #define NVS_TYPE_SHFT       0
0156 #define NVS_TYPE_MASK       (UINT64_CAST 0x7)
0157 #define NVS_ERROR_MASK      (UINT64_CAST 0x4)  /* bit set means error */
0158
0159
0160 #define  PIOTYPE_READ       0   /* VECTOR_PARMS and VECTOR_STATUS   */
0161 #define  PIOTYPE_WRITE      1   /* VECTOR_PARMS and VECTOR_STATUS   */
0162 #define  PIOTYPE_UNDEFINED  2   /* VECTOR_PARMS and VECTOR_STATUS   */
0163 #define  PIOTYPE_EXCHANGE   3   /* VECTOR_PARMS and VECTOR_STATUS   */
0164 #define  PIOTYPE_ADDR_ERR   4   /* VECTOR_STATUS only           */
0165 #define  PIOTYPE_CMD_ERR    5   /* VECTOR_STATUS only           */
0166 #define  PIOTYPE_PROT_ERR   6   /* VECTOR_STATUS only           */
0167 #define  PIOTYPE_UNKNOWN    7   /* VECTOR_STATUS only           */
0168
0169 /* NI_AGE_XXX mask and shift definitions */
0170
0171 #define NAGE_VCH_SHFT       10
0172 #define NAGE_VCH_MASK       (UINT64_CAST 3 << 10)
0173 #define NAGE_CC_SHFT        8
0174 #define NAGE_CC_MASK        (UINT64_CAST 3 << 8)
0175 #define NAGE_AGE_SHFT       0
0176 #define NAGE_AGE_MASK       (UINT64_CAST 0xff)
0177 #define NAGE_MASK       (NAGE_VCH_MASK | NAGE_CC_MASK | NAGE_AGE_MASK)
0178
0179 #define  VCHANNEL_A     0
0180 #define  VCHANNEL_B     1
0181 #define  VCHANNEL_ANY       2
0182
0183 /* NI_PORT_PARMS mask and shift definitions */
0184
0185 #define NPP_NULLTO_SHFT     10
0186 #define NPP_NULLTO_MASK     (UINT64_CAST 0x3f << 16)
0187 #define NPP_MAXBURST_SHFT   0
0188 #define NPP_MAXBURST_MASK   (UINT64_CAST 0x3ff)
0189 #define NPP_RESET_DFLT_HUB20    ((UINT64_CAST 1     << NPP_NULLTO_SHFT) | \
0190                  (UINT64_CAST 0x3f0 << NPP_MAXBURST_SHFT))
0191 #define NPP_RESET_DEFAULTS  ((UINT64_CAST 6     << NPP_NULLTO_SHFT) | \
0192                  (UINT64_CAST 0x3f0 << NPP_MAXBURST_SHFT))
0193
0194
0195 /* NI_PORT_ERROR mask and shift definitions */
0196
0197 #define NPE_LINKRESET       (UINT64_CAST 1 << 37)
0198 #define NPE_INTERNALERROR   (UINT64_CAST 1 << 36)
0199 #define NPE_BADMESSAGE      (UINT64_CAST 1 << 35)
0200 #define NPE_BADDEST     (UINT64_CAST 1 << 34)
0201 #define NPE_FIFOOVERFLOW    (UINT64_CAST 1 << 33)
0202 #define NPE_CREDITTO_SHFT   28
0203 #define NPE_CREDITTO_MASK   (UINT64_CAST 0xf << 28)
0204 #define NPE_TAILTO_SHFT     24
0205 #define NPE_TAILTO_MASK     (UINT64_CAST 0xf << 24)
0206 #define NPE_RETRYCOUNT_SHFT 16
0207 #define NPE_RETRYCOUNT_MASK (UINT64_CAST 0xff << 16)
0208 #define NPE_CBERRCOUNT_SHFT 8
0209 #define NPE_CBERRCOUNT_MASK (UINT64_CAST 0xff << 8)
0210 #define NPE_SNERRCOUNT_SHFT 0
0211 #define NPE_SNERRCOUNT_MASK (UINT64_CAST 0xff << 0)
0212 #define NPE_MASK        0x3effffffff
0213
0214 #define NPE_COUNT_MAX       0xff
0215
0216 #define NPE_FATAL_ERRORS    (NPE_LINKRESET | NPE_INTERNALERROR |    \
0217                  NPE_BADMESSAGE | NPE_BADDEST |     \
0218                  NPE_FIFOOVERFLOW | NPE_CREDITTO_MASK | \
0219                  NPE_TAILTO_MASK)
0220
0221 /* NI_META_TABLE mask and shift definitions */
0222
0223 #define NMT_EXIT_PORT_MASK (UINT64_CAST 0xf)
0224
0225 /* NI_LOCAL_TABLE mask and shift definitions */
0226
0227 #define NLT_EXIT_PORT_MASK (UINT64_CAST 0xf)
0228
0229 #ifndef __ASSEMBLY__
0230
0231 typedef union   hubni_port_error_u {
0232     u64 nipe_reg_value;
0233     struct {
0234         u64 nipe_rsvd:  26, /* unused */
0235         nipe_lnk_reset:  1, /* link reset */
0236         nipe_intl_err:   1, /* internal error */
0237         nipe_bad_msg:    1, /* bad message */
0238         nipe_bad_dest:   1, /* bad dest */
0239         nipe_fifo_ovfl:  1, /* fifo overflow */
0240         nipe_rsvd1:  1, /* unused */
0241         nipe_credit_to:  4, /* credit timeout */
0242         nipe_tail_to:    4, /* tail timeout */
0243         nipe_retry_cnt:  8, /* retry error count */
0244         nipe_cb_cnt:     8, /* checkbit error count */
0245         nipe_sn_cnt:     8; /* sequence number count */
0246     } nipe_fields_s;
0247 } hubni_port_error_t;
0248
0249 #define NI_LLP_RETRY_MAX    0xff
0250 #define NI_LLP_CB_MAX       0xff
0251 #define NI_LLP_SN_MAX       0xff
0252
0253 static inline int get_region_shift(void)
0254 {
0255     if (LOCAL_HUB_L(NI_STATUS_REV_ID) & NSRI_REGIONSIZE_MASK)
0256         return NASID_TO_FINEREG_SHFT;
0257
0258     return NASID_TO_COARSEREG_SHFT;
0259 }
0260
0261 #endif /* !__ASSEMBLY__ */
0262
0263 #endif /* _ASM_SGI_SN0_HUBNI_H */