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OSCL-LXR
 
 

     

0001 /*
0002  * This file is subject to the terms and conditions of the GNU General Public
0003  * License.  See the file "COPYING" in the main directory of this archive
0004  * for more details.
0005  *
0006  * Derived from IRIX <sys/SN/SN0/hubio.h>, Revision 1.80.
0007  *
0008  * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
0009  * Copyright (C) 1999 by Ralf Baechle
0010  */
0011 #ifndef _ASM_SGI_SN_SN0_HUBIO_H
0012 #define _ASM_SGI_SN_SN0_HUBIO_H
0013 
0014 /*
0015  * Hub I/O interface registers
0016  *
0017  * All registers in this file are subject to change until Hub chip tapeout.
0018  * In general, the longer software name should be used when available.
0019  */
0020 
0021 /*
0022  * Slightly friendlier names for some common registers.
0023  * The hardware definitions follow.
0024  */
0025 #define IIO_WIDGET      IIO_WID      /* Widget identification */
0026 #define IIO_WIDGET_STAT     IIO_WSTAT    /* Widget status register */
0027 #define IIO_WIDGET_CTRL     IIO_WCR      /* Widget control register */
0028 #define IIO_WIDGET_TOUT     IIO_WRTO     /* Widget request timeout */
0029 #define IIO_WIDGET_FLUSH    IIO_WTFR     /* Widget target flush */
0030 #define IIO_PROTECT     IIO_ILAPR    /* IO interface protection */
0031 #define IIO_PROTECT_OVRRD   IIO_ILAPO    /* IO protect override */
0032 #define IIO_OUTWIDGET_ACCESS    IIO_IOWA     /* Outbound widget access */
0033 #define IIO_INWIDGET_ACCESS IIO_IIWA     /* Inbound widget access */
0034 #define IIO_INDEV_ERR_MASK  IIO_IIDEM    /* Inbound device error mask */
0035 #define IIO_LLP_CSR     IIO_ILCSR    /* LLP control and status */
0036 #define IIO_LLP_LOG     IIO_ILLR     /* LLP log */
0037 #define IIO_XTALKCC_TOUT    IIO_IXCC     /* Xtalk credit count timeout*/
0038 #define IIO_XTALKTT_TOUT    IIO_IXTT     /* Xtalk tail timeout */
0039 #define IIO_IO_ERR_CLR      IIO_IECLR    /* IO error clear */
0040 #define IIO_BTE_CRB_CNT     IIO_IBCN     /* IO BTE CRB count */
0041 
0042 #define IIO_LLP_CSR_IS_UP       0x00002000
0043 #define IIO_LLP_CSR_LLP_STAT_MASK   0x00003000
0044 #define IIO_LLP_CSR_LLP_STAT_SHFT   12
0045 
0046 /* key to IIO_PROTECT_OVRRD */
0047 #define IIO_PROTECT_OVRRD_KEY   0x53474972756c6573ull   /* "SGIrules" */
0048 
0049 /* BTE register names */
0050 #define IIO_BTE_STAT_0      IIO_IBLS_0   /* Also BTE length/status 0 */
0051 #define IIO_BTE_SRC_0       IIO_IBSA_0   /* Also BTE source address  0 */
0052 #define IIO_BTE_DEST_0      IIO_IBDA_0   /* Also BTE dest. address 0 */
0053 #define IIO_BTE_CTRL_0      IIO_IBCT_0   /* Also BTE control/terminate 0 */
0054 #define IIO_BTE_NOTIFY_0    IIO_IBNA_0   /* Also BTE notification 0 */
0055 #define IIO_BTE_INT_0       IIO_IBIA_0   /* Also BTE interrupt 0 */
0056 #define IIO_BTE_OFF_0       0        /* Base offset from BTE 0 regs. */
0057 #define IIO_BTE_OFF_1   IIO_IBLS_1 - IIO_IBLS_0 /* Offset from base to BTE 1 */
0058 
0059 /* BTE register offsets from base */
0060 #define BTEOFF_STAT     0
0061 #define BTEOFF_SRC      (IIO_BTE_SRC_0 - IIO_BTE_STAT_0)
0062 #define BTEOFF_DEST     (IIO_BTE_DEST_0 - IIO_BTE_STAT_0)
0063 #define BTEOFF_CTRL     (IIO_BTE_CTRL_0 - IIO_BTE_STAT_0)
0064 #define BTEOFF_NOTIFY       (IIO_BTE_NOTIFY_0 - IIO_BTE_STAT_0)
0065 #define BTEOFF_INT      (IIO_BTE_INT_0 - IIO_BTE_STAT_0)
0066 
0067 
0068 /*
0069  * The following definitions use the names defined in the IO interface
0070  * document for ease of reference.  When possible, software should
0071  * generally use the longer but clearer names defined above.
0072  */
0073 
0074 #define IIO_BASE    0x400000
0075 #define IIO_BASE_BTE0   0x410000
0076 #define IIO_BASE_BTE1   0x420000
0077 #define IIO_BASE_PERF   0x430000
0078 #define IIO_PERF_CNT    0x430008
0079 
0080 #define IO_PERF_SETS    32
0081 
0082 #define IIO_WID     0x400000    /* Widget identification */
0083 #define IIO_WSTAT   0x400008    /* Widget status */
0084 #define IIO_WCR     0x400020    /* Widget control */
0085 
0086 #define IIO_WSTAT_ECRAZY    (1ULL << 32)    /* Hub gone crazy */
0087 #define IIO_WSTAT_TXRETRY   (1ULL << 9) /* Hub Tx Retry timeout */
0088 #define IIO_WSTAT_TXRETRY_MASK  (0x7F)
0089 #define IIO_WSTAT_TXRETRY_SHFT  (16)
0090 #define IIO_WSTAT_TXRETRY_CNT(w)    (((w) >> IIO_WSTAT_TXRETRY_SHFT) & \
0091                       IIO_WSTAT_TXRETRY_MASK)
0092 
0093 #define IIO_ILAPR   0x400100    /* Local Access Protection */
0094 #define IIO_ILAPO   0x400108    /* Protection override */
0095 #define IIO_IOWA    0x400110    /* outbound widget access */
0096 #define IIO_IIWA    0x400118    /* inbound widget access */
0097 #define IIO_IIDEM   0x400120    /* Inbound Device Error Mask */
0098 #define IIO_ILCSR   0x400128    /* LLP control and status */
0099 #define IIO_ILLR    0x400130    /* LLP Log */
0100 #define IIO_IIDSR   0x400138    /* Interrupt destination */
0101 
0102 #define IIO_IIBUSERR    0x1400208   /* Reads here cause a bus error. */
0103 
0104 /* IO Interrupt Destination Register */
0105 #define IIO_IIDSR_SENT_SHIFT    28
0106 #define IIO_IIDSR_SENT_MASK 0x10000000
0107 #define IIO_IIDSR_ENB_SHIFT 24
0108 #define IIO_IIDSR_ENB_MASK  0x01000000
0109 #define IIO_IIDSR_NODE_SHIFT    8
0110 #define IIO_IIDSR_NODE_MASK 0x0000ff00
0111 #define IIO_IIDSR_LVL_SHIFT 0
0112 #define IIO_IIDSR_LVL_MASK  0x0000003f
0113 
0114 
0115 /* GFX Flow Control Node/Widget Register */
0116 #define IIO_IGFX_0  0x400140    /* gfx node/widget register 0 */
0117 #define IIO_IGFX_1  0x400148    /* gfx node/widget register 1 */
0118 #define IIO_IGFX_W_NUM_BITS 4   /* size of widget num field */
0119 #define IIO_IGFX_W_NUM_MASK ((1<<IIO_IGFX_W_NUM_BITS)-1)
0120 #define IIO_IGFX_W_NUM_SHIFT    0
0121 #define IIO_IGFX_N_NUM_BITS 9   /* size of node num field */
0122 #define IIO_IGFX_N_NUM_MASK ((1<<IIO_IGFX_N_NUM_BITS)-1)
0123 #define IIO_IGFX_N_NUM_SHIFT    4
0124 #define IIO_IGFX_P_NUM_BITS 1   /* size of processor num field */
0125 #define IIO_IGFX_P_NUM_MASK ((1<<IIO_IGFX_P_NUM_BITS)-1)
0126 #define IIO_IGFX_P_NUM_SHIFT    16
0127 #define IIO_IGFX_VLD_BITS   1   /* size of valid field */
0128 #define IIO_IGFX_VLD_MASK   ((1<<IIO_IGFX_VLD_BITS)-1)
0129 #define IIO_IGFX_VLD_SHIFT  20
0130 #define IIO_IGFX_INIT(widget, node, cpu, valid)             (\
0131     (((widget) & IIO_IGFX_W_NUM_MASK) << IIO_IGFX_W_NUM_SHIFT) |     \
0132     (((node)   & IIO_IGFX_N_NUM_MASK) << IIO_IGFX_N_NUM_SHIFT) |     \
0133     (((cpu)    & IIO_IGFX_P_NUM_MASK) << IIO_IGFX_P_NUM_SHIFT) |     \
0134     (((valid)  & IIO_IGFX_VLD_MASK)   << IIO_IGFX_VLD_SHIFT)     )
0135 
0136 /* Scratch registers (not all bits available) */
0137 #define IIO_SCRATCH_REG0    0x400150
0138 #define IIO_SCRATCH_REG1    0x400158
0139 #define IIO_SCRATCH_MASK    0x0000000f00f11fff
0140 
0141 #define IIO_SCRATCH_BIT0_0  0x0000000800000000
0142 #define IIO_SCRATCH_BIT0_1  0x0000000400000000
0143 #define IIO_SCRATCH_BIT0_2  0x0000000200000000
0144 #define IIO_SCRATCH_BIT0_3  0x0000000100000000
0145 #define IIO_SCRATCH_BIT0_4  0x0000000000800000
0146 #define IIO_SCRATCH_BIT0_5  0x0000000000400000
0147 #define IIO_SCRATCH_BIT0_6  0x0000000000200000
0148 #define IIO_SCRATCH_BIT0_7  0x0000000000100000
0149 #define IIO_SCRATCH_BIT0_8  0x0000000000010000
0150 #define IIO_SCRATCH_BIT0_9  0x0000000000001000
0151 #define IIO_SCRATCH_BIT0_R  0x0000000000000fff
0152 
0153 /* IO Translation Table Entries */
0154 #define IIO_NUM_ITTES   7       /* ITTEs numbered 0..6 */
0155                     /* Hw manuals number them 1..7! */
0156 
0157 /*
0158  * As a permanent workaround for a bug in the PI side of the hub, we've
0159  * redefined big window 7 as small window 0.
0160  */
0161 #define HUB_NUM_BIG_WINDOW  IIO_NUM_ITTES - 1
0162 
0163 /*
0164  * Use the top big window as a surrogate for the first small window
0165  */
0166 #define SWIN0_BIGWIN        HUB_NUM_BIG_WINDOW
0167 
0168 #define ILCSR_WARM_RESET    0x100
0169 /*
0170  * The IO LLP control status register and widget control register
0171  */
0172 #ifndef __ASSEMBLY__
0173 
0174 typedef union hubii_wid_u {
0175     u64 wid_reg_value;
0176     struct {
0177         u64 wid_rsvd:   32, /* unused */
0178             wid_rev_num:     4, /* revision number */
0179             wid_part_num:   16, /* the widget type: hub=c101 */
0180             wid_mfg_num:    11, /* Manufacturer id (IBM) */
0181             wid_rsvd1:   1; /* Reserved */
0182     } wid_fields_s;
0183 } hubii_wid_t;
0184 
0185 
0186 typedef union hubii_wcr_u {
0187     u64 wcr_reg_value;
0188     struct {
0189         u64 wcr_rsvd:   41, /* unused */
0190             wcr_e_thresh:    5, /* elasticity threshold */
0191             wcr_dir_con:     1, /* widget direct connect */
0192             wcr_f_bad_pkt:   1, /* Force bad llp pkt enable */
0193             wcr_xbar_crd:    3, /* LLP crossbar credit */
0194             wcr_rsvd1:   8, /* Reserved */
0195             wcr_tag_mode:    1, /* Tag mode */
0196             wcr_widget_id:   4; /* LLP crossbar credit */
0197     } wcr_fields_s;
0198 } hubii_wcr_t;
0199 
0200 #define iwcr_dir_con    wcr_fields_s.wcr_dir_con
0201 
0202 typedef union hubii_wstat_u {
0203     u64  reg_value;
0204     struct {
0205         u64 rsvd1:      31,
0206             crazy:       1, /* Crazy bit        */
0207             rsvd2:       8,
0208             llp_tx_cnt:  8, /* LLP Xmit retry counter */
0209             rsvd3:       6,
0210             tx_max_rtry:     1, /* LLP Retry Timeout Signal */
0211             rsvd4:       2,
0212             xt_tail_to:  1, /* Xtalk Tail Timeout   */
0213             xt_crd_to:   1, /* Xtalk Credit Timeout */
0214             pending:     4; /* Pending Requests */
0215     } wstat_fields_s;
0216 } hubii_wstat_t;
0217 
0218 
0219 typedef union hubii_ilcsr_u {
0220     u64 icsr_reg_value;
0221     struct {
0222         u64 icsr_rsvd:  22, /* unused */
0223             icsr_max_burst: 10, /* max burst */
0224             icsr_rsvd4:  6, /* reserved */
0225             icsr_max_retry: 10, /* max retry */
0226             icsr_rsvd3:  2, /* reserved */
0227             icsr_lnk_stat:   2, /* link status */
0228             icsr_bm8:    1, /* Bit mode 8 */
0229             icsr_llp_en:     1, /* LLP enable bit */
0230             icsr_rsvd2:  1, /* reserver */
0231             icsr_wrm_reset:  1, /* Warm reset bit */
0232             icsr_rsvd1:  2, /* Data ready offset */
0233             icsr_null_to:    6; /* Null timeout   */
0234 
0235     } icsr_fields_s;
0236 } hubii_ilcsr_t;
0237 
0238 
0239 typedef union hubii_iowa_u {
0240     u64 iowa_reg_value;
0241     struct {
0242         u64 iowa_rsvd:  48, /* unused */
0243             iowa_wxoac:  8, /* xtalk widget access bits */
0244             iowa_rsvd1:  7, /* xtalk widget access bits */
0245             iowa_w0oac:  1; /* xtalk widget access bits */
0246     } iowa_fields_s;
0247 } hubii_iowa_t;
0248 
0249 typedef union hubii_iiwa_u {
0250     u64 iiwa_reg_value;
0251     struct {
0252         u64 iiwa_rsvd:  48, /* unused */
0253             iiwa_wxiac:  8, /* hub wid access bits */
0254             iiwa_rsvd1:  7, /* reserved */
0255             iiwa_w0iac:  1; /* hub wid0 access */
0256     } iiwa_fields_s;
0257 } hubii_iiwa_t;
0258 
0259 typedef union   hubii_illr_u {
0260     u64 illr_reg_value;
0261     struct {
0262         u64 illr_rsvd:  32, /* unused */
0263             illr_cb_cnt:    16, /* checkbit error count */
0264             illr_sn_cnt:    16; /* sequence number count */
0265     } illr_fields_s;
0266 } hubii_illr_t;
0267 
0268 /* The structures below are defined to extract and modify the ii
0269 performance registers */
0270 
0271 /* io_perf_sel allows the caller to specify what tests will be
0272    performed */
0273 typedef union io_perf_sel {
0274     u64 perf_sel_reg;
0275     struct {
0276         u64 perf_rsvd  : 48,
0277             perf_icct  :  8,
0278             perf_ippr1 :  4,
0279             perf_ippr0 :  4;
0280     } perf_sel_bits;
0281 } io_perf_sel_t;
0282 
0283 /* io_perf_cnt is to extract the count from the hub registers. Due to
0284    hardware problems there is only one counter, not two. */
0285 
0286 typedef union io_perf_cnt {
0287     u64 perf_cnt;
0288     struct {
0289         u64 perf_rsvd1 : 32,
0290             perf_rsvd2 : 12,
0291             perf_cnt   : 20;
0292     } perf_cnt_bits;
0293 } io_perf_cnt_t;
0294 
0295 #endif /* !__ASSEMBLY__ */
0296 
0297 
0298 #define LNK_STAT_WORKING    0x2
0299 
0300 #define IIO_LLP_CB_MAX  0xffff
0301 #define IIO_LLP_SN_MAX  0xffff
0302 
0303 /* IO PRB Entries */
0304 #define IIO_NUM_IPRBS   (9)
0305 #define IIO_IOPRB_0 0x400198    /* PRB entry 0 */
0306 #define IIO_IOPRB_8 0x4001a0    /* PRB entry 8 */
0307 #define IIO_IOPRB_9 0x4001a8    /* PRB entry 9 */
0308 #define IIO_IOPRB_A 0x4001b0    /* PRB entry a */
0309 #define IIO_IOPRB_B 0x4001b8    /* PRB entry b */
0310 #define IIO_IOPRB_C 0x4001c0    /* PRB entry c */
0311 #define IIO_IOPRB_D 0x4001c8    /* PRB entry d */
0312 #define IIO_IOPRB_E 0x4001d0    /* PRB entry e */
0313 #define IIO_IOPRB_F 0x4001d8    /* PRB entry f */
0314 
0315 
0316 #define IIO_IXCC    0x4001e0    /* Crosstalk credit count timeout */
0317 #define IIO_IXTCC   IIO_IXCC
0318 #define IIO_IMEM    0x4001e8    /* Miscellaneous Enable Mask */
0319 #define IIO_IXTT    0x4001f0    /* Crosstalk tail timeout */
0320 #define IIO_IECLR   0x4001f8    /* IO error clear */
0321 #define IIO_IBCN    0x400200    /* IO BTE CRB count */
0322 
0323 /*
0324  * IIO_IMEM Register fields.
0325  */
0326 #define IIO_IMEM_W0ESD  0x1     /* Widget 0 shut down due to error */
0327 #define IIO_IMEM_B0ESD  (1 << 4)    /* BTE 0 shut down due to error */
0328 #define IIO_IMEM_B1ESD  (1 << 8)    /* BTE 1 Shut down due to error */
0329 
0330 /* PIO Read address Table Entries */
0331 #define IIO_IPCA    0x400300    /* PRB Counter adjust */
0332 #define IIO_NUM_PRTES   8       /* Total number of PRB table entries */
0333 #define IIO_PRTE_0  0x400308    /* PIO Read address table entry 0 */
0334 #define IIO_PRTE(_x)    (IIO_PRTE_0 + (8 * (_x)))
0335 #define IIO_WIDPRTE(x)  IIO_PRTE(((x) - 8)) /* widget ID to its PRTE num */
0336 #define IIO_IPDR    0x400388    /* PIO table entry deallocation */
0337 #define IIO_ICDR    0x400390    /* CRB Entry Deallocation */
0338 #define IIO_IFDR    0x400398    /* IOQ FIFO Depth */
0339 #define IIO_IIAP    0x4003a0    /* IIQ Arbitration Parameters */
0340 #define IIO_IMMR    IIO_IIAP
0341 #define IIO_ICMR    0x4003a8    /* CRB Management Register */
0342 #define IIO_ICCR    0x4003b0    /* CRB Control Register */
0343 #define IIO_ICTO    0x4003b8    /* CRB Time Out Register */
0344 #define IIO_ICTP    0x4003c0    /* CRB Time Out Prescalar */
0345 
0346 
0347 /*
0348  * ICMR register fields
0349  */
0350 #define IIO_ICMR_PC_VLD_SHFT    36
0351 #define IIO_ICMR_PC_VLD_MASK    (0x7fffUL << IIO_ICMR_PC_VLD_SHFT)
0352 
0353 #define IIO_ICMR_CRB_VLD_SHFT   20
0354 #define IIO_ICMR_CRB_VLD_MASK   (0x7fffUL << IIO_ICMR_CRB_VLD_SHFT)
0355 
0356 #define IIO_ICMR_FC_CNT_SHFT    16
0357 #define IIO_ICMR_FC_CNT_MASK    (0xf << IIO_ICMR_FC_CNT_SHFT)
0358 
0359 #define IIO_ICMR_C_CNT_SHFT 4
0360 #define IIO_ICMR_C_CNT_MASK (0xf << IIO_ICMR_C_CNT_SHFT)
0361 
0362 #define IIO_ICMR_P_CNT_SHFT 0
0363 #define IIO_ICMR_P_CNT_MASK (0xf << IIO_ICMR_P_CNT_SHFT)
0364 
0365 #define IIO_ICMR_PRECISE    (1UL << 52)
0366 #define IIO_ICMR_CLR_RPPD   (1UL << 13)
0367 #define IIO_ICMR_CLR_RQPD   (1UL << 12)
0368 
0369 /*
0370  * IIO PIO Deallocation register field masks : (IIO_IPDR)
0371  */
0372 #define IIO_IPDR_PND    (1 << 4)
0373 
0374 /*
0375  * IIO CRB deallocation register field masks: (IIO_ICDR)
0376  */
0377 #define IIO_ICDR_PND    (1 << 4)
0378 
0379 /*
0380  * IIO CRB control register Fields: IIO_ICCR
0381  */
0382 #define IIO_ICCR_PENDING    (0x10000)
0383 #define IIO_ICCR_CMD_MASK   (0xFF)
0384 #define IIO_ICCR_CMD_SHFT   (7)
0385 #define IIO_ICCR_CMD_NOP    (0x0)   /* No Op */
0386 #define IIO_ICCR_CMD_WAKE   (0x100) /* Reactivate CRB entry and process */
0387 #define IIO_ICCR_CMD_TIMEOUT    (0x200) /* Make CRB timeout & mark invalid */
0388 #define IIO_ICCR_CMD_EJECT  (0x400) /* Contents of entry written to memory
0389                      * via a WB
0390                      */
0391 #define IIO_ICCR_CMD_FLUSH  (0x800)
0392 
0393 /*
0394  * CRB manipulation macros
0395  *  The CRB macros are slightly complicated, since there are up to
0396  *  four registers associated with each CRB entry.
0397  */
0398 #define IIO_NUM_CRBS        15  /* Number of CRBs */
0399 #define IIO_NUM_NORMAL_CRBS 12  /* Number of regular CRB entries */
0400 #define IIO_NUM_PC_CRBS     4   /* Number of partial cache CRBs */
0401 #define IIO_ICRB_OFFSET     8
0402 #define IIO_ICRB_0      0x400400
0403 /* XXX - This is now tuneable:
0404     #define IIO_FIRST_PC_ENTRY 12
0405  */
0406 
0407 #define IIO_ICRB_A(_x)  (IIO_ICRB_0 + (4 * IIO_ICRB_OFFSET * (_x)))
0408 #define IIO_ICRB_B(_x)  (IIO_ICRB_A(_x) + 1*IIO_ICRB_OFFSET)
0409 #define IIO_ICRB_C(_x)  (IIO_ICRB_A(_x) + 2*IIO_ICRB_OFFSET)
0410 #define IIO_ICRB_D(_x)  (IIO_ICRB_A(_x) + 3*IIO_ICRB_OFFSET)
0411 
0412 /* XXX - IBUE register coming for Hub 2 */
0413 
0414 /*
0415  *
0416  * CRB Register description.
0417  *
0418  * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
0419  * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
0420  * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
0421  * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
0422  * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
0423  *
0424  * Many of the fields in CRB are status bits used by hardware
0425  * for implementation of the protocol. It's very dangerous to
0426  * mess around with the CRB registers.
0427  *
0428  * It's OK to read the CRB registers and try to make sense out of the
0429  * fields in CRB.
0430  *
0431  * Updating CRB requires all activities in Hub IIO to be quiesced.
0432  * otherwise, a write to CRB could corrupt other CRB entries.
0433  * CRBs are here only as a back door peek to hub IIO's status.
0434  * Quiescing implies  no dmas no PIOs
0435  * either directly from the cpu or from sn0net.
0436  * this is not something that can be done easily. So, AVOID updating
0437  * CRBs.
0438  */
0439 
0440 /*
0441  * Fields in CRB Register A
0442  */
0443 #ifndef __ASSEMBLY__
0444 typedef union icrba_u {
0445     u64 reg_value;
0446     struct {
0447         u64 resvd:  6,
0448             stall_bte0: 1,  /* Stall BTE 0 */
0449             stall_bte1: 1,  /* Stall BTE 1 */
0450             error:  1,  /* CRB has an error */
0451             ecode:  3,  /* Error Code       */
0452             lnetuce: 1, /* SN0net Uncorrectable error */
0453             mark:   1,  /* CRB Has been marked  */
0454             xerr:   1,  /* Error bit set in xtalk header */
0455             sidn:   4,  /* SIDN field from xtalk    */
0456             tnum:   5,  /* TNUM field in xtalk      */
0457             addr:   38, /* Address of request   */
0458             valid:  1,  /* Valid status     */
0459             iow:    1;  /* IO Write operation   */
0460     } icrba_fields_s;
0461 } icrba_t;
0462 
0463 /* This is an alternate typedef for the HUB1 CRB A in order to allow
0464    runtime selection of the format based on the REV_ID field of the
0465    NI_STATUS_REV_ID register. */
0466 typedef union h1_icrba_u {
0467     u64 reg_value;
0468 
0469     struct {
0470         u64 resvd:  6,
0471             unused: 1,  /* Unused but RW!!  */
0472             error:  1,  /* CRB has an error */
0473             ecode:  4,  /* Error Code       */
0474             lnetuce: 1, /* SN0net Uncorrectable error */
0475             mark:   1,  /* CRB Has been marked  */
0476             xerr:   1,  /* Error bit set in xtalk header */
0477             sidn:   4,  /* SIDN field from xtalk    */
0478             tnum:   5,  /* TNUM field in xtalk      */
0479             addr:   38, /* Address of request   */
0480             valid:  1,  /* Valid status     */
0481             iow:    1;  /* IO Write operation   */
0482     } h1_icrba_fields_s;
0483 } h1_icrba_t;
0484 
0485 /* XXX - Is this still right?  Check the spec. */
0486 #define ICRBN_A_CERR_SHFT   54
0487 #define ICRBN_A_ERR_MASK    0x3ff
0488 
0489 #endif /* !__ASSEMBLY__ */
0490 
0491 #define IIO_ICRB_ADDR_SHFT  2   /* Shift to get proper address */
0492 
0493 /*
0494  * values for "ecode" field
0495  */
0496 #define IIO_ICRB_ECODE_DERR 0   /* Directory error due to IIO access */
0497 #define IIO_ICRB_ECODE_PERR 1   /* Poison error on IO access */
0498 #define IIO_ICRB_ECODE_WERR 2   /* Write error by IIO access
0499                      * e.g. WINV to a Read only line.
0500                      */
0501 #define IIO_ICRB_ECODE_AERR 3   /* Access error caused by IIO access */
0502 #define IIO_ICRB_ECODE_PWERR    4   /* Error on partial write   */
0503 #define IIO_ICRB_ECODE_PRERR    5   /* Error on partial read    */
0504 #define IIO_ICRB_ECODE_TOUT 6   /* CRB timeout before deallocating */
0505 #define IIO_ICRB_ECODE_XTERR    7   /* Incoming xtalk pkt had error bit */
0506 
0507 
0508 
0509 /*
0510  * Fields in CRB Register B
0511  */
0512 #ifndef __ASSEMBLY__
0513 typedef union icrbb_u {
0514     u64 reg_value;
0515     struct {
0516         u64 rsvd1:  5,
0517         btenum: 1,  /* BTE to which entry belongs to */
0518         cohtrans: 1,    /* Coherent transaction */
0519         xtsize: 2,  /* Xtalk operation size
0520                  * 0: Double Word
0521                  * 1: 32 Bytes.
0522                  * 2: 128 Bytes,
0523                  * 3: Reserved.
0524                  */
0525         srcnode: 9, /* Source Node ID       */
0526         srcinit: 2, /* Source Initiator:
0527                  * See below for field values.
0528                  */
0529         useold: 1,  /* Use OLD command for processing */
0530         imsgtype: 2,    /* Incoming message type
0531                  * see below for field values
0532                  */
0533         imsg:   8,  /* Incoming message */
0534         initator: 3,    /* Initiator of original request
0535                  * See below for field values.
0536                  */
0537         reqtype: 5, /* Identifies type of request
0538                  * See below for field values.
0539                  */
0540         rsvd2:  7,
0541         ackcnt: 11, /* Invalidate ack count */
0542         resp:   1,  /* data response  given to processor */
0543         ack:    1,  /* indicates data ack received  */
0544         hold:   1,  /* entry is gathering inval acks */
0545         wb_pend:1,  /* waiting for writeback to complete */
0546         intvn:  1,  /* Intervention */
0547         stall_ib: 1,    /* Stall Ibuf (from crosstalk) */
0548         stall_intr: 1;  /* Stall internal interrupts */
0549     } icrbb_field_s;
0550 } icrbb_t;
0551 
0552 /* This is an alternate typedef for the HUB1 CRB B in order to allow
0553    runtime selection of the format based on the REV_ID field of the
0554    NI_STATUS_REV_ID register. */
0555 typedef union h1_icrbb_u {
0556     u64 reg_value;
0557     struct {
0558         u64 rsvd1:  5,
0559             btenum: 1,  /* BTE to which entry belongs to */
0560             cohtrans: 1,    /* Coherent transaction */
0561             xtsize: 2,  /* Xtalk operation size
0562                      * 0: Double Word
0563                      * 1: 32 Bytes.
0564                      * 2: 128 Bytes,
0565                      * 3: Reserved.
0566                      */
0567             srcnode: 9, /* Source Node ID       */
0568             srcinit: 2, /* Source Initiator:
0569                      * See below for field values.
0570                      */
0571             useold: 1,  /* Use OLD command for processing */
0572             imsgtype: 2,    /* Incoming message type
0573                      * see below for field values
0574                      */
0575             imsg:   8,  /* Incoming message */
0576             initator: 3,    /* Initiator of original request
0577                      * See below for field values.
0578                      */
0579             rsvd2:  1,
0580             pcache: 1,  /* entry belongs to partial cache */
0581             reqtype: 5, /* Identifies type of request
0582                      * See below for field values.
0583                      */
0584             stl_ib: 1,  /* stall Ibus coming from xtalk */
0585             stl_intr: 1,    /* Stall internal interrupts */
0586             stl_bte0: 1,    /* Stall BTE 0  */
0587             stl_bte1: 1,    /* Stall BTE 1  */
0588             intrvn: 1,  /* Req was target of intervention */
0589             ackcnt: 11, /* Invalidate ack count */
0590             resp:   1,  /* data response  given to processor */
0591             ack:    1,  /* indicates data ack received  */
0592             hold:   1,  /* entry is gathering inval acks */
0593             wb_pend:1,  /* waiting for writeback to complete */
0594             sleep:  1,  /* xtalk req sleeping till IO-sync */
0595             pnd_reply: 1,   /* replies not issed due to IOQ full */
0596             pnd_req: 1; /* reqs not issued due to IOQ full */
0597     } h1_icrbb_field_s;
0598 } h1_icrbb_t;
0599 
0600 
0601 #define b_imsgtype  icrbb_field_s.imsgtype
0602 #define b_btenum    icrbb_field_s.btenum
0603 #define b_cohtrans  icrbb_field_s.cohtrans
0604 #define b_xtsize    icrbb_field_s.xtsize
0605 #define b_srcnode   icrbb_field_s.srcnode
0606 #define b_srcinit   icrbb_field_s.srcinit
0607 #define b_imsgtype  icrbb_field_s.imsgtype
0608 #define b_imsg      icrbb_field_s.imsg
0609 #define b_initiator icrbb_field_s.initiator
0610 
0611 #endif /* !__ASSEMBLY__ */
0612 
0613 /*
0614  * values for field xtsize
0615  */
0616 #define IIO_ICRB_XTSIZE_DW  0   /* Xtalk operation size is 8 bytes  */
0617 #define IIO_ICRB_XTSIZE_32  1   /* Xtalk operation size is 32 bytes */
0618 #define IIO_ICRB_XTSIZE_128 2   /* Xtalk operation size is 128 bytes */
0619 
0620 /*
0621  * values for field srcinit
0622  */
0623 #define IIO_ICRB_PROC0      0   /* Source of request is Proc 0 */
0624 #define IIO_ICRB_PROC1      1   /* Source of request is Proc 1 */
0625 #define IIO_ICRB_GB_REQ     2   /* Source is Guaranteed BW request */
0626 #define IIO_ICRB_IO_REQ     3   /* Source is Normal IO request  */
0627 
0628 /*
0629  * Values for field imsgtype
0630  */
0631 #define IIO_ICRB_IMSGT_XTALK    0   /* Incoming Message from Xtalk */
0632 #define IIO_ICRB_IMSGT_BTE  1   /* Incoming message from BTE    */
0633 #define IIO_ICRB_IMSGT_SN0NET   2   /* Incoming message from SN0 net */
0634 #define IIO_ICRB_IMSGT_CRB  3   /* Incoming message from CRB ???  */
0635 
0636 /*
0637  * values for field initiator.
0638  */
0639 #define IIO_ICRB_INIT_XTALK 0   /* Message originated in xtalk  */
0640 #define IIO_ICRB_INIT_BTE0  0x1 /* Message originated in BTE 0  */
0641 #define IIO_ICRB_INIT_SN0NET    0x2 /* Message originated in SN0net */
0642 #define IIO_ICRB_INIT_CRB   0x3 /* Message originated in CRB ?  */
0643 #define IIO_ICRB_INIT_BTE1  0x5 /* MEssage originated in BTE 1  */
0644 
0645 /*
0646  * Values for field reqtype.
0647  */
0648 /* XXX - Need to fix this for Hub 2 */
0649 #define IIO_ICRB_REQ_DWRD   0   /* Request type double word */
0650 #define IIO_ICRB_REQ_QCLRD  1   /* Request is Qrtr Caceh line Rd */
0651 #define IIO_ICRB_REQ_BLKRD  2   /* Request is block read    */
0652 #define IIO_ICRB_REQ_RSHU   6   /* Request is BTE block read    */
0653 #define IIO_ICRB_REQ_REXU   7   /* request is BTE Excl Read */
0654 #define IIO_ICRB_REQ_RDEX   8   /* Request is Read Exclusive    */
0655 #define IIO_ICRB_REQ_WINC   9   /* Request is Write Invalidate  */
0656 #define IIO_ICRB_REQ_BWINV  10  /* Request is BTE Winv      */
0657 #define IIO_ICRB_REQ_PIORD  11  /* Request is PIO read      */
0658 #define IIO_ICRB_REQ_PIOWR  12  /* Request is PIO Write     */
0659 #define IIO_ICRB_REQ_PRDM   13  /* Request is Fetch&Op      */
0660 #define IIO_ICRB_REQ_PWRM   14  /* Request is Store &Op     */
0661 #define IIO_ICRB_REQ_PTPWR  15  /* Request is Peer to peer  */
0662 #define IIO_ICRB_REQ_WB     16  /* Request is Write back    */
0663 #define IIO_ICRB_REQ_DEX    17  /* Retained DEX Cache line  */
0664 
0665 /*
0666  * Fields in CRB Register C
0667  */
0668 
0669 #ifndef __ASSEMBLY__
0670 
0671 typedef union icrbc_s {
0672     u64 reg_value;
0673     struct {
0674         u64 rsvd:   6,
0675             sleep:  1,
0676             pricnt: 4,  /* Priority count sent with Read req */
0677             pripsc: 4,  /* Priority Pre scalar  */
0678             bteop:  1,  /* BTE Operation    */
0679             push_be: 34,    /* Push address Byte enable
0680                      * Holds push addr, if CRB is for BTE
0681                      * If CRB belongs to Partial cache,
0682                      * this contains byte enables bits
0683                      * ([47:46] = 0)
0684                      */
0685             suppl:  11, /* Supplemental field   */
0686             barrop: 1,  /* Barrier Op bit set in xtalk req */
0687             doresp: 1,  /* Xtalk req needs a response   */
0688             gbr:    1;  /* GBR bit set in xtalk packet  */
0689     } icrbc_field_s;
0690 } icrbc_t;
0691 
0692 #define c_pricnt    icrbc_field_s.pricnt
0693 #define c_pripsc    icrbc_field_s.pripsc
0694 #define c_bteop     icrbc_field_s.bteop
0695 #define c_bteaddr   icrbc_field_s.push_be   /* push_be field has 2 names */
0696 #define c_benable   icrbc_field_s.push_be   /* push_be field has 2 names */
0697 #define c_suppl     icrbc_field_s.suppl
0698 #define c_barrop    icrbc_field_s.barrop
0699 #define c_doresp    icrbc_field_s.doresp
0700 #define c_gbr   icrbc_field_s.gbr
0701 #endif /* !__ASSEMBLY__ */
0702 
0703 /*
0704  * Fields in CRB Register D
0705  */
0706 
0707 #ifndef __ASSEMBLY__
0708 typedef union icrbd_s {
0709     u64 reg_value;
0710     struct {
0711         u64 rsvd:   38,
0712         toutvld: 1, /* Timeout in progress for this CRB */
0713         ctxtvld: 1, /* Context field below is valid */
0714         rsvd2:  1,
0715         context: 15,    /* Bit vector:
0716                  * Has a bit set for each CRB entry
0717                  * which needs to be deallocated
0718                  * before this CRB entry is processed.
0719                  * Set only for barrier operations.
0720                  */
0721         timeout: 8; /* Timeout Upper 8 bits */
0722     } icrbd_field_s;
0723 } icrbd_t;
0724 
0725 #define icrbd_toutvld   icrbd_field_s.toutvld
0726 #define icrbd_ctxtvld   icrbd_field_s.ctxtvld
0727 #define icrbd_context   icrbd_field_s.context
0728 
0729 
0730 typedef union hubii_ifdr_u {
0731     u64 hi_ifdr_value;
0732     struct {
0733         u64 ifdr_rsvd:  49,
0734             ifdr_maxrp:  7,
0735             ifdr_rsvd1:  1,
0736             ifdr_maxrq:  7;
0737     } hi_ifdr_fields;
0738 } hubii_ifdr_t;
0739 
0740 #endif /* !__ASSEMBLY__ */
0741 
0742 /*
0743  * Hardware designed names for the BTE control registers.
0744  */
0745 #define IIO_IBLS_0  0x410000    /* BTE length/status 0 */
0746 #define IIO_IBSA_0  0x410008    /* BTE source address 0 */
0747 #define IIO_IBDA_0  0x410010    /* BTE destination address 0 */
0748 #define IIO_IBCT_0  0x410018    /* BTE control/terminate 0 */
0749 #define IIO_IBNA_0  0x410020    /* BTE notification address 0 */
0750 #define IIO_IBNR_0  IIO_IBNA_0
0751 #define IIO_IBIA_0  0x410028    /* BTE interrupt address 0 */
0752 
0753 #define IIO_IBLS_1  0x420000    /* BTE length/status 1 */
0754 #define IIO_IBSA_1  0x420008    /* BTE source address 1 */
0755 #define IIO_IBDA_1  0x420010    /* BTE destination address 1 */
0756 #define IIO_IBCT_1  0x420018    /* BTE control/terminate 1 */
0757 #define IIO_IBNA_1  0x420020    /* BTE notification address 1 */
0758 #define IIO_IBNR_1  IIO_IBNA_1
0759 #define IIO_IBIA_1  0x420028    /* BTE interrupt address 1 */
0760 
0761 /*
0762  * More miscellaneous registers
0763  */
0764 #define IIO_IPCR    0x430000    /* Performance Control */
0765 #define IIO_IPPR    0x430008    /* Performance Profiling */
0766 
0767 /*
0768  * IO Error Clear register bit field definitions
0769  */
0770 #define IECLR_BTE1      (1 << 18)  /* clear bte error 1 ??? */
0771 #define IECLR_BTE0      (1 << 17)  /* clear bte error 0 ??? */
0772 #define IECLR_CRAZY     (1 << 16)  /* clear crazy bit in wstat reg */
0773 #define IECLR_PRB_F     (1 << 15)  /* clear err bit in PRB_F reg */
0774 #define IECLR_PRB_E     (1 << 14)  /* clear err bit in PRB_E reg */
0775 #define IECLR_PRB_D     (1 << 13)  /* clear err bit in PRB_D reg */
0776 #define IECLR_PRB_C     (1 << 12)  /* clear err bit in PRB_C reg */
0777 #define IECLR_PRB_B     (1 << 11)  /* clear err bit in PRB_B reg */
0778 #define IECLR_PRB_A     (1 << 10)  /* clear err bit in PRB_A reg */
0779 #define IECLR_PRB_9     (1 << 9)   /* clear err bit in PRB_9 reg */
0780 #define IECLR_PRB_8     (1 << 8)   /* clear err bit in PRB_8 reg */
0781 #define IECLR_PRB_0     (1 << 0)   /* clear err bit in PRB_0 reg */
0782 
0783 /*
0784  * IO PIO Read Table Entry format
0785  */
0786 
0787 #ifndef __ASSEMBLY__
0788 
0789 typedef union iprte_a {
0790     u64 entry;
0791     struct {
0792         u64 rsvd1     : 7,  /* Reserved field       */
0793         valid     : 1,  /* Maps to a timeout entry  */
0794         rsvd2     : 1,
0795         srcnode   : 9,  /* Node which did this PIO  */
0796         initiator : 2,  /* If T5A or T5B or IO      */
0797         rsvd3     : 3,
0798         addr      : 38, /* Physical address of PIO  */
0799         rsvd4     : 3;
0800     } iprte_fields;
0801 } iprte_a_t;
0802 
0803 #define iprte_valid iprte_fields.valid
0804 #define iprte_timeout   iprte_fields.timeout
0805 #define iprte_srcnode   iprte_fields.srcnode
0806 #define iprte_init  iprte_fields.initiator
0807 #define iprte_addr  iprte_fields.addr
0808 
0809 #endif /* !__ASSEMBLY__ */
0810 
0811 #define IPRTE_ADDRSHFT  3
0812 
0813 /*
0814  * Hub IIO PRB Register format.
0815  */
0816 
0817 #ifndef __ASSEMBLY__
0818 /*
0819  * Note: Fields bnakctr, anakctr, xtalkctrmode, ovflow fields are
0820  * "Status" fields, and should only be used in case of clean up after errors.
0821  */
0822 
0823 typedef union iprb_u {
0824     u64 reg_value;
0825     struct {
0826         u64 rsvd1:  15,
0827         error:  1,  /* Widget rcvd wr resp pkt w/ error */
0828         ovflow: 5,  /* Overflow count. perf measurement */
0829         fire_and_forget: 1, /* Launch Write without response */
0830         mode:   2,  /* Widget operation Mode    */
0831         rsvd2:  2,
0832         bnakctr: 14,
0833         rsvd3:  2,
0834         anakctr: 14,
0835         xtalkctr: 8;
0836     } iprb_fields_s;
0837 } iprb_t;
0838 
0839 #define iprb_regval reg_value
0840 
0841 #define iprb_error  iprb_fields_s.error
0842 #define iprb_ovflow iprb_fields_s.ovflow
0843 #define iprb_ff     iprb_fields_s.fire_and_forget
0844 #define iprb_mode   iprb_fields_s.mode
0845 #define iprb_bnakctr    iprb_fields_s.bnakctr
0846 #define iprb_anakctr    iprb_fields_s.anakctr
0847 #define iprb_xtalkctr   iprb_fields_s.xtalkctr
0848 
0849 #endif /* !__ASSEMBLY__ */
0850 
0851 /*
0852  * values for mode field in iprb_t.
0853  * For details of the meanings of NAK and Accept, refer the PIO flow
0854  * document
0855  */
0856 #define IPRB_MODE_NORMAL    (0)
0857 #define IPRB_MODE_COLLECT_A (1) /* PRB in collect A mode */
0858 #define IPRB_MODE_SERVICE_A (2) /* NAK B and Accept A */
0859 #define IPRB_MODE_SERVICE_B (3) /* NAK A and Accept B */
0860 
0861 /*
0862  * IO CRB entry C_A to E_A : Partial (cache) CRBS
0863  */
0864 #ifndef __ASSEMBLY__
0865 typedef union icrbp_a {
0866     u64   ip_reg;       /* the entire register value    */
0867     struct {
0868          u64 error: 1,  /*    63, error occurred        */
0869         ln_uce: 1,  /*    62: uncorrectable memory  */
0870         ln_ae:  1,  /*    61: protection violation  */
0871         ln_werr:1,  /*    60: write access error    */
0872         ln_aerr:1,  /*    59: sn0net: Address error */
0873         ln_perr:1,  /*    58: sn0net: poison error  */
0874         timeout:1,  /*    57: CRB timed out     */
0875         l_bdpkt:1,  /*    56: truncated pkt on sn0net   */
0876         c_bdpkt:1,  /*    55: truncated pkt on xtalk    */
0877         c_err:  1,  /*    54: incoming xtalk req, err set*/
0878         rsvd1: 12,  /* 53-42: reserved          */
0879         valid:  1,  /*    41: Valid status      */
0880         sidn:   4,  /* 40-37: SIDN field of xtalk rqst  */
0881         tnum:   5,  /* 36-32: TNUM of xtalk request */
0882         bo: 1,  /*    31: barrier op set in xtalk rqst*/
0883         resprqd:1,  /*    30: xtalk rqst requires response*/
0884         gbr:    1,  /*    29: gbr bit set in xtalk rqst */
0885         size:   2,  /* 28-27: size of xtalk request */
0886         excl:   4,  /* 26-23: exclusive bit(s)      */
0887         stall:  3,  /* 22-20: stall (xtalk, bte 0/1)    */
0888         intvn:  1,  /*    19: rqst target of intervention*/
0889         resp:   1,  /*    18: Data response given to t5 */
0890         ack:    1,  /*    17: Data ack received.    */
0891         hold:   1,  /*    16: crb gathering invalidate acks*/
0892         wb: 1,  /*    15: writeback pending.    */
0893         ack_cnt:11, /* 14-04: counter of invalidate acks*/
0894         tscaler:4;  /* 03-00: Timeout prescaler     */
0895     } ip_fmt;
0896 } icrbp_a_t;
0897 
0898 #endif /* !__ASSEMBLY__ */
0899 
0900 /*
0901  * A couple of defines to go with the above structure.
0902  */
0903 #define ICRBP_A_CERR_SHFT   54
0904 #define ICRBP_A_ERR_MASK    0x3ff
0905 
0906 #ifndef __ASSEMBLY__
0907 typedef union hubii_idsr {
0908     u64 iin_reg;
0909     struct {
0910         u64 rsvd1 : 35,
0911             isent : 1,
0912             rsvd2 : 3,
0913             ienable: 1,
0914             rsvd  : 7,
0915             node  : 9,
0916             rsvd4 : 1,
0917             level : 7;
0918     } iin_fmt;
0919 } hubii_idsr_t;
0920 #endif /* !__ASSEMBLY__ */
0921 
0922 /*
0923  * IO BTE Length/Status (IIO_IBLS) register bit field definitions
0924  */
0925 #define IBLS_BUSY       (0x1 << 20)
0926 #define IBLS_ERROR_SHFT     16
0927 #define IBLS_ERROR      (0x1 << IBLS_ERROR_SHFT)
0928 #define IBLS_LENGTH_MASK    0xffff
0929 
0930 /*
0931  * IO BTE Control/Terminate register (IBCT) register bit field definitions
0932  */
0933 #define IBCT_POISON     (0x1 << 8)
0934 #define IBCT_NOTIFY     (0x1 << 4)
0935 #define IBCT_ZFIL_MODE      (0x1 << 0)
0936 
0937 /*
0938  * IO BTE Interrupt Address Register (IBIA) register bit field definitions
0939  */
0940 #define IBIA_LEVEL_SHFT     16
0941 #define IBIA_LEVEL_MASK     (0x7f << IBIA_LEVEL_SHFT)
0942 #define IBIA_NODE_ID_SHFT   0
0943 #define IBIA_NODE_ID_MASK   (0x1ff)
0944 
0945 /*
0946  * Miscellaneous hub constants
0947  */
0948 
0949 /* Number of widgets supported by hub */
0950 #define HUB_NUM_WIDGET      9
0951 #define HUB_WIDGET_ID_MIN   0x8
0952 #define HUB_WIDGET_ID_MAX   0xf
0953 
0954 #define HUB_WIDGET_PART_NUM 0xc101
0955 #define MAX_HUBS_PER_XBOW   2
0956 
0957 /*
0958  * Get a hub's widget id from widget control register
0959  */
0960 #define IIO_WCR_WID_GET(nasid)  (REMOTE_HUB_L(nasid, III_WCR) & 0xf)
0961 #define IIO_WST_ERROR_MASK  (UINT64_CAST 1 << 32) /* Widget status error */
0962 
0963 /*
0964  * Number of credits Hub widget has while sending req/response to
0965  * xbow.
0966  * Value of 3 is required by Xbow 1.1
0967  * We may be able to increase this to 4 with Xbow 1.2.
0968  */
0969 #define       HUBII_XBOW_CREDIT       3
0970 #define       HUBII_XBOW_REV2_CREDIT  4
0971 
0972 #endif /* _ASM_SGI_SN_SN0_HUBIO_H */
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