asm/sn/ioc3.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (C) 1999, 2000 Ralf Baechle
0004  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
0005  */
0006 #ifndef MIPS_SN_IOC3_H
0007 #define MIPS_SN_IOC3_H
0008
0009 #include <linux/types.h>
0010
0011 /* serial port register map */
0012 struct ioc3_serialregs {
0013     u32 sscr;
0014     u32 stpir;
0015     u32 stcir;
0016     u32 srpir;
0017     u32 srcir;
0018     u32 srtr;
0019     u32 shadow;
0020 };
0021
0022 /* SUPERIO uart register map */
0023 struct ioc3_uartregs {
0024     u8  iu_lcr;
0025     union {
0026         u8  iu_iir; /* read only */
0027         u8  iu_fcr; /* write only */
0028     };
0029     union {
0030         u8  iu_ier; /* DLAB == 0 */
0031         u8  iu_dlm; /* DLAB == 1 */
0032     };
0033     union {
0034         u8  iu_rbr; /* read only, DLAB == 0 */
0035         u8  iu_thr; /* write only, DLAB == 0 */
0036         u8  iu_dll; /* DLAB == 1 */
0037     };
0038     u8  iu_scr;
0039     u8  iu_msr;
0040     u8  iu_lsr;
0041     u8  iu_mcr;
0042 };
0043
0044 struct ioc3_sioregs {
0045     u8  fill[0x141];    /* starts at 0x141 */
0046
0047     u8  kbdcg;
0048     u8  uartc;
0049
0050     u8  fill0[0x151 - 0x142 - 1];
0051
0052     u8  pp_dcr;
0053     u8  pp_dsr;
0054     u8  pp_data;
0055
0056     u8  fill1[0x159 - 0x153 - 1];
0057
0058     u8  pp_ecr;
0059     u8  pp_cfgb;
0060     u8  pp_fifa;
0061
0062     u8  fill2[0x16a - 0x15b - 1];
0063
0064     u8  rtcdat;
0065     u8  rtcad;
0066
0067     u8  fill3[0x170 - 0x16b - 1];
0068
0069     struct ioc3_uartregs    uartb;  /* 0x20170  */
0070     struct ioc3_uartregs    uarta;  /* 0x20178  */
0071 };
0072
0073 struct ioc3_ethregs {
0074     u32 emcr;       /* 0x000f0  */
0075     u32 eisr;       /* 0x000f4  */
0076     u32 eier;       /* 0x000f8  */
0077     u32 ercsr;      /* 0x000fc  */
0078     u32 erbr_h;     /* 0x00100  */
0079     u32 erbr_l;     /* 0x00104  */
0080     u32 erbar;      /* 0x00108  */
0081     u32 ercir;      /* 0x0010c  */
0082     u32 erpir;      /* 0x00110  */
0083     u32 ertr;       /* 0x00114  */
0084     u32 etcsr;      /* 0x00118  */
0085     u32 ersr;       /* 0x0011c  */
0086     u32 etcdc;      /* 0x00120  */
0087     u32 ebir;       /* 0x00124  */
0088     u32 etbr_h;     /* 0x00128  */
0089     u32 etbr_l;     /* 0x0012c  */
0090     u32 etcir;      /* 0x00130  */
0091     u32 etpir;      /* 0x00134  */
0092     u32 emar_h;     /* 0x00138  */
0093     u32 emar_l;     /* 0x0013c  */
0094     u32 ehar_h;     /* 0x00140  */
0095     u32 ehar_l;     /* 0x00144  */
0096     u32 micr;       /* 0x00148  */
0097     u32 midr_r;     /* 0x0014c  */
0098     u32 midr_w;     /* 0x00150  */
0099 };
0100
0101 struct ioc3_serioregs {
0102     u32 km_csr;     /* 0x0009c  */
0103     u32 k_rd;       /* 0x000a0  */
0104     u32 m_rd;       /* 0x000a4  */
0105     u32 k_wd;       /* 0x000a8  */
0106     u32 m_wd;       /* 0x000ac  */
0107 };
0108
0109 /* Register layout of IOC3 in configuration space.  */
0110 struct ioc3 {
0111     /* PCI Config Space registers  */
0112     u32 pci_id;     /* 0x00000  */
0113     u32 pci_scr;    /* 0x00004  */
0114     u32 pci_rev;    /* 0x00008  */
0115     u32 pci_lat;    /* 0x0000c  */
0116     u32 pci_addr;   /* 0x00010  */
0117     u32 pci_err_addr_l; /* 0x00014  */
0118     u32 pci_err_addr_h; /* 0x00018  */
0119
0120     u32 sio_ir;     /* 0x0001c  */
0121     u32 sio_ies;    /* 0x00020  */
0122     u32 sio_iec;    /* 0x00024  */
0123     u32 sio_cr;     /* 0x00028  */
0124     u32 int_out;    /* 0x0002c  */
0125     u32 mcr;        /* 0x00030  */
0126
0127     /* General Purpose I/O registers  */
0128     u32 gpcr_s;     /* 0x00034  */
0129     u32 gpcr_c;     /* 0x00038  */
0130     u32 gpdr;       /* 0x0003c  */
0131     u32 gppr[16];   /* 0x00040  */
0132
0133     /* Parallel Port Registers  */
0134     u32 ppbr_h_a;   /* 0x00080  */
0135     u32 ppbr_l_a;   /* 0x00084  */
0136     u32 ppcr_a;     /* 0x00088  */
0137     u32 ppcr;       /* 0x0008c  */
0138     u32 ppbr_h_b;   /* 0x00090  */
0139     u32 ppbr_l_b;   /* 0x00094  */
0140     u32 ppcr_b;     /* 0x00098  */
0141
0142     /* Keyboard and Mouse Registers  */
0143     struct ioc3_serioregs   serio;
0144
0145     /* Serial Port Registers  */
0146     u32 sbbr_h;     /* 0x000b0  */
0147     u32 sbbr_l;     /* 0x000b4  */
0148     struct ioc3_serialregs  port_a;
0149     struct ioc3_serialregs  port_b;
0150
0151     /* Ethernet Registers */
0152     struct ioc3_ethregs eth;
0153     u32 pad1[(0x20000 - 0x00154) / 4];
0154
0155     /* SuperIO Registers  XXX */
0156     struct ioc3_sioregs sregs;  /* 0x20000 */
0157     u32 pad2[(0x40000 - 0x20180) / 4];
0158
0159     /* SSRAM Diagnostic Access */
0160     u32 ssram[(0x80000 - 0x40000) / 4];
0161
0162     /* Bytebus device offsets
0163        0x80000 -   Access to the generic devices selected with   DEV0
0164        0x9FFFF     bytebus DEV_SEL_0
0165        0xA0000 -   Access to the generic devices selected with   DEV1
0166        0xBFFFF     bytebus DEV_SEL_1
0167        0xC0000 -   Access to the generic devices selected with   DEV2
0168        0xDFFFF     bytebus DEV_SEL_2
0169        0xE0000 -   Access to the generic devices selected with   DEV3
0170        0xFFFFF     bytebus DEV_SEL_3  */
0171 };
0172
0173
0174 #define PCI_LAT         0xc     /* Latency Timer */
0175 #define PCI_SCR_DROP_MODE_EN    0x00008000  /* drop pios on parity err */
0176 #define UARTA_BASE      0x178
0177 #define UARTB_BASE      0x170
0178
0179 /*
0180  * Bytebus device space
0181  */
0182 #define IOC3_BYTEBUS_DEV0   0x80000L
0183 #define IOC3_BYTEBUS_DEV1   0xa0000L
0184 #define IOC3_BYTEBUS_DEV2   0xc0000L
0185 #define IOC3_BYTEBUS_DEV3   0xe0000L
0186
0187 /*
0188  * Ethernet RX Buffer
0189  */
0190 struct ioc3_erxbuf {
0191     u32 w0;         /* first word (valid,bcnt,cksum) */
0192     u32 err;            /* second word various errors */
0193     /* next comes n bytes of padding */
0194     /* then the received ethernet frame itself */
0195 };
0196
0197 #define ERXBUF_IPCKSUM_MASK 0x0000ffff
0198 #define ERXBUF_BYTECNT_MASK 0x07ff0000
0199 #define ERXBUF_BYTECNT_SHIFT    16
0200 #define ERXBUF_V        0x80000000
0201
0202 #define ERXBUF_CRCERR       0x00000001  /* aka RSV15 */
0203 #define ERXBUF_FRAMERR      0x00000002  /* aka RSV14 */
0204 #define ERXBUF_CODERR       0x00000004  /* aka RSV13 */
0205 #define ERXBUF_INVPREAMB    0x00000008  /* aka RSV18 */
0206 #define ERXBUF_LOLEN        0x00007000  /* aka RSV2_0 */
0207 #define ERXBUF_HILEN        0x03ff0000  /* aka RSV12_3 */
0208 #define ERXBUF_MULTICAST    0x04000000  /* aka RSV16 */
0209 #define ERXBUF_BROADCAST    0x08000000  /* aka RSV17 */
0210 #define ERXBUF_LONGEVENT    0x10000000  /* aka RSV19 */
0211 #define ERXBUF_BADPKT       0x20000000  /* aka RSV20 */
0212 #define ERXBUF_GOODPKT      0x40000000  /* aka RSV21 */
0213 #define ERXBUF_CARRIER      0x80000000  /* aka RSV22 */
0214
0215 /*
0216  * Ethernet TX Descriptor
0217  */
0218 #define ETXD_DATALEN    104
0219 struct ioc3_etxd {
0220     u32 cmd;                /* command field */
0221     u32 bufcnt;             /* buffer counts field */
0222     u64 p1;             /* buffer pointer 1 */
0223     u64 p2;             /* buffer pointer 2 */
0224     u8  data[ETXD_DATALEN];     /* opt. tx data */
0225 };
0226
0227 #define ETXD_BYTECNT_MASK   0x000007ff  /* total byte count */
0228 #define ETXD_INTWHENDONE    0x00001000  /* intr when done */
0229 #define ETXD_D0V        0x00010000  /* data 0 valid */
0230 #define ETXD_B1V        0x00020000  /* buf 1 valid */
0231 #define ETXD_B2V        0x00040000  /* buf 2 valid */
0232 #define ETXD_DOCHECKSUM     0x00080000  /* insert ip cksum */
0233 #define ETXD_CHKOFF_MASK    0x07f00000  /* cksum byte offset */
0234 #define ETXD_CHKOFF_SHIFT   20
0235
0236 #define ETXD_D0CNT_MASK     0x0000007f
0237 #define ETXD_B1CNT_MASK     0x0007ff00
0238 #define ETXD_B1CNT_SHIFT    8
0239 #define ETXD_B2CNT_MASK     0x7ff00000
0240 #define ETXD_B2CNT_SHIFT    20
0241
0242 /* ------------------------------------------------------------------------- */
0243
0244 /* Superio Registers (PIO Access) */
0245 #define IOC3_SIO_BASE       0x20000
0246 #define IOC3_SIO_UARTC      (IOC3_SIO_BASE+0x141)   /* UART Config */
0247 #define IOC3_SIO_KBDCG      (IOC3_SIO_BASE+0x142)   /* KBD Config */
0248 #define IOC3_SIO_PP_BASE    (IOC3_SIO_BASE+PP_BASE) /* Parallel Port */
0249 #define IOC3_SIO_RTC_BASE   (IOC3_SIO_BASE+0x168)   /* Real Time Clock */
0250 #define IOC3_SIO_UB_BASE    (IOC3_SIO_BASE+UARTB_BASE)  /* UART B */
0251 #define IOC3_SIO_UA_BASE    (IOC3_SIO_BASE+UARTA_BASE)  /* UART A */
0252
0253 /* SSRAM Diagnostic Access */
0254 #define IOC3_SSRAM  IOC3_RAM_OFF    /* base of SSRAM diagnostic access */
0255 #define IOC3_SSRAM_LEN  0x40000 /* 256kb (addrspc sz, may not be populated) */
0256 #define IOC3_SSRAM_DM   0x0000ffff  /* data mask */
0257 #define IOC3_SSRAM_PM   0x00010000  /* parity mask */
0258
0259 /* bitmasks for PCI_SCR */
0260 #define PCI_SCR_PAR_RESP_EN 0x00000040  /* enb PCI parity checking */
0261 #define PCI_SCR_SERR_EN     0x00000100  /* enable the SERR# driver */
0262 #define PCI_SCR_DROP_MODE_EN    0x00008000  /* drop pios on parity err */
0263 #define PCI_SCR_RX_SERR     (0x1 << 16)
0264 #define PCI_SCR_DROP_MODE   (0x1 << 17)
0265 #define PCI_SCR_SIG_PAR_ERR (0x1 << 24)
0266 #define PCI_SCR_SIG_TAR_ABRT    (0x1 << 27)
0267 #define PCI_SCR_RX_TAR_ABRT (0x1 << 28)
0268 #define PCI_SCR_SIG_MST_ABRT    (0x1 << 29)
0269 #define PCI_SCR_SIG_SERR    (0x1 << 30)
0270 #define PCI_SCR_PAR_ERR     (0x1 << 31)
0271
0272 /* bitmasks for IOC3_KM_CSR */
0273 #define KM_CSR_K_WRT_PEND 0x00000001    /* kbd port xmitting or resetting */
0274 #define KM_CSR_M_WRT_PEND 0x00000002    /* mouse port xmitting or resetting */
0275 #define KM_CSR_K_LCB      0x00000004    /* Line Cntrl Bit for last KBD write */
0276 #define KM_CSR_M_LCB      0x00000008    /* same for mouse */
0277 #define KM_CSR_K_DATA     0x00000010    /* state of kbd data line */
0278 #define KM_CSR_K_CLK      0x00000020    /* state of kbd clock line */
0279 #define KM_CSR_K_PULL_DATA 0x00000040   /* pull kbd data line low */
0280 #define KM_CSR_K_PULL_CLK 0x00000080    /* pull kbd clock line low */
0281 #define KM_CSR_M_DATA     0x00000100    /* state of ms data line */
0282 #define KM_CSR_M_CLK      0x00000200    /* state of ms clock line */
0283 #define KM_CSR_M_PULL_DATA 0x00000400   /* pull ms data line low */
0284 #define KM_CSR_M_PULL_CLK 0x00000800    /* pull ms clock line low */
0285 #define KM_CSR_EMM_MODE   0x00001000    /* emulation mode */
0286 #define KM_CSR_SIM_MODE   0x00002000    /* clock X8 */
0287 #define KM_CSR_K_SM_IDLE  0x00004000    /* Keyboard is idle */
0288 #define KM_CSR_M_SM_IDLE  0x00008000    /* Mouse is idle */
0289 #define KM_CSR_K_TO   0x00010000    /* Keyboard trying to send/receive */
0290 #define KM_CSR_M_TO   0x00020000    /* Mouse trying to send/receive */
0291 #define KM_CSR_K_TO_EN    0x00040000    /* KM_CSR_K_TO + KM_CSR_K_TO_EN = cause
0292                        SIO_IR to assert */
0293 #define KM_CSR_M_TO_EN    0x00080000    /* KM_CSR_M_TO + KM_CSR_M_TO_EN = cause
0294                        SIO_IR to assert */
0295 #define KM_CSR_K_CLAMP_1  0x00100000    /* Pull K_CLK low aft recv 1 char */
0296 #define KM_CSR_M_CLAMP_1  0x00200000    /* Pull M_CLK low aft recv 1 char */
0297 #define KM_CSR_K_CLAMP_3  0x00400000    /* Pull K_CLK low aft recv 3 chars */
0298 #define KM_CSR_M_CLAMP_3  0x00800000    /* Pull M_CLK low aft recv 3 chars */
0299
0300 /* bitmasks for IOC3_K_RD and IOC3_M_RD */
0301 #define KM_RD_DATA_2    0x000000ff  /* 3rd char recvd since last read */
0302 #define KM_RD_DATA_2_SHIFT 0
0303 #define KM_RD_DATA_1    0x0000ff00  /* 2nd char recvd since last read */
0304 #define KM_RD_DATA_1_SHIFT 8
0305 #define KM_RD_DATA_0    0x00ff0000  /* 1st char recvd since last read */
0306 #define KM_RD_DATA_0_SHIFT 16
0307 #define KM_RD_FRAME_ERR_2 0x01000000    /*  framing or parity error in byte 2 */
0308 #define KM_RD_FRAME_ERR_1 0x02000000    /* same for byte 1 */
0309 #define KM_RD_FRAME_ERR_0 0x04000000    /* same for byte 0 */
0310
0311 #define KM_RD_KBD_MSE   0x08000000  /* 0 if from kbd, 1 if from mouse */
0312 #define KM_RD_OFLO  0x10000000  /* 4th char recvd before this read */
0313 #define KM_RD_VALID_2   0x20000000  /* DATA_2 valid */
0314 #define KM_RD_VALID_1   0x40000000  /* DATA_1 valid */
0315 #define KM_RD_VALID_0   0x80000000  /* DATA_0 valid */
0316 #define KM_RD_VALID_ALL (KM_RD_VALID_0|KM_RD_VALID_1|KM_RD_VALID_2)
0317
0318 /* bitmasks for IOC3_K_WD & IOC3_M_WD */
0319 #define KM_WD_WRT_DATA  0x000000ff  /* write to keyboard/mouse port */
0320 #define KM_WD_WRT_DATA_SHIFT 0
0321
0322 /* bitmasks for serial RX status byte */
0323 #define RXSB_OVERRUN    0x01    /* char(s) lost */
0324 #define RXSB_PAR_ERR    0x02    /* parity error */
0325 #define RXSB_FRAME_ERR  0x04    /* framing error */
0326 #define RXSB_BREAK  0x08    /* break character */
0327 #define RXSB_CTS    0x10    /* state of CTS */
0328 #define RXSB_DCD    0x20    /* state of DCD */
0329 #define RXSB_MODEM_VALID 0x40   /* DCD, CTS and OVERRUN are valid */
0330 #define RXSB_DATA_VALID 0x80    /* data byte, FRAME_ERR PAR_ERR & BREAK valid */
0331
0332 /* bitmasks for serial TX control byte */
0333 #define TXCB_INT_WHEN_DONE 0x20 /* interrupt after this byte is sent */
0334 #define TXCB_INVALID    0x00    /* byte is invalid */
0335 #define TXCB_VALID  0x40    /* byte is valid */
0336 #define TXCB_MCR    0x80    /* data<7:0> to modem control register */
0337 #define TXCB_DELAY  0xc0    /* delay data<7:0> mSec */
0338
0339 /* bitmasks for IOC3_SBBR_L */
0340 #define SBBR_L_SIZE 0x00000001  /* 0 == 1KB rings, 1 == 4KB rings */
0341 #define SBBR_L_BASE 0xfffff000  /* lower serial ring base addr */
0342
0343 /* bitmasks for IOC3_SSCR_<A:B> */
0344 #define SSCR_RX_THRESHOLD 0x000001ff    /* hiwater mark */
0345 #define SSCR_TX_TIMER_BUSY 0x00010000   /* TX timer in progress */
0346 #define SSCR_HFC_EN 0x00020000  /* hardware flow control enabled */
0347 #define SSCR_RX_RING_DCD 0x00040000 /* post RX record on delta-DCD */
0348 #define SSCR_RX_RING_CTS 0x00080000 /* post RX record on delta-CTS */
0349 #define SSCR_HIGH_SPD   0x00100000  /* 4X speed */
0350 #define SSCR_DIAG   0x00200000  /* bypass clock divider for sim */
0351 #define SSCR_RX_DRAIN   0x08000000  /* drain RX buffer to memory */
0352 #define SSCR_DMA_EN 0x10000000  /* enable ring buffer DMA */
0353 #define SSCR_DMA_PAUSE  0x20000000  /* pause DMA */
0354 #define SSCR_PAUSE_STATE 0x40000000 /* sets when PAUSE takes effect */
0355 #define SSCR_RESET  0x80000000  /* reset DMA channels */
0356
0357 /* all producer/consumer pointers are the same bitfield */
0358 #define PROD_CONS_PTR_4K 0x00000ff8 /* for 4K buffers */
0359 #define PROD_CONS_PTR_1K 0x000003f8 /* for 1K buffers */
0360 #define PROD_CONS_PTR_OFF 3
0361
0362 /* bitmasks for IOC3_SRCIR_<A:B> */
0363 #define SRCIR_ARM   0x80000000  /* arm RX timer */
0364
0365 /* bitmasks for IOC3_SRPIR_<A:B> */
0366 #define SRPIR_BYTE_CNT  0x07000000  /* bytes in packer */
0367 #define SRPIR_BYTE_CNT_SHIFT 24
0368
0369 /* bitmasks for IOC3_STCIR_<A:B> */
0370 #define STCIR_BYTE_CNT  0x0f000000  /* bytes in unpacker */
0371 #define STCIR_BYTE_CNT_SHIFT 24
0372
0373 /* bitmasks for IOC3_SHADOW_<A:B> */
0374 #define SHADOW_DR   0x00000001  /* data ready */
0375 #define SHADOW_OE   0x00000002  /* overrun error */
0376 #define SHADOW_PE   0x00000004  /* parity error */
0377 #define SHADOW_FE   0x00000008  /* framing error */
0378 #define SHADOW_BI   0x00000010  /* break interrupt */
0379 #define SHADOW_THRE 0x00000020  /* transmit holding register empty */
0380 #define SHADOW_TEMT 0x00000040  /* transmit shift register empty */
0381 #define SHADOW_RFCE 0x00000080  /* char in RX fifo has an error */
0382 #define SHADOW_DCTS 0x00010000  /* delta clear to send */
0383 #define SHADOW_DDCD 0x00080000  /* delta data carrier detect */
0384 #define SHADOW_CTS  0x00100000  /* clear to send */
0385 #define SHADOW_DCD  0x00800000  /* data carrier detect */
0386 #define SHADOW_DTR  0x01000000  /* data terminal ready */
0387 #define SHADOW_RTS  0x02000000  /* request to send */
0388 #define SHADOW_OUT1 0x04000000  /* 16550 OUT1 bit */
0389 #define SHADOW_OUT2 0x08000000  /* 16550 OUT2 bit */
0390 #define SHADOW_LOOP 0x10000000  /* loopback enabled */
0391
0392 /* bitmasks for IOC3_SRTR_<A:B> */
0393 #define SRTR_CNT    0x00000fff  /* reload value for RX timer */
0394 #define SRTR_CNT_VAL    0x0fff0000  /* current value of RX timer */
0395 #define SRTR_CNT_VAL_SHIFT 16
0396 #define SRTR_HZ     16000   /* SRTR clock frequency */
0397
0398 /* bitmasks for IOC3_SIO_IR, IOC3_SIO_IEC and IOC3_SIO_IES  */
0399 #define SIO_IR_SA_TX_MT     0x00000001  /* Serial port A TX empty */
0400 #define SIO_IR_SA_RX_FULL   0x00000002  /* port A RX buf full */
0401 #define SIO_IR_SA_RX_HIGH   0x00000004  /* port A RX hiwat */
0402 #define SIO_IR_SA_RX_TIMER  0x00000008  /* port A RX timeout */
0403 #define SIO_IR_SA_DELTA_DCD 0x00000010  /* port A delta DCD */
0404 #define SIO_IR_SA_DELTA_CTS 0x00000020  /* port A delta CTS */
0405 #define SIO_IR_SA_INT       0x00000040  /* port A pass-thru intr */
0406 #define SIO_IR_SA_TX_EXPLICIT   0x00000080  /* port A explicit TX thru */
0407 #define SIO_IR_SA_MEMERR    0x00000100  /* port A PCI error */
0408 #define SIO_IR_SB_TX_MT     0x00000200  /* */
0409 #define SIO_IR_SB_RX_FULL   0x00000400  /* */
0410 #define SIO_IR_SB_RX_HIGH   0x00000800  /* */
0411 #define SIO_IR_SB_RX_TIMER  0x00001000  /* */
0412 #define SIO_IR_SB_DELTA_DCD 0x00002000  /* */
0413 #define SIO_IR_SB_DELTA_CTS 0x00004000  /* */
0414 #define SIO_IR_SB_INT       0x00008000  /* */
0415 #define SIO_IR_SB_TX_EXPLICIT   0x00010000  /* */
0416 #define SIO_IR_SB_MEMERR    0x00020000  /* */
0417 #define SIO_IR_PP_INT       0x00040000  /* P port pass-thru intr */
0418 #define SIO_IR_PP_INTA      0x00080000  /* PP context A thru */
0419 #define SIO_IR_PP_INTB      0x00100000  /* PP context B thru */
0420 #define SIO_IR_PP_MEMERR    0x00200000  /* PP PCI error */
0421 #define SIO_IR_KBD_INT      0x00400000  /* kbd/mouse intr */
0422 #define SIO_IR_RT_INT       0x08000000  /* RT output pulse */
0423 #define SIO_IR_GEN_INT1     0x10000000  /* RT input pulse */
0424 #define SIO_IR_GEN_INT_SHIFT    28
0425
0426 /* per device interrupt masks */
0427 #define SIO_IR_SA       (SIO_IR_SA_TX_MT | SIO_IR_SA_RX_FULL | \
0428                  SIO_IR_SA_RX_HIGH | SIO_IR_SA_RX_TIMER | \
0429                  SIO_IR_SA_DELTA_DCD | SIO_IR_SA_DELTA_CTS | \
0430                  SIO_IR_SA_INT | SIO_IR_SA_TX_EXPLICIT | \
0431                  SIO_IR_SA_MEMERR)
0432 #define SIO_IR_SB       (SIO_IR_SB_TX_MT | SIO_IR_SB_RX_FULL | \
0433                  SIO_IR_SB_RX_HIGH | SIO_IR_SB_RX_TIMER | \
0434                  SIO_IR_SB_DELTA_DCD | SIO_IR_SB_DELTA_CTS | \
0435                  SIO_IR_SB_INT | SIO_IR_SB_TX_EXPLICIT | \
0436                  SIO_IR_SB_MEMERR)
0437 #define SIO_IR_PP       (SIO_IR_PP_INT | SIO_IR_PP_INTA | \
0438                  SIO_IR_PP_INTB | SIO_IR_PP_MEMERR)
0439 #define SIO_IR_RT       (SIO_IR_RT_INT | SIO_IR_GEN_INT1)
0440
0441 /* bitmasks for SIO_CR */
0442 #define SIO_CR_SIO_RESET    0x00000001  /* reset the SIO */
0443 #define SIO_CR_SER_A_BASE   0x000000fe  /* DMA poll addr port A */
0444 #define SIO_CR_SER_A_BASE_SHIFT 1
0445 #define SIO_CR_SER_B_BASE   0x00007f00  /* DMA poll addr port B */
0446 #define SIO_CR_SER_B_BASE_SHIFT 8
0447 #define SIO_SR_CMD_PULSE    0x00078000  /* byte bus strobe length */
0448 #define SIO_CR_CMD_PULSE_SHIFT  15
0449 #define SIO_CR_ARB_DIAG     0x00380000  /* cur !enet PCI requet (ro) */
0450 #define SIO_CR_ARB_DIAG_TXA 0x00000000
0451 #define SIO_CR_ARB_DIAG_RXA 0x00080000
0452 #define SIO_CR_ARB_DIAG_TXB 0x00100000
0453 #define SIO_CR_ARB_DIAG_RXB 0x00180000
0454 #define SIO_CR_ARB_DIAG_PP  0x00200000
0455 #define SIO_CR_ARB_DIAG_IDLE    0x00400000  /* 0 -> active request (ro) */
0456
0457 /* bitmasks for INT_OUT */
0458 #define INT_OUT_COUNT   0x0000ffff  /* pulse interval timer */
0459 #define INT_OUT_MODE    0x00070000  /* mode mask */
0460 #define INT_OUT_MODE_0  0x00000000  /* set output to 0 */
0461 #define INT_OUT_MODE_1  0x00040000  /* set output to 1 */
0462 #define INT_OUT_MODE_1PULSE 0x00050000  /* send 1 pulse */
0463 #define INT_OUT_MODE_PULSES 0x00060000  /* send 1 pulse every interval */
0464 #define INT_OUT_MODE_SQW 0x00070000 /* toggle output every interval */
0465 #define INT_OUT_DIAG    0x40000000  /* diag mode */
0466 #define INT_OUT_INT_OUT 0x80000000  /* current state of INT_OUT */
0467
0468 /* time constants for INT_OUT */
0469 #define INT_OUT_NS_PER_TICK (30 * 260)  /* 30 ns PCI clock, divisor=260 */
0470 #define INT_OUT_TICKS_PER_PULSE 3   /* outgoing pulse lasts 3 ticks */
0471 #define INT_OUT_US_TO_COUNT(x)      /* convert uS to a count value */ \
0472     (((x) * 10 + INT_OUT_NS_PER_TICK / 200) *   \
0473      100 / INT_OUT_NS_PER_TICK - 1)
0474 #define INT_OUT_COUNT_TO_US(x)      /* convert count value to uS */ \
0475     (((x) + 1) * INT_OUT_NS_PER_TICK / 1000)
0476 #define INT_OUT_MIN_TICKS 3 /* min period is width of pulse in "ticks" */
0477 #define INT_OUT_MAX_TICKS INT_OUT_COUNT     /* largest possible count */
0478
0479 /* bitmasks for GPCR */
0480 #define GPCR_DIR    0x000000ff  /* tristate pin input or output */
0481 #define GPCR_DIR_PIN(x) (1<<(x))    /* access one of the DIR bits */
0482 #define GPCR_EDGE   0x000f0000  /* extint edge or level sensitive */
0483 #define GPCR_EDGE_PIN(x) (1<<((x)+15))  /* access one of the EDGE bits */
0484
0485 /* values for GPCR */
0486 #define GPCR_INT_OUT_EN 0x00100000  /* enable INT_OUT to pin 0 */
0487 #define GPCR_MLAN_EN    0x00200000  /* enable MCR to pin 8 */
0488 #define GPCR_DIR_SERA_XCVR 0x00000080   /* Port A Transceiver select enable */
0489 #define GPCR_DIR_SERB_XCVR 0x00000040   /* Port B Transceiver select enable */
0490 #define GPCR_DIR_PHY_RST   0x00000020   /* ethernet PHY reset enable */
0491
0492 /* defs for some of the generic I/O pins */
0493 #define GPCR_PHY_RESET      0x20    /* pin is output to PHY reset */
0494 #define GPCR_UARTB_MODESEL  0x40    /* pin is output to port B mode sel */
0495 #define GPCR_UARTA_MODESEL  0x80    /* pin is output to port A mode sel */
0496
0497 #define GPPR_PHY_RESET_PIN  5   /* GIO pin cntrlling phy reset */
0498 #define GPPR_UARTB_MODESEL_PIN  6   /* GIO pin cntrlling uart b mode sel */
0499 #define GPPR_UARTA_MODESEL_PIN  7   /* GIO pin cntrlling uart a mode sel */
0500
0501 /* ethernet */
0502 #define EMCR_DUPLEX     0x00000001
0503 #define EMCR_PROMISC        0x00000002
0504 #define EMCR_PADEN      0x00000004
0505 #define EMCR_RXOFF_MASK     0x000001f8
0506 #define EMCR_RXOFF_SHIFT    3
0507 #define EMCR_RAMPAR     0x00000200
0508 #define EMCR_BADPAR     0x00000800
0509 #define EMCR_BUFSIZ     0x00001000
0510 #define EMCR_TXDMAEN        0x00002000
0511 #define EMCR_TXEN       0x00004000
0512 #define EMCR_RXDMAEN        0x00008000
0513 #define EMCR_RXEN       0x00010000
0514 #define EMCR_LOOPBACK       0x00020000
0515 #define EMCR_ARB_DIAG       0x001c0000
0516 #define EMCR_ARB_DIAG_IDLE  0x00200000
0517 #define EMCR_RST        0x80000000
0518
0519 #define EISR_RXTIMERINT     0x00000001
0520 #define EISR_RXTHRESHINT    0x00000002
0521 #define EISR_RXOFLO     0x00000004
0522 #define EISR_RXBUFOFLO      0x00000008
0523 #define EISR_RXMEMERR       0x00000010
0524 #define EISR_RXPARERR       0x00000020
0525 #define EISR_TXEMPTY        0x00010000
0526 #define EISR_TXRTRY     0x00020000
0527 #define EISR_TXEXDEF        0x00040000
0528 #define EISR_TXLCOL     0x00080000
0529 #define EISR_TXGIANT        0x00100000
0530 #define EISR_TXBUFUFLO      0x00200000
0531 #define EISR_TXEXPLICIT     0x00400000
0532 #define EISR_TXCOLLWRAP     0x00800000
0533 #define EISR_TXDEFERWRAP    0x01000000
0534 #define EISR_TXMEMERR       0x02000000
0535 #define EISR_TXPARERR       0x04000000
0536
0537 #define ERCSR_THRESH_MASK   0x000001ff  /* enet RX threshold */
0538 #define ERCSR_RX_TMR        0x40000000  /* simulation only */
0539 #define ERCSR_DIAG_OFLO     0x80000000  /* simulation only */
0540
0541 #define ERBR_ALIGNMENT      4096
0542 #define ERBR_L_RXRINGBASE_MASK  0xfffff000
0543
0544 #define ERBAR_BARRIER_BIT   0x0100
0545 #define ERBAR_RXBARR_MASK   0xffff0000
0546 #define ERBAR_RXBARR_SHIFT  16
0547
0548 #define ERCIR_RXCONSUME_MASK    0x00000fff
0549
0550 #define ERPIR_RXPRODUCE_MASK    0x00000fff
0551 #define ERPIR_ARM       0x80000000
0552
0553 #define ERTR_CNT_MASK       0x000007ff
0554
0555 #define ETCSR_IPGT_MASK     0x0000007f
0556 #define ETCSR_IPGR1_MASK    0x00007f00
0557 #define ETCSR_IPGR1_SHIFT   8
0558 #define ETCSR_IPGR2_MASK    0x007f0000
0559 #define ETCSR_IPGR2_SHIFT   16
0560 #define ETCSR_NOTXCLK       0x80000000
0561
0562 #define ETCDC_COLLCNT_MASK  0x0000ffff
0563 #define ETCDC_DEFERCNT_MASK 0xffff0000
0564 #define ETCDC_DEFERCNT_SHIFT    16
0565
0566 #define ETBR_ALIGNMENT      (64*1024)
0567 #define ETBR_L_RINGSZ_MASK  0x00000001
0568 #define ETBR_L_RINGSZ128    0
0569 #define ETBR_L_RINGSZ512    1
0570 #define ETBR_L_TXRINGBASE_MASK  0xffffc000
0571
0572 #define ETCIR_TXCONSUME_MASK    0x0000ffff
0573 #define ETCIR_IDLE      0x80000000
0574
0575 #define ETPIR_TXPRODUCE_MASK    0x0000ffff
0576
0577 #define EBIR_TXBUFPROD_MASK 0x0000001f
0578 #define EBIR_TXBUFCONS_MASK 0x00001f00
0579 #define EBIR_TXBUFCONS_SHIFT    8
0580 #define EBIR_RXBUFPROD_MASK 0x007fc000
0581 #define EBIR_RXBUFPROD_SHIFT    14
0582 #define EBIR_RXBUFCONS_MASK 0xff800000
0583 #define EBIR_RXBUFCONS_SHIFT    23
0584
0585 #define MICR_REGADDR_MASK   0x0000001f
0586 #define MICR_PHYADDR_MASK   0x000003e0
0587 #define MICR_PHYADDR_SHIFT  5
0588 #define MICR_READTRIG       0x00000400
0589 #define MICR_BUSY       0x00000800
0590
0591 #define MIDR_DATA_MASK      0x0000ffff
0592
0593 /* subsystem IDs supplied by card detection in pci-xtalk-bridge */
0594 #define IOC3_SUBSYS_IP27_BASEIO6G   0xc300
0595 #define IOC3_SUBSYS_IP27_MIO        0xc301
0596 #define IOC3_SUBSYS_IP27_BASEIO     0xc302
0597 #define IOC3_SUBSYS_IP29_SYSBOARD   0xc303
0598 #define IOC3_SUBSYS_IP30_SYSBOARD   0xc304
0599 #define IOC3_SUBSYS_MENET       0xc305
0600 #define IOC3_SUBSYS_MENET4      0xc306
0601 #define IOC3_SUBSYS_IO7         0xc307
0602 #define IOC3_SUBSYS_IO8         0xc308
0603 #define IOC3_SUBSYS_IO9         0xc309
0604 #define IOC3_SUBSYS_IP34_SYSBOARD   0xc30A
0605
0606 #endif /* MIPS_SN_IOC3_H */