asm/sn/intr.h

0001 /*
0002  * This file is subject to the terms and conditions of the GNU General Public
0003  * License.  See the file "COPYING" in the main directory of this archive
0004  * for more details.
0005  *
0006  * Copyright (C) 1992 - 1997 Silicon Graphics, Inc.
0007  */
0008 #ifndef __ASM_SN_INTR_H
0009 #define __ASM_SN_INTR_H
0010
0011 /*
0012  * Macros to manipulate the interrupt register on the calling hub chip.
0013  */
0014
0015 #define LOCAL_HUB_SEND_INTR(level)              \
0016     LOCAL_HUB_S(PI_INT_PEND_MOD, (0x100 | (level)))
0017 #define REMOTE_HUB_SEND_INTR(hub, level)            \
0018     REMOTE_HUB_S((hub), PI_INT_PEND_MOD, (0x100 | (level)))
0019
0020 /*
0021  * When clearing the interrupt, make sure this clear does make it
0022  * to the hub. Otherwise we could end up losing interrupts.
0023  * We do an uncached load of the int_pend0 register to ensure this.
0024  */
0025
0026 #define LOCAL_HUB_CLR_INTR(level)               \
0027 do {                                \
0028     LOCAL_HUB_S(PI_INT_PEND_MOD, (level));          \
0029     LOCAL_HUB_L(PI_INT_PEND0);              \
0030 } while (0);
0031
0032 #define REMOTE_HUB_CLR_INTR(hub, level)             \
0033 do {                                \
0034     nasid_t  __hub = (hub);                 \
0035                                 \
0036     REMOTE_HUB_S(__hub, PI_INT_PEND_MOD, (level));      \
0037     REMOTE_HUB_L(__hub, PI_INT_PEND0);          \
0038 } while (0);
0039
0040 /*
0041  * Hard-coded interrupt levels:
0042  */
0043
0044 /*
0045  *  L0 = SW1
0046  *  L1 = SW2
0047  *  L2 = INT_PEND0
0048  *  L3 = INT_PEND1
0049  *  L4 = RTC
0050  *  L5 = Profiling Timer
0051  *  L6 = Hub Errors
0052  *  L7 = Count/Compare (T5 counters)
0053  */
0054
0055
0056 /*
0057  * INT_PEND0 hard-coded bits.
0058  */
0059
0060 /*
0061  * INT_PEND0 bits determined by hardware:
0062  */
0063 #define RESERVED_INTR        0  /* What is this bit? */
0064 #define GFX_INTR_A       1
0065 #define GFX_INTR_B       2
0066 #define PG_MIG_INTR      3
0067 #define UART_INTR        4
0068 #define CC_PEND_A        5
0069 #define CC_PEND_B        6
0070
0071 /*
0072  * INT_PEND0 used by the kernel for itself ...
0073  */
0074 #define CPU_RESCHED_A_IRQ    7
0075 #define CPU_RESCHED_B_IRQ    8
0076 #define CPU_CALL_A_IRQ       9
0077 #define CPU_CALL_B_IRQ      10
0078
0079 /*
0080  * INT_PEND1 hard-coded bits:
0081  */
0082 #define NI_BRDCAST_ERR_A    39
0083 #define NI_BRDCAST_ERR_B    40
0084
0085 #define LLP_PFAIL_INTR_A    41  /* see ml/SN/SN0/sysctlr.c */
0086 #define LLP_PFAIL_INTR_B    42
0087
0088 #define TLB_INTR_A      43  /* used for tlb flush random */
0089 #define TLB_INTR_B      44
0090
0091 #define IP27_INTR_0     45  /* Reserved for PROM use */
0092 #define IP27_INTR_1     46  /* do not use in Kernel */
0093 #define IP27_INTR_2     47
0094 #define IP27_INTR_3     48
0095 #define IP27_INTR_4     49
0096 #define IP27_INTR_5     50
0097 #define IP27_INTR_6     51
0098 #define IP27_INTR_7     52
0099
0100 #define BRIDGE_ERROR_INTR   53  /* Setup by PROM to catch   */
0101                     /* Bridge Errors */
0102 #define DEBUG_INTR_A        54
0103 #define DEBUG_INTR_B        55  /* Used by symmon to stop all cpus */
0104 #define IO_ERROR_INTR       57  /* Setup by PROM */
0105 #define CLK_ERR_INTR        58
0106 #define COR_ERR_INTR_A      59
0107 #define COR_ERR_INTR_B      60
0108 #define MD_COR_ERR_INTR     61
0109 #define NI_ERROR_INTR       62
0110 #define MSC_PANIC_INTR      63
0111
0112 #endif /* __ASM_SN_INTR_H */