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0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*  *********************************************************************
0003     *  SB1250 Board Support Package
0004     *
0005     *  UART Constants               File: sb1250_uart.h
0006     *
0007     *  This module contains constants and macros useful for
0008     *  manipulating the SB1250's UARTs
0009     *
0010     *  SB1250 specification level:  User's manual 1/02/02
0011     *
0012     *********************************************************************
0013     *
0014     *  Copyright 2000,2001,2002,2003
0015     *  Broadcom Corporation. All rights reserved.
0016     *
0017     ********************************************************************* */
0018 
0019 
0020 #ifndef _SB1250_UART_H
0021 #define _SB1250_UART_H
0022 
0023 #include <asm/sibyte/sb1250_defs.h>
0024 
0025 /* **********************************************************************
0026    * DUART Registers
0027    ********************************************************************** */
0028 
0029 /*
0030  * DUART Mode Register #1 (Table 10-3)
0031  * Register: DUART_MODE_REG_1_A
0032  * Register: DUART_MODE_REG_1_B
0033  */
0034 
0035 #define S_DUART_BITS_PER_CHAR       0
0036 #define M_DUART_BITS_PER_CHAR       _SB_MAKEMASK(2, S_DUART_BITS_PER_CHAR)
0037 #define V_DUART_BITS_PER_CHAR(x)    _SB_MAKEVALUE(x, S_DUART_BITS_PER_CHAR)
0038 
0039 #define K_DUART_BITS_PER_CHAR_RSV0  0
0040 #define K_DUART_BITS_PER_CHAR_RSV1  1
0041 #define K_DUART_BITS_PER_CHAR_7     2
0042 #define K_DUART_BITS_PER_CHAR_8     3
0043 
0044 #define V_DUART_BITS_PER_CHAR_RSV0  V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_RSV0)
0045 #define V_DUART_BITS_PER_CHAR_RSV1  V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_RSV1)
0046 #define V_DUART_BITS_PER_CHAR_7     V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_7)
0047 #define V_DUART_BITS_PER_CHAR_8     V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_8)
0048 
0049 
0050 #define M_DUART_PARITY_TYPE_EVEN    0x00
0051 #define M_DUART_PARITY_TYPE_ODD     _SB_MAKEMASK1(2)
0052 
0053 #define S_DUART_PARITY_MODE      3
0054 #define M_DUART_PARITY_MODE     _SB_MAKEMASK(2, S_DUART_PARITY_MODE)
0055 #define V_DUART_PARITY_MODE(x)      _SB_MAKEVALUE(x, S_DUART_PARITY_MODE)
0056 
0057 #define K_DUART_PARITY_MODE_ADD       0
0058 #define K_DUART_PARITY_MODE_ADD_FIXED 1
0059 #define K_DUART_PARITY_MODE_NONE      2
0060 
0061 #define V_DUART_PARITY_MODE_ADD       V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_ADD)
0062 #define V_DUART_PARITY_MODE_ADD_FIXED V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_ADD_FIXED)
0063 #define V_DUART_PARITY_MODE_NONE      V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_NONE)
0064 
0065 #define M_DUART_TX_IRQ_SEL_TXRDY    0
0066 #define M_DUART_TX_IRQ_SEL_TXEMPT   _SB_MAKEMASK1(5)
0067 
0068 #define M_DUART_RX_IRQ_SEL_RXRDY    0
0069 #define M_DUART_RX_IRQ_SEL_RXFULL   _SB_MAKEMASK1(6)
0070 
0071 #define M_DUART_RX_RTS_ENA      _SB_MAKEMASK1(7)
0072 
0073 /*
0074  * DUART Mode Register #2 (Table 10-4)
0075  * Register: DUART_MODE_REG_2_A
0076  * Register: DUART_MODE_REG_2_B
0077  */
0078 
0079 #define M_DUART_MODE_RESERVED1      _SB_MAKEMASK(3, 0)   /* ignored */
0080 
0081 #define M_DUART_STOP_BIT_LEN_2      _SB_MAKEMASK1(3)
0082 #define M_DUART_STOP_BIT_LEN_1      0
0083 
0084 #define M_DUART_TX_CTS_ENA      _SB_MAKEMASK1(4)
0085 
0086 
0087 #define M_DUART_MODE_RESERVED2      _SB_MAKEMASK1(5)    /* must be zero */
0088 
0089 #define S_DUART_CHAN_MODE       6
0090 #define M_DUART_CHAN_MODE       _SB_MAKEMASK(2, S_DUART_CHAN_MODE)
0091 #define V_DUART_CHAN_MODE(x)        _SB_MAKEVALUE(x, S_DUART_CHAN_MODE)
0092 
0093 #define K_DUART_CHAN_MODE_NORMAL    0
0094 #define K_DUART_CHAN_MODE_LCL_LOOP  2
0095 #define K_DUART_CHAN_MODE_REM_LOOP  3
0096 
0097 #define V_DUART_CHAN_MODE_NORMAL    V_DUART_CHAN_MODE(K_DUART_CHAN_MODE_NORMAL)
0098 #define V_DUART_CHAN_MODE_LCL_LOOP  V_DUART_CHAN_MODE(K_DUART_CHAN_MODE_LCL_LOOP)
0099 #define V_DUART_CHAN_MODE_REM_LOOP  V_DUART_CHAN_MODE(K_DUART_CHAN_MODE_REM_LOOP)
0100 
0101 /*
0102  * DUART Command Register (Table 10-5)
0103  * Register: DUART_CMD_A
0104  * Register: DUART_CMD_B
0105  */
0106 
0107 #define M_DUART_RX_EN           _SB_MAKEMASK1(0)
0108 #define M_DUART_RX_DIS          _SB_MAKEMASK1(1)
0109 #define M_DUART_TX_EN           _SB_MAKEMASK1(2)
0110 #define M_DUART_TX_DIS          _SB_MAKEMASK1(3)
0111 
0112 #define S_DUART_MISC_CMD        4
0113 #define M_DUART_MISC_CMD        _SB_MAKEMASK(3, S_DUART_MISC_CMD)
0114 #define V_DUART_MISC_CMD(x)     _SB_MAKEVALUE(x, S_DUART_MISC_CMD)
0115 
0116 #define K_DUART_MISC_CMD_NOACTION0   0
0117 #define K_DUART_MISC_CMD_NOACTION1   1
0118 #define K_DUART_MISC_CMD_RESET_RX    2
0119 #define K_DUART_MISC_CMD_RESET_TX    3
0120 #define K_DUART_MISC_CMD_NOACTION4   4
0121 #define K_DUART_MISC_CMD_RESET_BREAK_INT 5
0122 #define K_DUART_MISC_CMD_START_BREAK     6
0123 #define K_DUART_MISC_CMD_STOP_BREAK  7
0124 
0125 #define V_DUART_MISC_CMD_NOACTION0   V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION0)
0126 #define V_DUART_MISC_CMD_NOACTION1   V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION1)
0127 #define V_DUART_MISC_CMD_RESET_RX    V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_RX)
0128 #define V_DUART_MISC_CMD_RESET_TX    V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_TX)
0129 #define V_DUART_MISC_CMD_NOACTION4   V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION4)
0130 #define V_DUART_MISC_CMD_RESET_BREAK_INT V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_BREAK_INT)
0131 #define V_DUART_MISC_CMD_START_BREAK     V_DUART_MISC_CMD(K_DUART_MISC_CMD_START_BREAK)
0132 #define V_DUART_MISC_CMD_STOP_BREAK  V_DUART_MISC_CMD(K_DUART_MISC_CMD_STOP_BREAK)
0133 
0134 #define M_DUART_CMD_RESERVED         _SB_MAKEMASK1(7)
0135 
0136 /*
0137  * DUART Status Register (Table 10-6)
0138  * Register: DUART_STATUS_A
0139  * Register: DUART_STATUS_B
0140  * READ-ONLY
0141  */
0142 
0143 #define M_DUART_RX_RDY          _SB_MAKEMASK1(0)
0144 #define M_DUART_RX_FFUL         _SB_MAKEMASK1(1)
0145 #define M_DUART_TX_RDY          _SB_MAKEMASK1(2)
0146 #define M_DUART_TX_EMT          _SB_MAKEMASK1(3)
0147 #define M_DUART_OVRUN_ERR       _SB_MAKEMASK1(4)
0148 #define M_DUART_PARITY_ERR      _SB_MAKEMASK1(5)
0149 #define M_DUART_FRM_ERR         _SB_MAKEMASK1(6)
0150 #define M_DUART_RCVD_BRK        _SB_MAKEMASK1(7)
0151 
0152 /*
0153  * DUART Baud Rate Register (Table 10-7)
0154  * Register: DUART_CLK_SEL_A
0155  * Register: DUART_CLK_SEL_B
0156  */
0157 
0158 #define M_DUART_CLK_COUNTER     _SB_MAKEMASK(12, 0)
0159 #define V_DUART_BAUD_RATE(x)        (100000000/((x)*20)-1)
0160 
0161 /*
0162  * DUART Data Registers (Table 10-8 and 10-9)
0163  * Register: DUART_RX_HOLD_A
0164  * Register: DUART_RX_HOLD_B
0165  * Register: DUART_TX_HOLD_A
0166  * Register: DUART_TX_HOLD_B
0167  */
0168 
0169 #define M_DUART_RX_DATA         _SB_MAKEMASK(8, 0)
0170 #define M_DUART_TX_DATA         _SB_MAKEMASK(8, 0)
0171 
0172 /*
0173  * DUART Input Port Register (Table 10-10)
0174  * Register: DUART_IN_PORT
0175  */
0176 
0177 #define M_DUART_IN_PIN0_VAL     _SB_MAKEMASK1(0)
0178 #define M_DUART_IN_PIN1_VAL     _SB_MAKEMASK1(1)
0179 #define M_DUART_IN_PIN2_VAL     _SB_MAKEMASK1(2)
0180 #define M_DUART_IN_PIN3_VAL     _SB_MAKEMASK1(3)
0181 #define M_DUART_IN_PIN4_VAL     _SB_MAKEMASK1(4)
0182 #define M_DUART_IN_PIN5_VAL     _SB_MAKEMASK1(5)
0183 #define M_DUART_RIN0_PIN        _SB_MAKEMASK1(6)
0184 #define M_DUART_RIN1_PIN        _SB_MAKEMASK1(7)
0185 
0186 /*
0187  * DUART Input Port Change Status Register (Tables 10-11, 10-12, and 10-13)
0188  * Register: DUART_INPORT_CHNG
0189  */
0190 
0191 #define S_DUART_IN_PIN_VAL      0
0192 #define M_DUART_IN_PIN_VAL      _SB_MAKEMASK(4, S_DUART_IN_PIN_VAL)
0193 
0194 #define S_DUART_IN_PIN_CHNG     4
0195 #define M_DUART_IN_PIN_CHNG     _SB_MAKEMASK(4, S_DUART_IN_PIN_CHNG)
0196 
0197 
0198 /*
0199  * DUART Output port control register (Table 10-14)
0200  * Register: DUART_OPCR
0201  */
0202 
0203 #define M_DUART_OPCR_RESERVED0      _SB_MAKEMASK1(0)   /* must be zero */
0204 #define M_DUART_OPC2_SEL        _SB_MAKEMASK1(1)
0205 #define M_DUART_OPCR_RESERVED1      _SB_MAKEMASK1(2)   /* must be zero */
0206 #define M_DUART_OPC3_SEL        _SB_MAKEMASK1(3)
0207 #define M_DUART_OPCR_RESERVED2      _SB_MAKEMASK(4, 4)  /* must be zero */
0208 
0209 /*
0210  * DUART Aux Control Register (Table 10-15)
0211  * Register: DUART_AUX_CTRL
0212  */
0213 
0214 #define M_DUART_IP0_CHNG_ENA        _SB_MAKEMASK1(0)
0215 #define M_DUART_IP1_CHNG_ENA        _SB_MAKEMASK1(1)
0216 #define M_DUART_IP2_CHNG_ENA        _SB_MAKEMASK1(2)
0217 #define M_DUART_IP3_CHNG_ENA        _SB_MAKEMASK1(3)
0218 #define M_DUART_ACR_RESERVED        _SB_MAKEMASK(4, 4)
0219 
0220 #define M_DUART_CTS_CHNG_ENA        _SB_MAKEMASK1(0)
0221 #define M_DUART_CIN_CHNG_ENA        _SB_MAKEMASK1(2)
0222 
0223 /*
0224  * DUART Interrupt Status Register (Table 10-16)
0225  * Register: DUART_ISR
0226  */
0227 
0228 #define M_DUART_ISR_TX_A        _SB_MAKEMASK1(0)
0229 
0230 #define S_DUART_ISR_RX_A        1
0231 #define M_DUART_ISR_RX_A        _SB_MAKEMASK1(S_DUART_ISR_RX_A)
0232 #define V_DUART_ISR_RX_A(x)     _SB_MAKEVALUE(x, S_DUART_ISR_RX_A)
0233 #define G_DUART_ISR_RX_A(x)     _SB_GETVALUE(x, S_DUART_ISR_RX_A, M_DUART_ISR_RX_A)
0234 
0235 #define M_DUART_ISR_BRK_A       _SB_MAKEMASK1(2)
0236 #define M_DUART_ISR_IN_A        _SB_MAKEMASK1(3)
0237 #define M_DUART_ISR_ALL_A       _SB_MAKEMASK(4, 0)
0238 
0239 #define M_DUART_ISR_TX_B        _SB_MAKEMASK1(4)
0240 #define M_DUART_ISR_RX_B        _SB_MAKEMASK1(5)
0241 #define M_DUART_ISR_BRK_B       _SB_MAKEMASK1(6)
0242 #define M_DUART_ISR_IN_B        _SB_MAKEMASK1(7)
0243 #define M_DUART_ISR_ALL_B       _SB_MAKEMASK(4, 4)
0244 
0245 /*
0246  * DUART Channel A Interrupt Status Register (Table 10-17)
0247  * DUART Channel B Interrupt Status Register (Table 10-18)
0248  * Register: DUART_ISR_A
0249  * Register: DUART_ISR_B
0250  */
0251 
0252 #define M_DUART_ISR_TX          _SB_MAKEMASK1(0)
0253 #define M_DUART_ISR_RX          _SB_MAKEMASK1(1)
0254 #define M_DUART_ISR_BRK         _SB_MAKEMASK1(2)
0255 #define M_DUART_ISR_IN          _SB_MAKEMASK1(3)
0256 #define M_DUART_ISR_ALL         _SB_MAKEMASK(4, 0)
0257 #define M_DUART_ISR_RESERVED        _SB_MAKEMASK(4, 4)
0258 
0259 /*
0260  * DUART Interrupt Mask Register (Table 10-19)
0261  * Register: DUART_IMR
0262  */
0263 
0264 #define M_DUART_IMR_TX_A        _SB_MAKEMASK1(0)
0265 #define M_DUART_IMR_RX_A        _SB_MAKEMASK1(1)
0266 #define M_DUART_IMR_BRK_A       _SB_MAKEMASK1(2)
0267 #define M_DUART_IMR_IN_A        _SB_MAKEMASK1(3)
0268 #define M_DUART_IMR_ALL_A       _SB_MAKEMASK(4, 0)
0269 
0270 #define M_DUART_IMR_TX_B        _SB_MAKEMASK1(4)
0271 #define M_DUART_IMR_RX_B        _SB_MAKEMASK1(5)
0272 #define M_DUART_IMR_BRK_B       _SB_MAKEMASK1(6)
0273 #define M_DUART_IMR_IN_B        _SB_MAKEMASK1(7)
0274 #define M_DUART_IMR_ALL_B       _SB_MAKEMASK(4, 4)
0275 
0276 /*
0277  * DUART Channel A Interrupt Mask Register (Table 10-20)
0278  * DUART Channel B Interrupt Mask Register (Table 10-21)
0279  * Register: DUART_IMR_A
0280  * Register: DUART_IMR_B
0281  */
0282 
0283 #define M_DUART_IMR_TX          _SB_MAKEMASK1(0)
0284 #define M_DUART_IMR_RX          _SB_MAKEMASK1(1)
0285 #define M_DUART_IMR_BRK         _SB_MAKEMASK1(2)
0286 #define M_DUART_IMR_IN          _SB_MAKEMASK1(3)
0287 #define M_DUART_IMR_ALL         _SB_MAKEMASK(4, 0)
0288 #define M_DUART_IMR_RESERVED        _SB_MAKEMASK(4, 4)
0289 
0290 
0291 /*
0292  * DUART Output Port Set Register (Table 10-22)
0293  * Register: DUART_SET_OPR
0294  */
0295 
0296 #define M_DUART_SET_OPR0        _SB_MAKEMASK1(0)
0297 #define M_DUART_SET_OPR1        _SB_MAKEMASK1(1)
0298 #define M_DUART_SET_OPR2        _SB_MAKEMASK1(2)
0299 #define M_DUART_SET_OPR3        _SB_MAKEMASK1(3)
0300 #define M_DUART_OPSR_RESERVED       _SB_MAKEMASK(4, 4)
0301 
0302 /*
0303  * DUART Output Port Clear Register (Table 10-23)
0304  * Register: DUART_CLEAR_OPR
0305  */
0306 
0307 #define M_DUART_CLR_OPR0        _SB_MAKEMASK1(0)
0308 #define M_DUART_CLR_OPR1        _SB_MAKEMASK1(1)
0309 #define M_DUART_CLR_OPR2        _SB_MAKEMASK1(2)
0310 #define M_DUART_CLR_OPR3        _SB_MAKEMASK1(3)
0311 #define M_DUART_OPCR_RESERVED       _SB_MAKEMASK(4, 4)
0312 
0313 /*
0314  * DUART Output Port RTS Register (Table 10-24)
0315  * Register: DUART_OUT_PORT
0316  */
0317 
0318 #define M_DUART_OUT_PIN_SET0        _SB_MAKEMASK1(0)
0319 #define M_DUART_OUT_PIN_SET1        _SB_MAKEMASK1(1)
0320 #define M_DUART_OUT_PIN_CLR0        _SB_MAKEMASK1(2)
0321 #define M_DUART_OUT_PIN_CLR1        _SB_MAKEMASK1(3)
0322 #define M_DUART_OPRR_RESERVED       _SB_MAKEMASK(4, 4)
0323 
0324 #define M_DUART_OUT_PIN_SET(chan) \
0325     (chan == 0 ? M_DUART_OUT_PIN_SET0 : M_DUART_OUT_PIN_SET1)
0326 #define M_DUART_OUT_PIN_CLR(chan) \
0327     (chan == 0 ? M_DUART_OUT_PIN_CLR0 : M_DUART_OUT_PIN_CLR1)
0328 
0329 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
0330 /*
0331  * Full Interrupt Control Register
0332  */
0333 
0334 #define S_DUART_SIG_FULL       _SB_MAKE64(0)
0335 #define M_DUART_SIG_FULL       _SB_MAKEMASK(4, S_DUART_SIG_FULL)
0336 #define V_DUART_SIG_FULL(x)    _SB_MAKEVALUE(x, S_DUART_SIG_FULL)
0337 #define G_DUART_SIG_FULL(x)    _SB_GETVALUE(x, S_DUART_SIG_FULL, M_DUART_SIG_FULL)
0338 
0339 #define S_DUART_INT_TIME       _SB_MAKE64(4)
0340 #define M_DUART_INT_TIME       _SB_MAKEMASK(4, S_DUART_INT_TIME)
0341 #define V_DUART_INT_TIME(x)    _SB_MAKEVALUE(x, S_DUART_INT_TIME)
0342 #define G_DUART_INT_TIME(x)    _SB_GETVALUE(x, S_DUART_INT_TIME, M_DUART_INT_TIME)
0343 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */
0344 
0345 
0346 /* ********************************************************************** */
0347 
0348 
0349 #endif