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OSCL-LXR

 
 

    


0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*  *********************************************************************
0003     *  SB1250 Board Support Package
0004     *
0005     *  Synchronous Serial Constants      File: sb1250_syncser.h
0006     *
0007     *  This module contains constants and macros useful for
0008     *  manipulating the SB1250's Synchronous Serial
0009     *
0010     *  SB1250 specification level:  User's manual 1/02/02
0011     *
0012     *********************************************************************
0013     *
0014     *  Copyright 2000,2001,2002,2003
0015     *  Broadcom Corporation. All rights reserved.
0016     *
0017     ********************************************************************* */
0018 
0019 
0020 #ifndef _SB1250_SYNCSER_H
0021 #define _SB1250_SYNCSER_H
0022 
0023 #include <asm/sibyte/sb1250_defs.h>
0024 
0025 /*
0026  * Serial Mode Configuration Register
0027  */
0028 
0029 #define M_SYNCSER_CRC_MODE         _SB_MAKEMASK1(0)
0030 #define M_SYNCSER_MSB_FIRST        _SB_MAKEMASK1(1)
0031 
0032 #define S_SYNCSER_FLAG_NUM         2
0033 #define M_SYNCSER_FLAG_NUM         _SB_MAKEMASK(4, S_SYNCSER_FLAG_NUM)
0034 #define V_SYNCSER_FLAG_NUM         _SB_MAKEVALUE(x, S_SYNCSER_FLAG_NUM)
0035 
0036 #define M_SYNCSER_FLAG_EN          _SB_MAKEMASK1(6)
0037 #define M_SYNCSER_HDLC_EN          _SB_MAKEMASK1(7)
0038 #define M_SYNCSER_LOOP_MODE        _SB_MAKEMASK1(8)
0039 #define M_SYNCSER_LOOPBACK         _SB_MAKEMASK1(9)
0040 
0041 /*
0042  * Serial Clock Source and Line Interface Mode Register
0043  */
0044 
0045 #define M_SYNCSER_RXCLK_INV        _SB_MAKEMASK1(0)
0046 #define M_SYNCSER_RXCLK_EXT        _SB_MAKEMASK1(1)
0047 
0048 #define S_SYNCSER_RXSYNC_DLY           2
0049 #define M_SYNCSER_RXSYNC_DLY           _SB_MAKEMASK(2, S_SYNCSER_RXSYNC_DLY)
0050 #define V_SYNCSER_RXSYNC_DLY(x)        _SB_MAKEVALUE(x, S_SYNCSER_RXSYNC_DLY)
0051 
0052 #define M_SYNCSER_RXSYNC_LOW           _SB_MAKEMASK1(4)
0053 #define M_SYNCSER_RXSTRB_LOW           _SB_MAKEMASK1(5)
0054 
0055 #define M_SYNCSER_RXSYNC_EDGE          _SB_MAKEMASK1(6)
0056 #define M_SYNCSER_RXSYNC_INT           _SB_MAKEMASK1(7)
0057 
0058 #define M_SYNCSER_TXCLK_INV        _SB_MAKEMASK1(8)
0059 #define M_SYNCSER_TXCLK_EXT        _SB_MAKEMASK1(9)
0060 
0061 #define S_SYNCSER_TXSYNC_DLY           10
0062 #define M_SYNCSER_TXSYNC_DLY           _SB_MAKEMASK(2, S_SYNCSER_TXSYNC_DLY)
0063 #define V_SYNCSER_TXSYNC_DLY(x)        _SB_MAKEVALUE(x, S_SYNCSER_TXSYNC_DLY)
0064 
0065 #define M_SYNCSER_TXSYNC_LOW           _SB_MAKEMASK1(12)
0066 #define M_SYNCSER_TXSTRB_LOW           _SB_MAKEMASK1(13)
0067 
0068 #define M_SYNCSER_TXSYNC_EDGE          _SB_MAKEMASK1(14)
0069 #define M_SYNCSER_TXSYNC_INT           _SB_MAKEMASK1(15)
0070 
0071 /*
0072  * Serial Command Register
0073  */
0074 
0075 #define M_SYNCSER_CMD_RX_EN        _SB_MAKEMASK1(0)
0076 #define M_SYNCSER_CMD_TX_EN        _SB_MAKEMASK1(1)
0077 #define M_SYNCSER_CMD_RX_RESET         _SB_MAKEMASK1(2)
0078 #define M_SYNCSER_CMD_TX_RESET         _SB_MAKEMASK1(3)
0079 #define M_SYNCSER_CMD_TX_PAUSE         _SB_MAKEMASK1(5)
0080 
0081 /*
0082  * Serial DMA Enable Register
0083  */
0084 
0085 #define M_SYNCSER_DMA_RX_EN        _SB_MAKEMASK1(0)
0086 #define M_SYNCSER_DMA_TX_EN        _SB_MAKEMASK1(4)
0087 
0088 /*
0089  * Serial Status Register
0090  */
0091 
0092 #define M_SYNCSER_RX_CRCERR        _SB_MAKEMASK1(0)
0093 #define M_SYNCSER_RX_ABORT         _SB_MAKEMASK1(1)
0094 #define M_SYNCSER_RX_OCTET         _SB_MAKEMASK1(2)
0095 #define M_SYNCSER_RX_LONGFRM           _SB_MAKEMASK1(3)
0096 #define M_SYNCSER_RX_SHORTFRM          _SB_MAKEMASK1(4)
0097 #define M_SYNCSER_RX_OVERRUN           _SB_MAKEMASK1(5)
0098 #define M_SYNCSER_RX_SYNC_ERR          _SB_MAKEMASK1(6)
0099 #define M_SYNCSER_TX_CRCERR        _SB_MAKEMASK1(8)
0100 #define M_SYNCSER_TX_UNDERRUN          _SB_MAKEMASK1(9)
0101 #define M_SYNCSER_TX_SYNC_ERR          _SB_MAKEMASK1(10)
0102 #define M_SYNCSER_TX_PAUSE_COMPLETE    _SB_MAKEMASK1(11)
0103 #define M_SYNCSER_RX_EOP_COUNT         _SB_MAKEMASK1(16)
0104 #define M_SYNCSER_RX_EOP_TIMER         _SB_MAKEMASK1(17)
0105 #define M_SYNCSER_RX_EOP_SEEN          _SB_MAKEMASK1(18)
0106 #define M_SYNCSER_RX_HWM           _SB_MAKEMASK1(19)
0107 #define M_SYNCSER_RX_LWM           _SB_MAKEMASK1(20)
0108 #define M_SYNCSER_RX_DSCR          _SB_MAKEMASK1(21)
0109 #define M_SYNCSER_RX_DERR          _SB_MAKEMASK1(22)
0110 #define M_SYNCSER_TX_EOP_COUNT         _SB_MAKEMASK1(24)
0111 #define M_SYNCSER_TX_EOP_TIMER         _SB_MAKEMASK1(25)
0112 #define M_SYNCSER_TX_EOP_SEEN          _SB_MAKEMASK1(26)
0113 #define M_SYNCSER_TX_HWM           _SB_MAKEMASK1(27)
0114 #define M_SYNCSER_TX_LWM           _SB_MAKEMASK1(28)
0115 #define M_SYNCSER_TX_DSCR          _SB_MAKEMASK1(29)
0116 #define M_SYNCSER_TX_DERR          _SB_MAKEMASK1(30)
0117 #define M_SYNCSER_TX_DZERO         _SB_MAKEMASK1(31)
0118 
0119 /*
0120  * Sequencer Table Entry format
0121  */
0122 
0123 #define M_SYNCSER_SEQ_LAST         _SB_MAKEMASK1(0)
0124 #define M_SYNCSER_SEQ_BYTE         _SB_MAKEMASK1(1)
0125 
0126 #define S_SYNCSER_SEQ_COUNT        2
0127 #define M_SYNCSER_SEQ_COUNT        _SB_MAKEMASK(4, S_SYNCSER_SEQ_COUNT)
0128 #define V_SYNCSER_SEQ_COUNT(x)         _SB_MAKEVALUE(x, S_SYNCSER_SEQ_COUNT)
0129 
0130 #define M_SYNCSER_SEQ_ENABLE           _SB_MAKEMASK1(6)
0131 #define M_SYNCSER_SEQ_STROBE           _SB_MAKEMASK1(7)
0132 
0133 #endif