asm/sgi/mc.h

0001 /*
0002  * This file is subject to the terms and conditions of the GNU General Public
0003  * License. See the file "COPYING" in the main directory of this archive
0004  * for more details.
0005  *
0006  * mc.h: Definitions for SGI Memory Controller
0007  *
0008  * Copyright (C) 1996 David S. Miller
0009  * Copyright (C) 1999 Ralf Baechle
0010  * Copyright (C) 1999 Silicon Graphics, Inc.
0011  */
0012
0013 #ifndef _SGI_MC_H
0014 #define _SGI_MC_H
0015
0016 struct sgimc_regs {
0017     u32 _unused0;
0018     volatile u32 cpuctrl0;  /* CPU control register 0, readwrite */
0019 #define SGIMC_CCTRL0_REFS   0x0000000f /* REFS mask */
0020 #define SGIMC_CCTRL0_EREFRESH   0x00000010 /* Memory refresh enable */
0021 #define SGIMC_CCTRL0_EPERRGIO   0x00000020 /* GIO parity error enable */
0022 #define SGIMC_CCTRL0_EPERRMEM   0x00000040 /* Main mem parity error enable */
0023 #define SGIMC_CCTRL0_EPERRCPU   0x00000080 /* CPU bus parity error enable */
0024 #define SGIMC_CCTRL0_WDOG   0x00000100 /* Watchdog timer enable */
0025 #define SGIMC_CCTRL0_SYSINIT    0x00000200 /* System init bit */
0026 #define SGIMC_CCTRL0_GFXRESET   0x00000400 /* Graphics interface reset */
0027 #define SGIMC_CCTRL0_EISALOCK   0x00000800 /* Lock CPU from memory for EISA */
0028 #define SGIMC_CCTRL0_EPERRSCMD  0x00001000 /* SysCMD bus parity error enable */
0029 #define SGIMC_CCTRL0_IENAB  0x00002000 /* Allow interrupts from MC */
0030 #define SGIMC_CCTRL0_ESNOOP 0x00004000 /* Snooping I/O enable */
0031 #define SGIMC_CCTRL0_EPROMWR    0x00008000 /* Prom writes from cpu enable */
0032 #define SGIMC_CCTRL0_WRESETPMEM 0x00010000 /* Perform warm reset, preserves mem */
0033 #define SGIMC_CCTRL0_LENDIAN    0x00020000 /* Put MC in little-endian mode */
0034 #define SGIMC_CCTRL0_WRESETDMEM 0x00040000 /* Warm reset, destroys mem contents */
0035 #define SGIMC_CCTRL0_CMEMBADPAR 0x02000000 /* Generate bad perr from cpu to mem */
0036 #define SGIMC_CCTRL0_R4KNOCHKPARR 0x04000000 /* Don't chk parity on mem data reads */
0037 #define SGIMC_CCTRL0_GIOBTOB    0x08000000 /* Allow GIO back to back writes */
0038     u32 _unused1;
0039     volatile u32 cpuctrl1;  /* CPU control register 1, readwrite */
0040 #define SGIMC_CCTRL1_EGIOTIMEO  0x00000010 /* GIO bus timeout enable */
0041 #define SGIMC_CCTRL1_FIXEDEHPC  0x00001000 /* Fixed HPC endianness */
0042 #define SGIMC_CCTRL1_LITTLEHPC  0x00002000 /* Little endian HPC */
0043 #define SGIMC_CCTRL1_FIXEDEEXP0 0x00004000 /* Fixed EXP0 endianness */
0044 #define SGIMC_CCTRL1_LITTLEEXP0 0x00008000 /* Little endian EXP0 */
0045 #define SGIMC_CCTRL1_FIXEDEEXP1 0x00010000 /* Fixed EXP1 endianness */
0046 #define SGIMC_CCTRL1_LITTLEEXP1 0x00020000 /* Little endian EXP1 */
0047
0048     u32 _unused2;
0049     volatile u32 watchdogt; /* Watchdog reg rdonly, write clears */
0050
0051     u32 _unused3;
0052     volatile u32 systemid;  /* MC system ID register, readonly */
0053 #define SGIMC_SYSID_MASKREV 0x0000000f /* Revision of MC controller */
0054 #define SGIMC_SYSID_EPRESENT    0x00000010 /* Indicates presence of EISA bus */
0055
0056     u32 _unused4[3];
0057     volatile u32 divider;   /* Divider reg for RPSS */
0058
0059     u32 _unused5;
0060     u32 eeprom;     /* EEPROM byte reg for r4k */
0061 #define SGIMC_EEPROM_PRE    0x00000001 /* eeprom chip PRE pin assertion */
0062 #define SGIMC_EEPROM_CSEL   0x00000002 /* Active high, eeprom chip select */
0063 #define SGIMC_EEPROM_SECLOCK    0x00000004 /* EEPROM serial clock */
0064 #define SGIMC_EEPROM_SDATAO 0x00000008 /* Serial EEPROM data-out */
0065 #define SGIMC_EEPROM_SDATAI 0x00000010 /* Serial EEPROM data-in */
0066
0067     u32 _unused6[3];
0068     volatile u32 rcntpre;   /* Preload refresh counter */
0069
0070     u32 _unused7;
0071     volatile u32 rcounter;  /* Readonly refresh counter */
0072
0073     u32 _unused8[13];
0074     volatile u32 giopar;    /* Parameter word for GIO64 */
0075 #define SGIMC_GIOPAR_HPC64  0x00000001 /* HPC talks to GIO using 64-bits */
0076 #define SGIMC_GIOPAR_GFX64  0x00000002 /* GFX talks to GIO using 64-bits */
0077 #define SGIMC_GIOPAR_EXP064 0x00000004 /* EXP(slot0) talks using 64-bits */
0078 #define SGIMC_GIOPAR_EXP164 0x00000008 /* EXP(slot1) talks using 64-bits */
0079 #define SGIMC_GIOPAR_EISA64 0x00000010 /* EISA bus talks 64-bits to GIO */
0080 #define SGIMC_GIOPAR_HPC264 0x00000020 /* 2nd HPX talks 64-bits to GIO */
0081 #define SGIMC_GIOPAR_RTIMEGFX   0x00000040 /* GFX device has realtime attr */
0082 #define SGIMC_GIOPAR_RTIMEEXP0  0x00000080 /* EXP(slot0) has realtime attr */
0083 #define SGIMC_GIOPAR_RTIMEEXP1  0x00000100 /* EXP(slot1) has realtime attr */
0084 #define SGIMC_GIOPAR_MASTEREISA 0x00000200 /* EISA bus can act as bus master */
0085 #define SGIMC_GIOPAR_ONEBUS 0x00000400 /* Exists one GIO64 pipelined bus */
0086 #define SGIMC_GIOPAR_MASTERGFX  0x00000800 /* GFX can act as a bus master */
0087 #define SGIMC_GIOPAR_MASTEREXP0 0x00001000 /* EXP(slot0) can bus master */
0088 #define SGIMC_GIOPAR_MASTEREXP1 0x00002000 /* EXP(slot1) can bus master */
0089 #define SGIMC_GIOPAR_PLINEEXP0  0x00004000 /* EXP(slot0) has pipeline attr */
0090 #define SGIMC_GIOPAR_PLINEEXP1  0x00008000 /* EXP(slot1) has pipeline attr */
0091
0092     u32 _unused9;
0093     volatile u32 cputp; /* CPU bus arb time period */
0094
0095     u32 _unused10[3];
0096     volatile u32 lbursttp;  /* Time period for long bursts */
0097
0098     /* MC chip can drive up to 4 bank 4 SIMMs each. All SIMMs in bank must
0099      * be the same size. The size encoding for supported SIMMs is bellow */
0100     u32 _unused11[9];
0101     volatile u32 mconfig0;  /* Memory config register zero */
0102     u32 _unused12;
0103     volatile u32 mconfig1;  /* Memory config register one */
0104 #define SGIMC_MCONFIG_BASEADDR  0x000000ff /* Base address of bank*/
0105 #define SGIMC_MCONFIG_RMASK 0x00001f00 /* Ram config bitmask */
0106 #define SGIMC_MCONFIG_BVALID    0x00002000 /* Bank is valid */
0107 #define SGIMC_MCONFIG_SBANKS    0x00004000 /* Number of subbanks */
0108
0109     u32 _unused13;
0110     volatile u32 cmacc;    /* Mem access config for CPU */
0111     u32 _unused14;
0112     volatile u32 gmacc;    /* Mem access config for GIO */
0113
0114     /* This define applies to both cmacc and gmacc registers above. */
0115 #define SGIMC_MACC_ALIASBIG 0x20000000 /* 512MB home for alias */
0116
0117     /* Error address/status regs from GIO and CPU perspectives. */
0118     u32 _unused15;
0119     volatile u32 cerr;  /* Error address reg for CPU */
0120     u32 _unused16;
0121     volatile u32 cstat; /* Status reg for CPU */
0122 #define SGIMC_CSTAT_RD      0x00000100 /* read parity error */
0123 #define SGIMC_CSTAT_PAR     0x00000200 /* CPU parity error */
0124 #define SGIMC_CSTAT_ADDR    0x00000400 /* memory bus error bad addr */
0125 #define SGIMC_CSTAT_SYSAD_PAR   0x00000800 /* sysad parity error */
0126 #define SGIMC_CSTAT_SYSCMD_PAR  0x00001000 /* syscmd parity error */
0127 #define SGIMC_CSTAT_BAD_DATA    0x00002000 /* bad data identifier */
0128 #define SGIMC_CSTAT_PAR_MASK    0x00001f00 /* parity error mask */
0129 #define SGIMC_CSTAT_RD_PAR  (SGIMC_CSTAT_RD | SGIMC_CSTAT_PAR)
0130
0131     u32 _unused17;
0132     volatile u32 gerr;  /* Error address reg for GIO */
0133     u32 _unused18;
0134     volatile u32 gstat; /* Status reg for GIO */
0135 #define SGIMC_GSTAT_RD      0x00000100 /* read parity error */
0136 #define SGIMC_GSTAT_WR      0x00000200 /* write parity error */
0137 #define SGIMC_GSTAT_TIME    0x00000400 /* GIO bus timed out */
0138 #define SGIMC_GSTAT_PROM    0x00000800 /* write to PROM when PROM_EN not set */
0139 #define SGIMC_GSTAT_ADDR    0x00001000 /* parity error on addr cycle */
0140 #define SGIMC_GSTAT_BC      0x00002000 /* parity error on byte count cycle */
0141 #define SGIMC_GSTAT_PIO_RD  0x00004000 /* read data parity on pio */
0142 #define SGIMC_GSTAT_PIO_WR  0x00008000 /* write data parity on pio */
0143
0144     /* Special hard bus locking registers. */
0145     u32 _unused19;
0146     volatile u32 syssembit;     /* Uni-bit system semaphore */
0147     u32 _unused20;
0148     volatile u32 mlock;     /* Global GIO memory access lock */
0149     u32 _unused21;
0150     volatile u32 elock;     /* Locks EISA from GIO accesses */
0151
0152     /* GIO dma control registers. */
0153     u32 _unused22[15];
0154     volatile u32 gio_dma_trans; /* DMA mask to translation GIO addrs */
0155     u32 _unused23;
0156     volatile u32 gio_dma_sbits; /* DMA GIO addr substitution bits */
0157     u32 _unused24;
0158     volatile u32 dma_intr_cause;    /* DMA IRQ cause indicator bits */
0159     u32 _unused25;
0160     volatile u32 dma_ctrl;      /* Main DMA control reg */
0161
0162     /* DMA TLB entry 0 */
0163     u32 _unused26[5];
0164     volatile u32 dtlb_hi0;
0165     u32 _unused27;
0166     volatile u32 dtlb_lo0;
0167
0168     /* DMA TLB entry 1 */
0169     u32 _unused28;
0170     volatile u32 dtlb_hi1;
0171     u32 _unused29;
0172     volatile u32 dtlb_lo1;
0173
0174     /* DMA TLB entry 2 */
0175     u32 _unused30;
0176     volatile u32 dtlb_hi2;
0177     u32 _unused31;
0178     volatile u32 dtlb_lo2;
0179
0180     /* DMA TLB entry 3 */
0181     u32 _unused32;
0182     volatile u32 dtlb_hi3;
0183     u32 _unused33;
0184     volatile u32 dtlb_lo3;
0185
0186     u32 _unused34[0x0392];
0187
0188     u32 _unused35;
0189     volatile u32 rpsscounter;   /* Chirps at 100ns */
0190
0191     u32 _unused36[0x1000/4-2*4];
0192
0193     u32 _unused37;
0194     volatile u32 maddronly;     /* Address DMA goes at */
0195     u32 _unused38;
0196     volatile u32 maddrpdeflts;  /* Same as above, plus set defaults */
0197     u32 _unused39;
0198     volatile u32 dmasz;     /* DMA count */
0199     u32 _unused40;
0200     volatile u32 ssize;     /* DMA stride size */
0201     u32 _unused41;
0202     volatile u32 gmaddronly;    /* Set GIO DMA but don't start trans */
0203     u32 _unused42;
0204     volatile u32 dmaddnpgo;     /* Set GIO DMA addr + start transfer */
0205     u32 _unused43;
0206     volatile u32 dmamode;       /* DMA mode config bit settings */
0207     u32 _unused44;
0208     volatile u32 dmaccount;     /* Zoom and byte count for DMA */
0209     u32 _unused45;
0210     volatile u32 dmastart;      /* Pedal to the metal. */
0211     u32 _unused46;
0212     volatile u32 dmarunning;    /* DMA op is in progress */
0213     u32 _unused47;
0214     volatile u32 maddrdefstart; /* Set dma addr, defaults, and kick it */
0215 };
0216
0217 extern struct sgimc_regs *sgimc;
0218 #define SGIMC_BASE      0x1fa00000  /* physical */
0219
0220 /* Base location of the two ram banks found in IP2[0268] machines. */
0221 #define SGIMC_SEG0_BADDR    0x08000000
0222 #define SGIMC_SEG1_BADDR    0x20000000
0223
0224 /* Maximum size of the above banks are per machine. */
0225 #define SGIMC_SEG0_SIZE_ALL     0x10000000 /* 256MB */
0226 #define SGIMC_SEG1_SIZE_IP20_IP22   0x08000000 /* 128MB */
0227 #define SGIMC_SEG1_SIZE_IP26_IP28   0x20000000 /* 512MB */
0228
0229 extern void sgimc_init(void);
0230
0231 #endif /* _SGI_MC_H */