asm/sgi/ip22.h

0001 /*
0002  * This file is subject to the terms and conditions of the GNU General Public
0003  * License. See the file "COPYING" in the main directory of this archive
0004  * for more details.
0005  *
0006  * ip22.h: Definitions for SGI IP22 machines
0007  *
0008  * Copyright (C) 1996 David S. Miller
0009  * Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle
0010  */
0011
0012 #ifndef _SGI_IP22_H
0013 #define _SGI_IP22_H
0014
0015 /*
0016  * These are the virtual IRQ numbers, we divide all IRQ's into
0017  * 'spaces', the 'space' determines where and how to enable/disable
0018  * that particular IRQ on an SGI machine. HPC DMA and MC DMA interrupts
0019  * are not supported this way. Driver is supposed to allocate HPC/MC
0020  * interrupt as shareable and then look to proper status bit (see
0021  * HAL2 driver). This will prevent many complications, trust me ;-)
0022  */
0023
0024 #include <irq.h>
0025 #include <asm/sgi/ioc.h>
0026
0027 #define SGINT_EISA  0   /* 16 EISA irq levels (Indigo2) */
0028 #define SGINT_CPU   MIPS_CPU_IRQ_BASE   /* MIPS CPU define 8 interrupt sources */
0029 #define SGINT_LOCAL0    (SGINT_CPU+8)   /* 8 local0 irq levels */
0030 #define SGINT_LOCAL1    (SGINT_CPU+16)  /* 8 local1 irq levels */
0031 #define SGINT_LOCAL2    (SGINT_CPU+24)  /* 8 local2 vectored irq levels */
0032 #define SGINT_LOCAL3    (SGINT_CPU+32)  /* 8 local3 vectored irq levels */
0033 #define SGINT_END   (SGINT_CPU+40)  /* End of 'spaces' */
0034
0035 /*
0036  * Individual interrupt definitions for the Indy and Indigo2
0037  */
0038
0039 #define SGI_SOFT_0_IRQ  SGINT_CPU + 0
0040 #define SGI_SOFT_1_IRQ  SGINT_CPU + 1
0041 #define SGI_LOCAL_0_IRQ SGINT_CPU + 2
0042 #define SGI_LOCAL_1_IRQ SGINT_CPU + 3
0043 #define SGI_8254_0_IRQ  SGINT_CPU + 4
0044 #define SGI_8254_1_IRQ  SGINT_CPU + 5
0045 #define SGI_BUSERR_IRQ  SGINT_CPU + 6
0046 #define SGI_TIMER_IRQ   SGINT_CPU + 7
0047
0048 #define SGI_FIFO_IRQ    SGINT_LOCAL0 + 0    /* FIFO full */
0049 #define SGI_GIO_0_IRQ   SGI_FIFO_IRQ        /* GIO-0 */
0050 #define SGI_WD93_0_IRQ  SGINT_LOCAL0 + 1    /* 1st onboard WD93 */
0051 #define SGI_WD93_1_IRQ  SGINT_LOCAL0 + 2    /* 2nd onboard WD93 */
0052 #define SGI_ENET_IRQ    SGINT_LOCAL0 + 3    /* onboard ethernet */
0053 #define SGI_MCDMA_IRQ   SGINT_LOCAL0 + 4    /* MC DMA done */
0054 #define SGI_PARPORT_IRQ SGINT_LOCAL0 + 5    /* Parallel port */
0055 #define SGI_GIO_1_IRQ   SGINT_LOCAL0 + 6    /* GE / GIO-1 / 2nd-HPC */
0056 #define SGI_MAP_0_IRQ   SGINT_LOCAL0 + 7    /* Mappable interrupt 0 */
0057
0058 #define SGI_GPL0_IRQ    SGINT_LOCAL1 + 0    /* General Purpose LOCAL1_N<0> */
0059 #define SGI_PANEL_IRQ   SGINT_LOCAL1 + 1    /* front panel */
0060 #define SGI_GPL2_IRQ    SGINT_LOCAL1 + 2    /* General Purpose LOCAL1_N<2> */
0061 #define SGI_MAP_1_IRQ   SGINT_LOCAL1 + 3    /* Mappable interrupt 1 */
0062 #define SGI_HPCDMA_IRQ  SGINT_LOCAL1 + 4    /* HPC DMA done */
0063 #define SGI_ACFAIL_IRQ  SGINT_LOCAL1 + 5    /* AC fail */
0064 #define SGI_VINO_IRQ    SGINT_LOCAL1 + 6    /* Indy VINO */
0065 #define SGI_GIO_2_IRQ   SGINT_LOCAL1 + 7    /* Vert retrace / GIO-2 */
0066
0067 /* Mapped interrupts. These interrupts may be mapped to either 0, or 1 */
0068 #define SGI_VERT_IRQ    SGINT_LOCAL2 + 0    /* INT3: newport vertical status */
0069 #define SGI_EISA_IRQ    SGINT_LOCAL2 + 3    /* EISA interrupts */
0070 #define SGI_KEYBD_IRQ   SGINT_LOCAL2 + 4    /* keyboard */
0071 #define SGI_SERIAL_IRQ  SGINT_LOCAL2 + 5    /* onboard serial */
0072 #define SGI_GIOEXP0_IRQ (SGINT_LOCAL2 + 6)  /* Indy GIO EXP0 */
0073 #define SGI_GIOEXP1_IRQ (SGINT_LOCAL2 + 7)  /* Indy GIO EXP1 */
0074
0075 #define ip22_is_fullhouse() (sgioc->sysid & SGIOC_SYSID_FULLHOUSE)
0076
0077 extern unsigned short ip22_eeprom_read(unsigned int *ctrl, int reg);
0078 extern unsigned short ip22_nvram_read(int reg);
0079
0080 #endif