asm/sgi/ioc.h

0001 /*
0002  * This file is subject to the terms and conditions of the GNU General Public
0003  * License. See the file "COPYING" in the main directory of this archive
0004  * for more details.
0005  *
0006  * ioc.h: Definitions for SGI I/O Controller
0007  *
0008  * Copyright (C) 1996 David S. Miller
0009  * Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle
0010  * Copyright (C) 2001, 2003 Ladislav Michl
0011  */
0012
0013 #ifndef _SGI_IOC_H
0014 #define _SGI_IOC_H
0015
0016 #include <linux/types.h>
0017 #include <asm/sgi/pi1.h>
0018
0019 /*
0020  * All registers are 8-bit wide aligned on 32-bit boundary. Bad things
0021  * happen if you try word access them. You have been warned.
0022  */
0023
0024 struct sgioc_uart_regs {
0025     u8 _ctrl1[3];
0026     volatile u8 ctrl1;
0027     u8 _data1[3];
0028     volatile u8 data1;
0029     u8 _ctrl2[3];
0030     volatile u8 ctrl2;
0031     u8 _data2[3];
0032     volatile u8 data2;
0033 };
0034
0035 struct sgioc_keyb_regs {
0036     u8 _data[3];
0037     volatile u8 data;
0038     u8 _command[3];
0039     volatile u8 command;
0040 };
0041
0042 struct sgint_regs {
0043     u8 _istat0[3];
0044     volatile u8 istat0;     /* Interrupt status zero */
0045 #define SGINT_ISTAT0_FFULL  0x01
0046 #define SGINT_ISTAT0_SCSI0  0x02
0047 #define SGINT_ISTAT0_SCSI1  0x04
0048 #define SGINT_ISTAT0_ENET   0x08
0049 #define SGINT_ISTAT0_GFXDMA 0x10
0050 #define SGINT_ISTAT0_PPORT  0x20
0051 #define SGINT_ISTAT0_HPC2   0x40
0052 #define SGINT_ISTAT0_LIO2   0x80
0053     u8 _imask0[3];
0054     volatile u8 imask0;     /* Interrupt mask zero */
0055     u8 _istat1[3];
0056     volatile u8 istat1;     /* Interrupt status one */
0057 #define SGINT_ISTAT1_ISDNI  0x01
0058 #define SGINT_ISTAT1_PWR    0x02
0059 #define SGINT_ISTAT1_ISDNH  0x04
0060 #define SGINT_ISTAT1_LIO3   0x08
0061 #define SGINT_ISTAT1_HPC3   0x10
0062 #define SGINT_ISTAT1_AFAIL  0x20
0063 #define SGINT_ISTAT1_VIDEO  0x40
0064 #define SGINT_ISTAT1_GIO2   0x80
0065     u8 _imask1[3];
0066     volatile u8 imask1;     /* Interrupt mask one */
0067     u8 _vmeistat[3];
0068     volatile u8 vmeistat;       /* VME interrupt status */
0069     u8 _cmeimask0[3];
0070     volatile u8 cmeimask0;      /* VME interrupt mask zero */
0071     u8 _cmeimask1[3];
0072     volatile u8 cmeimask1;      /* VME interrupt mask one */
0073     u8 _cmepol[3];
0074     volatile u8 cmepol;     /* VME polarity */
0075     u8 _tclear[3];
0076     volatile u8 tclear;
0077     u8 _errstat[3];
0078     volatile u8 errstat;    /* Error status reg, reserved on INT2 */
0079     u32 _unused0[2];
0080     u8 _tcnt0[3];
0081     volatile u8 tcnt0;      /* counter 0 */
0082     u8 _tcnt1[3];
0083     volatile u8 tcnt1;      /* counter 1 */
0084     u8 _tcnt2[3];
0085     volatile u8 tcnt2;      /* counter 2 */
0086     u8 _tcword[3];
0087     volatile u8 tcword;     /* control word */
0088 #define SGINT_TCWORD_BCD    0x01    /* Use BCD mode for counters */
0089 #define SGINT_TCWORD_MMASK  0x0e    /* Mode bitmask. */
0090 #define SGINT_TCWORD_MITC   0x00    /* IRQ on terminal count (doesn't work) */
0091 #define SGINT_TCWORD_MOS    0x02    /* One-shot IRQ mode. */
0092 #define SGINT_TCWORD_MRGEN  0x04    /* Normal rate generation */
0093 #define SGINT_TCWORD_MSWGEN 0x06    /* Square wave generator mode */
0094 #define SGINT_TCWORD_MSWST  0x08    /* Software strobe */
0095 #define SGINT_TCWORD_MHWST  0x0a    /* Hardware strobe */
0096 #define SGINT_TCWORD_CMASK  0x30    /* Command mask */
0097 #define SGINT_TCWORD_CLAT   0x00    /* Latch command */
0098 #define SGINT_TCWORD_CLSB   0x10    /* LSB read/write */
0099 #define SGINT_TCWORD_CMSB   0x20    /* MSB read/write */
0100 #define SGINT_TCWORD_CALL   0x30    /* Full counter read/write */
0101 #define SGINT_TCWORD_CNT0   0x00    /* Select counter zero */
0102 #define SGINT_TCWORD_CNT1   0x40    /* Select counter one */
0103 #define SGINT_TCWORD_CNT2   0x80    /* Select counter two */
0104 #define SGINT_TCWORD_CRBCK  0xc0    /* Readback command */
0105 };
0106
0107 /*
0108  * The timer is the good old 8254.  Unlike in PCs it's clocked at exactly 1MHz
0109  */
0110 #define SGINT_TIMER_CLOCK   1000000
0111
0112 /*
0113  * This is the constant we're using for calibrating the counter.
0114  */
0115 #define SGINT_TCSAMP_COUNTER    ((SGINT_TIMER_CLOCK / HZ) + 255)
0116
0117 /* We need software copies of these because they are write only. */
0118 extern u8 sgi_ioc_reset, sgi_ioc_write;
0119
0120 struct sgioc_regs {
0121     struct pi1_regs pport;
0122     u32 _unused0[2];
0123     struct sgioc_uart_regs uart;
0124     struct sgioc_keyb_regs kbdmouse;
0125     u8 _gcsel[3];
0126     volatile u8 gcsel;
0127     u8 _genctrl[3];
0128     volatile u8 genctrl;
0129     u8 _panel[3];
0130     volatile u8 panel;
0131 #define SGIOC_PANEL_POWERON 0x01
0132 #define SGIOC_PANEL_POWERINTR   0x02
0133 #define SGIOC_PANEL_VOLDNINTR   0x10
0134 #define SGIOC_PANEL_VOLDNHOLD   0x20
0135 #define SGIOC_PANEL_VOLUPINTR   0x40
0136 #define SGIOC_PANEL_VOLUPHOLD   0x80
0137     u32 _unused1;
0138     u8 _sysid[3];
0139     volatile u8 sysid;
0140 #define SGIOC_SYSID_FULLHOUSE   0x01
0141 #define SGIOC_SYSID_BOARDREV(x) (((x) & 0x1e) >> 1)
0142 #define SGIOC_SYSID_CHIPREV(x)  (((x) & 0xe0) >> 5)
0143     u32 _unused2;
0144     u8 _read[3];
0145     volatile u8 read;
0146     u32 _unused3;
0147     u8 _dmasel[3];
0148     volatile u8 dmasel;
0149 #define SGIOC_DMASEL_SCLK10MHZ  0x00    /* use 10MHZ serial clock */
0150 #define SGIOC_DMASEL_ISDNB  0x01    /* enable isdn B */
0151 #define SGIOC_DMASEL_ISDNA  0x02    /* enable isdn A */
0152 #define SGIOC_DMASEL_PPORT  0x04    /* use parallel DMA */
0153 #define SGIOC_DMASEL_SCLK667MHZ 0x10    /* use 6.67MHZ serial clock */
0154 #define SGIOC_DMASEL_SCLKEXT    0x20    /* use external serial clock */
0155     u32 _unused4;
0156     u8 _reset[3];
0157     volatile u8 reset;
0158 #define SGIOC_RESET_PPORT   0x01    /* 0=parport reset, 1=nornal */
0159 #define SGIOC_RESET_KBDMOUSE    0x02    /* 0=kbdmouse reset, 1=normal */
0160 #define SGIOC_RESET_EISA    0x04    /* 0=eisa reset, 1=normal */
0161 #define SGIOC_RESET_ISDN    0x08    /* 0=isdn reset, 1=normal */
0162 #define SGIOC_RESET_LC0OFF  0x10    /* guiness: turn led off (red, else green) */
0163 #define SGIOC_RESET_LC1OFF  0x20    /* guiness: turn led off (green, else amber) */
0164     u32 _unused5;
0165     u8 _write[3];
0166     volatile u8 write;
0167 #define SGIOC_WRITE_NTHRESH 0x01    /* use 4.5db threshold */
0168 #define SGIOC_WRITE_TPSPEED 0x02    /* use 100ohm TP speed */
0169 #define SGIOC_WRITE_EPSEL   0x04    /* force cable mode: 1=AUI 0=TP */
0170 #define SGIOC_WRITE_EASEL   0x08    /* 1=autoselect 0=manual cable selection */
0171 #define SGIOC_WRITE_U1AMODE 0x10    /* 1=PC 0=MAC UART mode */
0172 #define SGIOC_WRITE_U0AMODE 0x20    /* 1=PC 0=MAC UART mode */
0173 #define SGIOC_WRITE_MLO     0x40    /* 1=4.75V 0=+5V */
0174 #define SGIOC_WRITE_MHI     0x80    /* 1=5.25V 0=+5V */
0175     u32 _unused6;
0176     struct sgint_regs int3;
0177     u32 _unused7[16];
0178     volatile u32 extio;     /* FullHouse only */
0179 #define EXTIO_S0_IRQ_3      0x8000  /* S0: vid.vsync */
0180 #define EXTIO_S0_IRQ_2      0x4000  /* S0: gfx.fifofull */
0181 #define EXTIO_S0_IRQ_1      0x2000  /* S0: gfx.int */
0182 #define EXTIO_S0_RETRACE    0x1000
0183 #define EXTIO_SG_IRQ_3      0x0800  /* SG: vid.vsync */
0184 #define EXTIO_SG_IRQ_2      0x0400  /* SG: gfx.fifofull */
0185 #define EXTIO_SG_IRQ_1      0x0200  /* SG: gfx.int */
0186 #define EXTIO_SG_RETRACE    0x0100
0187 #define EXTIO_GIO_33MHZ     0x0080
0188 #define EXTIO_EISA_BUSERR   0x0040
0189 #define EXTIO_MC_BUSERR     0x0020
0190 #define EXTIO_HPC3_BUSERR   0x0010
0191 #define EXTIO_S0_STAT_1     0x0008
0192 #define EXTIO_S0_STAT_0     0x0004
0193 #define EXTIO_SG_STAT_1     0x0002
0194 #define EXTIO_SG_STAT_0     0x0001
0195 };
0196
0197 extern struct sgioc_regs *sgioc;
0198 extern struct sgint_regs *sgint;
0199
0200 #endif