asm/sgi/hpc3.h

0001 /*
0002  * This file is subject to the terms and conditions of the GNU General Public
0003  * License. See the file "COPYING" in the main directory of this archive
0004  * for more details.
0005  *
0006  * hpc3.h: Definitions for SGI HPC3 controller
0007  *
0008  * Copyright (C) 1996 David S. Miller
0009  * Copyright (C) 1998 Ralf Baechle
0010  */
0011
0012 #ifndef _SGI_HPC3_H
0013 #define _SGI_HPC3_H
0014
0015 #include <linux/types.h>
0016 #include <asm/page.h>
0017
0018 /* An HPC DMA descriptor. */
0019 struct hpc_dma_desc {
0020     u32 pbuf;   /* physical address of data buffer */
0021     u32 cntinfo;    /* counter and info bits */
0022 #define HPCDMA_EOX  0x80000000 /* last desc in chain for tx */
0023 #define HPCDMA_EOR  0x80000000 /* last desc in chain for rx */
0024 #define HPCDMA_EOXP 0x40000000 /* end of packet for tx */
0025 #define HPCDMA_EORP 0x40000000 /* end of packet for rx */
0026 #define HPCDMA_XIE  0x20000000 /* irq generated when at end of this desc */
0027 #define HPCDMA_XIU  0x01000000 /* Tx buffer in use by CPU. */
0028 #define HPCDMA_EIPC 0x00ff0000 /* SEEQ ethernet special xternal bytecount */
0029 #define HPCDMA_ETXD 0x00008000 /* set to one by HPC when packet tx'd */
0030 #define HPCDMA_OWN  0x00004000 /* Denotes ring buffer ownership on rx */
0031 #define HPCDMA_BCNT 0x00003fff /* size in bytes of this dma buffer */
0032
0033     u32 pnext;  /* paddr of next hpc_dma_desc if any */
0034 };
0035
0036 /* The set of regs for each HPC3 PBUS DMA channel. */
0037 struct hpc3_pbus_dmacregs {
0038     volatile u32 pbdma_bptr;    /* pbus dma channel buffer ptr */
0039     volatile u32 pbdma_dptr;    /* pbus dma channel desc ptr */
0040     u32 _unused0[0x1000/4 - 2]; /* padding */
0041     volatile u32 pbdma_ctrl;    /* pbus dma channel control register has
0042                      * completely different meaning for read
0043                      * compared with write */
0044     /* read */
0045 #define HPC3_PDMACTRL_INT   0x00000001 /* interrupt (cleared after read) */
0046 #define HPC3_PDMACTRL_ISACT 0x00000002 /* channel active */
0047     /* write */
0048 #define HPC3_PDMACTRL_SEL   0x00000002 /* little endian transfer */
0049 #define HPC3_PDMACTRL_RCV   0x00000004 /* direction is receive */
0050 #define HPC3_PDMACTRL_FLSH  0x00000008 /* enable flush for receive DMA */
0051 #define HPC3_PDMACTRL_ACT   0x00000010 /* start dma transfer */
0052 #define HPC3_PDMACTRL_LD    0x00000020 /* load enable for ACT */
0053 #define HPC3_PDMACTRL_RT    0x00000040 /* Use realtime GIO bus servicing */
0054 #define HPC3_PDMACTRL_HW    0x0000ff00 /* DMA High-water mark */
0055 #define HPC3_PDMACTRL_FB    0x003f0000 /* Ptr to beginning of fifo */
0056 #define HPC3_PDMACTRL_FE    0x3f000000 /* Ptr to end of fifo */
0057
0058     u32 _unused1[0x1000/4 - 1]; /* padding */
0059 };
0060
0061 /* The HPC3 SCSI registers, this does not include external ones. */
0062 struct hpc3_scsiregs {
0063     volatile u32 cbptr; /* current dma buffer ptr, diagnostic use only */
0064     volatile u32 ndptr; /* next dma descriptor ptr */
0065     u32 _unused0[0x1000/4 - 2]; /* padding */
0066     volatile u32 bcd;   /* byte count info */
0067 #define HPC3_SBCD_BCNTMSK 0x00003fff /* bytes to transfer from/to memory */
0068 #define HPC3_SBCD_XIE     0x00004000 /* Send IRQ when done with cur buf */
0069 #define HPC3_SBCD_EOX     0x00008000 /* Indicates this is last buf in chain */
0070
0071     volatile u32 ctrl;    /* control register */
0072 #define HPC3_SCTRL_IRQ    0x01 /* IRQ asserted, either dma done or parity */
0073 #define HPC3_SCTRL_ENDIAN 0x02 /* DMA endian mode, 0=big 1=little */
0074 #define HPC3_SCTRL_DIR    0x04 /* DMA direction, 1=dev2mem 0=mem2dev */
0075 #define HPC3_SCTRL_FLUSH  0x08 /* Tells HPC3 to flush scsi fifos */
0076 #define HPC3_SCTRL_ACTIVE 0x10 /* SCSI DMA channel is active */
0077 #define HPC3_SCTRL_AMASK  0x20 /* DMA active inhibits PIO */
0078 #define HPC3_SCTRL_CRESET 0x40 /* Resets dma channel and external controller */
0079 #define HPC3_SCTRL_PERR   0x80 /* Bad parity on HPC3 iface to scsi controller */
0080
0081     volatile u32 gfptr; /* current GIO fifo ptr */
0082     volatile u32 dfptr; /* current device fifo ptr */
0083     volatile u32 dconfig;   /* DMA configuration register */
0084 #define HPC3_SDCFG_HCLK 0x00001 /* Enable DMA half clock mode */
0085 #define HPC3_SDCFG_D1   0x00006 /* Cycles to spend in D1 state */
0086 #define HPC3_SDCFG_D2   0x00038 /* Cycles to spend in D2 state */
0087 #define HPC3_SDCFG_D3   0x001c0 /* Cycles to spend in D3 state */
0088 #define HPC3_SDCFG_HWAT 0x00e00 /* DMA high water mark */
0089 #define HPC3_SDCFG_HW   0x01000 /* Enable 16-bit halfword DMA accesses to scsi */
0090 #define HPC3_SDCFG_SWAP 0x02000 /* Byte swap all DMA accesses */
0091 #define HPC3_SDCFG_EPAR 0x04000 /* Enable parity checking for DMA */
0092 #define HPC3_SDCFG_POLL 0x08000 /* hd_dreq polarity control */
0093 #define HPC3_SDCFG_ERLY 0x30000 /* hd_dreq behavior control bits */
0094
0095     volatile u32 pconfig;   /* PIO configuration register */
0096 #define HPC3_SPCFG_P3   0x0003 /* Cycles to spend in P3 state */
0097 #define HPC3_SPCFG_P2W  0x001c /* Cycles to spend in P2 state for writes */
0098 #define HPC3_SPCFG_P2R  0x01e0 /* Cycles to spend in P2 state for reads */
0099 #define HPC3_SPCFG_P1   0x0e00 /* Cycles to spend in P1 state */
0100 #define HPC3_SPCFG_HW   0x1000 /* Enable 16-bit halfword PIO accesses to scsi */
0101 #define HPC3_SPCFG_SWAP 0x2000 /* Byte swap all PIO accesses */
0102 #define HPC3_SPCFG_EPAR 0x4000 /* Enable parity checking for PIO */
0103 #define HPC3_SPCFG_FUJI 0x8000 /* Fujitsu scsi controller mode for faster dma/pio */
0104
0105     u32 _unused1[0x1000/4 - 6]; /* padding */
0106 };
0107
0108 /* SEEQ ethernet HPC3 registers, only one seeq per HPC3. */
0109 struct hpc3_ethregs {
0110     /* Receiver registers. */
0111     volatile u32 rx_cbptr;   /* current dma buffer ptr, diagnostic use only */
0112     volatile u32 rx_ndptr;   /* next dma descriptor ptr */
0113     u32 _unused0[0x1000/4 - 2]; /* padding */
0114     volatile u32 rx_bcd;    /* byte count info */
0115 #define HPC3_ERXBCD_BCNTMSK 0x00003fff /* bytes to be sent to memory */
0116 #define HPC3_ERXBCD_XIE     0x20000000 /* HPC3 interrupts cpu at end of this buf */
0117 #define HPC3_ERXBCD_EOX     0x80000000 /* flags this as end of descriptor chain */
0118
0119     volatile u32 rx_ctrl;   /* control register */
0120 #define HPC3_ERXCTRL_STAT50 0x0000003f /* Receive status reg bits of Seeq8003 */
0121 #define HPC3_ERXCTRL_STAT6  0x00000040 /* Rdonly irq status */
0122 #define HPC3_ERXCTRL_STAT7  0x00000080 /* Rdonlt old/new status bit from Seeq */
0123 #define HPC3_ERXCTRL_ENDIAN 0x00000100 /* Endian for dma channel, little=1 big=0 */
0124 #define HPC3_ERXCTRL_ACTIVE 0x00000200 /* Tells if DMA transfer is in progress */
0125 #define HPC3_ERXCTRL_AMASK  0x00000400 /* Tells if ACTIVE inhibits PIO's to hpc3 */
0126 #define HPC3_ERXCTRL_RBO    0x00000800 /* Receive buffer overflow if set to 1 */
0127
0128     volatile u32 rx_gfptr;  /* current GIO fifo ptr */
0129     volatile u32 rx_dfptr;  /* current device fifo ptr */
0130     u32 _unused1;       /* padding */
0131     volatile u32 reset; /* reset register */
0132 #define HPC3_ERST_CRESET 0x1    /* Reset dma channel and external controller */
0133 #define HPC3_ERST_CLRIRQ 0x2    /* Clear channel interrupt */
0134 #define HPC3_ERST_LBACK  0x4    /* Enable diagnostic loopback mode of Seeq8003 */
0135
0136     volatile u32 dconfig;    /* DMA configuration register */
0137 #define HPC3_EDCFG_D1    0x0000f /* Cycles to spend in D1 state for PIO */
0138 #define HPC3_EDCFG_D2    0x000f0 /* Cycles to spend in D2 state for PIO */
0139 #define HPC3_EDCFG_D3    0x00f00 /* Cycles to spend in D3 state for PIO */
0140 #define HPC3_EDCFG_WCTRL 0x01000 /* Enable writes of desc into ex ctrl port */
0141 #define HPC3_EDCFG_FRXDC 0x02000 /* Clear eop stat bits upon rxdc, hw seeq fix */
0142 #define HPC3_EDCFG_FEOP  0x04000 /* Bad packet marker timeout enable */
0143 #define HPC3_EDCFG_FIRQ  0x08000 /* Another bad packet timeout enable */
0144 #define HPC3_EDCFG_PTO   0x30000 /* Programmed timeout value for above two */
0145
0146     volatile u32 pconfig;   /* PIO configuration register */
0147 #define HPC3_EPCFG_P1    0x000f /* Cycles to spend in P1 state for PIO */
0148 #define HPC3_EPCFG_P2    0x00f0 /* Cycles to spend in P2 state for PIO */
0149 #define HPC3_EPCFG_P3    0x0f00 /* Cycles to spend in P3 state for PIO */
0150 #define HPC3_EPCFG_TST   0x1000 /* Diagnostic ram test feature bit */
0151
0152     u32 _unused2[0x1000/4 - 8]; /* padding */
0153
0154     /* Transmitter registers. */
0155     volatile u32 tx_cbptr;  /* current dma buffer ptr, diagnostic use only */
0156     volatile u32 tx_ndptr;  /* next dma descriptor ptr */
0157     u32 _unused3[0x1000/4 - 2]; /* padding */
0158     volatile u32 tx_bcd;        /* byte count info */
0159 #define HPC3_ETXBCD_BCNTMSK 0x00003fff  /* bytes to be read from memory */
0160 #define HPC3_ETXBCD_ESAMP   0x10000000  /* if set, too late to add descriptor */
0161 #define HPC3_ETXBCD_XIE     0x20000000  /* Interrupt cpu at end of cur desc */
0162 #define HPC3_ETXBCD_EOP     0x40000000  /* Last byte of cur buf is end of packet */
0163 #define HPC3_ETXBCD_EOX     0x80000000  /* This buf is the end of desc chain */
0164
0165     volatile u32 tx_ctrl;       /* control register */
0166 #define HPC3_ETXCTRL_STAT30 0x0000000f  /* Rdonly copy of seeq tx stat reg */
0167 #define HPC3_ETXCTRL_STAT4  0x00000010  /* Indicate late collision occurred */
0168 #define HPC3_ETXCTRL_STAT75 0x000000e0  /* Rdonly irq status from seeq */
0169 #define HPC3_ETXCTRL_ENDIAN 0x00000100  /* DMA channel endian mode, 1=little 0=big */
0170 #define HPC3_ETXCTRL_ACTIVE 0x00000200  /* DMA tx channel is active */
0171 #define HPC3_ETXCTRL_AMASK  0x00000400  /* Indicates ACTIVE inhibits PIO's */
0172
0173     volatile u32 tx_gfptr;      /* current GIO fifo ptr */
0174     volatile u32 tx_dfptr;      /* current device fifo ptr */
0175     u32 _unused4[0x1000/4 - 4]; /* padding */
0176 };
0177
0178 struct hpc3_regs {
0179     /* First regs for the PBUS 8 dma channels. */
0180     struct hpc3_pbus_dmacregs pbdma[8];
0181
0182     /* Now the HPC scsi registers, we get two scsi reg sets. */
0183     struct hpc3_scsiregs scsi_chan0, scsi_chan1;
0184
0185     /* The SEEQ hpc3 ethernet dma/control registers. */
0186     struct hpc3_ethregs ethregs;
0187
0188     /* Here are where the hpc3 fifo's can be directly accessed
0189      * via PIO accesses.  Under normal operation we never stick
0190      * our grubby paws in here so it's just padding. */
0191     u32 _unused0[0x18000/4];
0192
0193     /* HPC3 irq status regs.  Due to a peculiar bug you need to
0194      * look at two different register addresses to get at all of
0195      * the status bits.  The first reg can only reliably report
0196      * bits 4:0 of the status, and the second reg can only
0197      * reliably report bits 9:5 of the hpc3 irq status.  I told
0198      * you it was a peculiar bug. ;-)
0199      */
0200     volatile u32 istat0;        /* Irq status, only bits <4:0> reliable. */
0201 #define HPC3_ISTAT_PBIMASK  0x0ff   /* irq bits for pbus devs 0 --> 7 */
0202 #define HPC3_ISTAT_SC0MASK  0x100   /* irq bit for scsi channel 0 */
0203 #define HPC3_ISTAT_SC1MASK  0x200   /* irq bit for scsi channel 1 */
0204
0205     volatile u32 gio_misc;      /* GIO misc control bits. */
0206 #define HPC3_GIOMISC_ERTIME 0x1 /* Enable external timer real time. */
0207 #define HPC3_GIOMISC_DENDIAN    0x2 /* dma descriptor endian, 1=lit 0=big */
0208
0209     u32 eeprom;         /* EEPROM data reg. */
0210 #define HPC3_EEPROM_EPROT   0x01    /* Protect register enable */
0211 #define HPC3_EEPROM_CSEL    0x02    /* Chip select */
0212 #define HPC3_EEPROM_ECLK    0x04    /* EEPROM clock */
0213 #define HPC3_EEPROM_DATO    0x08    /* Data out */
0214 #define HPC3_EEPROM_DATI    0x10    /* Data in */
0215
0216     volatile u32 istat1;        /* Irq status, only bits <9:5> reliable. */
0217     volatile u32 bestat;        /* Bus error interrupt status reg. */
0218 #define HPC3_BESTAT_BLMASK  0x000ff /* Bus lane where bad parity occurred */
0219 #define HPC3_BESTAT_CTYPE   0x00100 /* Bus cycle type, 0=PIO 1=DMA */
0220 #define HPC3_BESTAT_PIDSHIFT    9
0221 #define HPC3_BESTAT_PIDMASK 0x3f700 /* DMA channel parity identifier */
0222
0223     u32 _unused1[0x14000/4 - 5];    /* padding */
0224
0225     /* Now direct PIO per-HPC3 peripheral access to external regs. */
0226     volatile u32 scsi0_ext[256];    /* SCSI channel 0 external regs */
0227     u32 _unused2[0x7c00/4];
0228     volatile u32 scsi1_ext[256];    /* SCSI channel 1 external regs */
0229     u32 _unused3[0x7c00/4];
0230     volatile u32 eth_ext[320];  /* Ethernet external registers */
0231     u32 _unused4[0x3b00/4];
0232
0233     /* Per-peripheral device external registers and DMA/PIO control. */
0234     volatile u32 pbus_extregs[16][256];
0235     volatile u32 pbus_dmacfg[8][128];
0236     /* Cycles to spend in D3 for reads */
0237 #define HPC3_DMACFG_D3R_MASK        0x00000001
0238 #define HPC3_DMACFG_D3R_SHIFT       0
0239     /* Cycles to spend in D4 for reads */
0240 #define HPC3_DMACFG_D4R_MASK        0x0000001e
0241 #define HPC3_DMACFG_D4R_SHIFT       1
0242     /* Cycles to spend in D5 for reads */
0243 #define HPC3_DMACFG_D5R_MASK        0x000001e0
0244 #define HPC3_DMACFG_D5R_SHIFT       5
0245     /* Cycles to spend in D3 for writes */
0246 #define HPC3_DMACFG_D3W_MASK        0x00000200
0247 #define HPC3_DMACFG_D3W_SHIFT       9
0248     /* Cycles to spend in D4 for writes */
0249 #define HPC3_DMACFG_D4W_MASK        0x00003c00
0250 #define HPC3_DMACFG_D4W_SHIFT       10
0251     /* Cycles to spend in D5 for writes */
0252 #define HPC3_DMACFG_D5W_MASK        0x0003c000
0253 #define HPC3_DMACFG_D5W_SHIFT       14
0254     /* Enable 16-bit DMA access mode */
0255 #define HPC3_DMACFG_DS16        0x00040000
0256     /* Places halfwords on high 16 bits of bus */
0257 #define HPC3_DMACFG_EVENHI      0x00080000
0258     /* Make this device real time */
0259 #define HPC3_DMACFG_RTIME       0x00200000
0260     /* 5 bit burst count for DMA device */
0261 #define HPC3_DMACFG_BURST_MASK      0x07c00000
0262 #define HPC3_DMACFG_BURST_SHIFT 22
0263     /* Use live pbus_dreq unsynchronized signal */
0264 #define HPC3_DMACFG_DRQLIVE     0x08000000
0265     volatile u32 pbus_piocfg[16][64];
0266     /* Cycles to spend in P2 state for reads */
0267 #define HPC3_PIOCFG_P2R_MASK        0x00001
0268 #define HPC3_PIOCFG_P2R_SHIFT       0
0269     /* Cycles to spend in P3 state for reads */
0270 #define HPC3_PIOCFG_P3R_MASK        0x0001e
0271 #define HPC3_PIOCFG_P3R_SHIFT       1
0272     /* Cycles to spend in P4 state for reads */
0273 #define HPC3_PIOCFG_P4R_MASK        0x001e0
0274 #define HPC3_PIOCFG_P4R_SHIFT       5
0275     /* Cycles to spend in P2 state for writes */
0276 #define HPC3_PIOCFG_P2W_MASK        0x00200
0277 #define HPC3_PIOCFG_P2W_SHIFT       9
0278     /* Cycles to spend in P3 state for writes */
0279 #define HPC3_PIOCFG_P3W_MASK        0x03c00
0280 #define HPC3_PIOCFG_P3W_SHIFT       10
0281     /* Cycles to spend in P4 state for writes */
0282 #define HPC3_PIOCFG_P4W_MASK        0x3c000
0283 #define HPC3_PIOCFG_P4W_SHIFT       14
0284     /* Enable 16-bit PIO accesses */
0285 #define HPC3_PIOCFG_DS16        0x40000
0286     /* Place even address bits in bits <15:8> */
0287 #define HPC3_PIOCFG_EVENHI      0x80000
0288
0289     /* PBUS PROM control regs. */
0290     volatile u32 pbus_promwe;   /* PROM write enable register */
0291 #define HPC3_PROM_WENAB 0x1 /* Enable writes to the PROM */
0292
0293     u32 _unused5[0x0800/4 - 1];
0294     volatile u32 pbus_promswap; /* Chip select swap reg */
0295 #define HPC3_PROM_SWAP  0x1 /* invert GIO addr bit to select prom0 or prom1 */
0296
0297     u32 _unused6[0x0800/4 - 1];
0298     volatile u32 pbus_gout; /* PROM general purpose output reg */
0299 #define HPC3_PROM_STAT  0x1 /* General purpose status bit in gout */
0300
0301     u32 _unused7[0x1000/4 - 1];
0302     volatile u32 rtcregs[14];   /* Dallas clock registers */
0303     u32 _unused8[50];
0304     volatile u32 bbram[8192-50-14]; /* Battery backed ram */
0305 };
0306
0307 /*
0308  * It is possible to have two HPC3's within the address space on
0309  * one machine, though only having one is more likely on an Indy.
0310  */
0311 extern struct hpc3_regs *hpc3c0, *hpc3c1;
0312 #define HPC3_CHIP0_BASE     0x1fb80000  /* physical */
0313 #define HPC3_CHIP1_BASE     0x1fb00000  /* physical */
0314
0315 extern void sgihpc_init(void);
0316
0317 #endif /* _SGI_HPC3_H */