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0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * HEART chip definitions
0004  *
0005  * Copyright (C) 2004-2007 Stanislaw Skowronek <skylark@unaligned.org>
0006  *       2009 Johannes Dickgreber <tanzy@gmx.de>
0007  *       2007-2015 Joshua Kinard <kumba@gentoo.org>
0008  */
0009 #ifndef __ASM_SGI_HEART_H
0010 #define __ASM_SGI_HEART_H
0011 
0012 #include <linux/types.h>
0013 #include <linux/time.h>
0014 
0015 /*
0016  * There are 8 DIMM slots on an IP30 system
0017  * board, which are grouped into four banks
0018  */
0019 #define HEART_MEMORY_BANKS  4
0020 
0021 /* HEART can support up to four CPUs */
0022 #define HEART_MAX_CPUS      4
0023 
0024 #define HEART_XKPHYS_BASE   ((void *)(IO_BASE | 0x000000000ff00000ULL))
0025 
0026 /**
0027  * struct ip30_heart_regs - struct that maps IP30 HEART registers.
0028  * @mode: HEART_MODE - Purpose Unknown, machine reset called from here.
0029  * @sdram_mode: HEART_SDRAM_MODE - purpose unknown.
0030  * @mem_refresh: HEART_MEM_REF - purpose unknown.
0031  * @mem_req_arb: HEART_MEM_REQ_ARB - purpose unknown.
0032  * @mem_cfg.q: union for 64bit access to HEART_MEMCFG - 4x 64bit registers.
0033  * @mem_cfg.l: union for 32bit access to HEART_MEMCFG - 8x 32bit registers.
0034  * @fc_mode: HEART_FC_MODE - Purpose Unknown, possibly for GFX flow control.
0035  * @fc_timer_limit: HEART_FC_TIMER_LIMIT - purpose unknown.
0036  * @fc_addr: HEART_FC0_ADDR, HEART_FC1_ADDR - purpose unknown.
0037  * @fc_credit_cnt: HEART_FC0_CR_CNT, HEART_FC1_CR_CNT - purpose unknown.
0038  * @fc_timer: HEART_FC0_TIMER, HEART_FC1_TIMER - purpose unknown.
0039  * @status: HEART_STATUS - HEART status information.
0040  * @bus_err_addr: HEART_BERR_ADDR - likely contains addr of recent SIGBUS.
0041  * @bus_err_misc: HEART_BERR_MISC - purpose unknown.
0042  * @mem_err_addr: HEART_MEMERR_ADDR - likely contains addr of recent mem err.
0043  * @mem_err_data: HEART_MEMERR_DATA - purpose unknown.
0044  * @piur_acc_err: HEART_PIUR_ACC_ERR - likely for access err to HEART regs.
0045  * @mlan_clock_div: HEART_MLAN_CLK_DIV - MicroLAN clock divider.
0046  * @mlan_ctrl: HEART_MLAN_CTL - MicroLAN control.
0047  * @__pad0: 0x0f40 bytes of padding -> next HEART register 0x01000.
0048  * @undefined: Undefined/diag register, write to it triggers PIUR_ACC_ERR.
0049  * @__pad1: 0xeff8 bytes of padding -> next HEART register 0x10000.
0050  * @imr: HEART_IMR0 to HEART_IMR3 - per-cpu interrupt mask register.
0051  * @set_isr: HEART_SET_ISR - set interrupt status register.
0052  * @clear_isr: HEART_CLR_ISR - clear interrupt status register.
0053  * @isr: HEART_ISR - interrupt status register (read-only).
0054  * @imsr: HEART_IMSR - purpose unknown.
0055  * @cause: HEART_CAUSE - HEART cause information.
0056  * @__pad2: 0xffb8 bytes of padding -> next HEART register 0x20000.
0057  * @count: HEART_COUNT - 52-bit counter.
0058  * @__pad3: 0xfff8 bytes of padding -> next HEART register 0x30000.
0059  * @compare: HEART_COMPARE - 24-bit compare.
0060  * @__pad4: 0xfff8 bytes of padding -> next HEART register 0x40000.
0061  * @trigger: HEART_TRIGGER - purpose unknown.
0062  * @__pad5: 0xfff8 bytes of padding -> next HEART register 0x50000.
0063  * @cpuid: HEART_PRID - contains CPU ID of CPU currently accessing HEART.
0064  * @__pad6: 0xfff8 bytes of padding -> next HEART register 0x60000.
0065  * @sync: HEART_SYNC - purpose unknown.
0066  *
0067  * HEART is the main system controller ASIC for IP30 system.  It incorporates
0068  * a memory controller, interrupt status/cause/set/clear management, basic
0069  * timer with count/compare, and other functionality.  For Linux, not all of
0070  * HEART's functions are fully understood.
0071  *
0072  * Implementation note: All HEART registers are 64bits-wide, but the mem_cfg
0073  * register only reports correct values if queried in 32bits.  Hence the need
0074  * for a union.  Even though mem_cfg.l has 8 array slots, we only ever query
0075  * up to 4 of those.  IP30 has 8 DIMM slots arranged into 4 banks, w/ 2 DIMMs
0076  * per bank.  Each 32bit read accesses one of these banks.  Perhaps HEART was
0077  * designed to address up to 8 banks (16 DIMMs)?  We may never know.
0078  */
0079 struct ip30_heart_regs {        /* 0x0ff00000 */
0080     u64 mode;           /* +  0x00000 */
0081     /* Memory */
0082     u64 sdram_mode;         /* +  0x00008 */
0083     u64 mem_refresh;        /* +  0x00010 */
0084     u64 mem_req_arb;        /* +  0x00018 */
0085     union {
0086         u64 q[HEART_MEMORY_BANKS];  /* readq() */
0087         u32 l[HEART_MEMORY_BANKS * 2];  /* readl() */
0088     } mem_cfg;          /* +  0x00020 */
0089     /* Flow control (gfx?) */
0090     u64 fc_mode;            /* +  0x00040 */
0091     u64 fc_timer_limit;     /* +  0x00048 */
0092     u64 fc_addr[2];         /* +  0x00050 */
0093     u64 fc_credit_cnt[2];       /* +  0x00060 */
0094     u64 fc_timer[2];        /* +  0x00070 */
0095     /* Status */
0096     u64 status;         /* +  0x00080 */
0097     /* Bus error */
0098     u64 bus_err_addr;       /* +  0x00088 */
0099     u64 bus_err_misc;       /* +  0x00090 */
0100     /* Memory error */
0101     u64 mem_err_addr;       /* +  0x00098 */
0102     u64 mem_err_data;       /* +  0x000a0 */
0103     /* Misc */
0104     u64 piur_acc_err;       /* +  0x000a8 */
0105     u64 mlan_clock_div;     /* +  0x000b0 */
0106     u64 mlan_ctrl;          /* +  0x000b8 */
0107     u64 __pad0[0x01e8];     /* +  0x000c0 + 0x0f40 */
0108     /* Undefined */
0109     u64 undefined;          /* +  0x01000 */
0110     u64 __pad1[0x1dff];     /* +  0x01008 + 0xeff8 */
0111     /* Interrupts */
0112     u64 imr[HEART_MAX_CPUS];    /* +  0x10000 */
0113     u64 set_isr;            /* +  0x10020 */
0114     u64 clear_isr;          /* +  0x10028 */
0115     u64 isr;            /* +  0x10030 */
0116     u64 imsr;           /* +  0x10038 */
0117     u64 cause;          /* +  0x10040 */
0118     u64 __pad2[0x1ff7];     /* +  0x10048 + 0xffb8 */
0119     /* Timer */
0120     u64 count;          /* +  0x20000 */
0121     u64 __pad3[0x1fff];     /* +  0x20008 + 0xfff8 */
0122     u64 compare;            /* +  0x30000 */
0123     u64 __pad4[0x1fff];     /* +  0x30008 + 0xfff8 */
0124     u64 trigger;            /* +  0x40000 */
0125     u64 __pad5[0x1fff];     /* +  0x40008 + 0xfff8 */
0126     /* Misc */
0127     u64 cpuid;          /* +  0x50000 */
0128     u64 __pad6[0x1fff];     /* +  0x50008 + 0xfff8 */
0129     u64 sync;           /* +  0x60000 */
0130 };
0131 
0132 
0133 /* For timer-related bits. */
0134 #define HEART_NS_PER_CYCLE  80
0135 #define HEART_CYCLES_PER_SEC    (NSEC_PER_SEC / HEART_NS_PER_CYCLE)
0136 
0137 
0138 /*
0139  * XXX: Everything below this comment will either go away or be cleaned
0140  *      up to fit in better with Linux.  A lot of the bit definitions for
0141  *      HEART were derived from IRIX's sys/RACER/heart.h header file.
0142  */
0143 
0144 /* HEART Masks */
0145 #define HEART_ATK_MASK      0x0007ffffffffffff  /* HEART attack mask */
0146 #define HEART_ACK_ALL_MASK  0xffffffffffffffff  /* Ack everything */
0147 #define HEART_CLR_ALL_MASK  0x0000000000000000  /* Clear all */
0148 #define HEART_BR_ERR_MASK   0x7ff8000000000000  /* BRIDGE error mask */
0149 #define HEART_CPU0_ERR_MASK 0x8ff8000000000000  /* CPU0 error mask */
0150 #define HEART_CPU1_ERR_MASK 0x97f8000000000000  /* CPU1 error mask */
0151 #define HEART_CPU2_ERR_MASK 0xa7f8000000000000  /* CPU2 error mask */
0152 #define HEART_CPU3_ERR_MASK 0xc7f8000000000000  /* CPU3 error mask */
0153 #define HEART_ERR_MASK      0x1ff           /* HEART error mask */
0154 #define HEART_ERR_MASK_START    51          /* HEART error start */
0155 #define HEART_ERR_MASK_END  63          /* HEART error end */
0156 
0157 /* Bits in the HEART_MODE register. */
0158 #define HM_PROC_DISABLE_SHFT        60
0159 #define HM_PROC_DISABLE_MSK     (0xfUL << HM_PROC_DISABLE_SHFT)
0160 #define HM_PROC_DISABLE(x)      (0x1UL << (x) + HM_PROC_DISABLE_SHFT)
0161 #define HM_MAX_PSR          (0x7UL << 57)
0162 #define HM_MAX_IOSR         (0x7UL << 54)
0163 #define HM_MAX_PEND_IOSR        (0x7UL << 51)
0164 #define HM_TRIG_SRC_SEL_MSK     (0x7UL << 48)
0165 #define HM_TRIG_HEART_EXC       (0x0UL << 48)
0166 #define HM_TRIG_REG_BIT         (0x1UL << 48)
0167 #define HM_TRIG_SYSCLK          (0x2UL << 48)
0168 #define HM_TRIG_MEMCLK_2X       (0x3UL << 48)
0169 #define HM_TRIG_MEMCLK          (0x4UL << 48)
0170 #define HM_TRIG_IOCLK           (0x5UL << 48)
0171 #define HM_PIU_TEST_MODE        (0xfUL << 40)
0172 #define HM_GP_FLAG_MSK          (0xfUL << 36)
0173 #define HM_GP_FLAG(x)           BIT((x) + 36)
0174 #define HM_MAX_PROC_HYST        (0xfUL << 32)
0175 #define HM_LLP_WRST_AFTER_RST       BIT(28)
0176 #define HM_LLP_LINK_RST         BIT(27)
0177 #define HM_LLP_WARM_RST         BIT(26)
0178 #define HM_COR_ECC_LCK          BIT(25)
0179 #define HM_REDUCED_PWR          BIT(24)
0180 #define HM_COLD_RST         BIT(23)
0181 #define HM_SW_RST           BIT(22)
0182 #define HM_MEM_FORCE_WR         BIT(21)
0183 #define HM_DB_ERR_GEN           BIT(20)
0184 #define HM_SB_ERR_GEN           BIT(19)
0185 #define HM_CACHED_PIO_EN        BIT(18)
0186 #define HM_CACHED_PROM_EN       BIT(17)
0187 #define HM_PE_SYS_COR_ERE       BIT(16)
0188 #define HM_GLOBAL_ECC_EN        BIT(15)
0189 #define HM_IO_COH_EN            BIT(14)
0190 #define HM_INT_EN           BIT(13)
0191 #define HM_DATA_CHK_EN          BIT(12)
0192 #define HM_REF_EN           BIT(11)
0193 #define HM_BAD_SYSWR_ERE        BIT(10)
0194 #define HM_BAD_SYSRD_ERE        BIT(9)
0195 #define HM_SYSSTATE_ERE         BIT(8)
0196 #define HM_SYSCMD_ERE           BIT(7)
0197 #define HM_NCOR_SYS_ERE         BIT(6)
0198 #define HM_COR_SYS_ERE          BIT(5)
0199 #define HM_DATA_ELMNT_ERE       BIT(4)
0200 #define HM_MEM_ADDR_PROC_ERE        BIT(3)
0201 #define HM_MEM_ADDR_IO_ERE      BIT(2)
0202 #define HM_NCOR_MEM_ERE         BIT(1)
0203 #define HM_COR_MEM_ERE          BIT(0)
0204 
0205 /* Bits in the HEART_MEM_REF register. */
0206 #define HEART_MEMREF_REFS(x)        ((0xfUL & (x)) << 16)
0207 #define HEART_MEMREF_PERIOD(x)      ((0xffffUL & (x)))
0208 #define HEART_MEMREF_REFS_VAL       HEART_MEMREF_REFS(8)
0209 #define HEART_MEMREF_PERIOD_VAL     HEART_MEMREF_PERIOD(0x4000)
0210 #define HEART_MEMREF_VAL        (HEART_MEMREF_REFS_VAL | \
0211                      HEART_MEMREF_PERIOD_VAL)
0212 
0213 /* Bits in the HEART_MEM_REQ_ARB register. */
0214 #define HEART_MEMARB_IODIS      (1  << 20)
0215 #define HEART_MEMARB_MAXPMWRQS      (15 << 16)
0216 #define HEART_MEMARB_MAXPMRRQS      (15 << 12)
0217 #define HEART_MEMARB_MAXPMRQS       (15 << 8)
0218 #define HEART_MEMARB_MAXRRRQS       (15 << 4)
0219 #define HEART_MEMARB_MAXGBRRQS      (15)
0220 
0221 /* Bits in the HEART_MEMCFG<x> registers. */
0222 #define HEART_MEMCFG_VALID      0x80000000  /* Bank is valid */
0223 #define HEART_MEMCFG_DENSITY        0x01c00000  /* Mem density */
0224 #define HEART_MEMCFG_SIZE_MASK      0x003f0000  /* Mem size mask */
0225 #define HEART_MEMCFG_ADDR_MASK      0x000001ff  /* Base addr mask */
0226 #define HEART_MEMCFG_SIZE_SHIFT     16      /* Mem size shift */
0227 #define HEART_MEMCFG_DENSITY_SHIFT  22      /* Density Shift */
0228 #define HEART_MEMCFG_UNIT_SHIFT     25      /* Unit Shift, 32MB */
0229 
0230 /* Bits in the HEART_STATUS register */
0231 #define HEART_STAT_HSTL_SDRV        BIT(14)
0232 #define HEART_STAT_FC_CR_OUT(x)     BIT((x) + 12)
0233 #define HEART_STAT_DIR_CNNCT        BIT(11)
0234 #define HEART_STAT_TRITON       BIT(10)
0235 #define HEART_STAT_R4K          BIT(9)
0236 #define HEART_STAT_BIG_ENDIAN       BIT(8)
0237 #define HEART_STAT_PROC_SHFT        4
0238 #define HEART_STAT_PROC_MSK     (0xfUL << HEART_STAT_PROC_SHFT)
0239 #define HEART_STAT_PROC_ACTIVE(x)   (0x1UL << ((x) + HEART_STAT_PROC_SHFT))
0240 #define HEART_STAT_WIDGET_ID        0xf
0241 
0242 /* Bits in the HEART_CAUSE register */
0243 #define HC_PE_SYS_COR_ERR_MSK       (0xfUL << 60)
0244 #define HC_PE_SYS_COR_ERR(x)        BIT((x) + 60)
0245 #define HC_PIOWDB_OFLOW         BIT(44)
0246 #define HC_PIORWRB_OFLOW        BIT(43)
0247 #define HC_PIUR_ACC_ERR         BIT(42)
0248 #define HC_BAD_SYSWR_ERR        BIT(41)
0249 #define HC_BAD_SYSRD_ERR        BIT(40)
0250 #define HC_SYSSTATE_ERR_MSK     (0xfUL << 36)
0251 #define HC_SYSSTATE_ERR(x)      BIT((x) + 36)
0252 #define HC_SYSCMD_ERR_MSK       (0xfUL << 32)
0253 #define HC_SYSCMD_ERR(x)        BIT((x) + 32)
0254 #define HC_NCOR_SYSAD_ERR_MSK       (0xfUL << 28)
0255 #define HC_NCOR_SYSAD_ERR(x)        BIT((x) + 28)
0256 #define HC_COR_SYSAD_ERR_MSK        (0xfUL << 24)
0257 #define HC_COR_SYSAD_ERR(x)     BIT((x) + 24)
0258 #define HC_DATA_ELMNT_ERR_MSK       (0xfUL << 20)
0259 #define HC_DATA_ELMNT_ERR(x)        BIT((x) + 20)
0260 #define HC_WIDGET_ERR           BIT(16)
0261 #define HC_MEM_ADDR_ERR_PROC_MSK    (0xfUL << 4)
0262 #define HC_MEM_ADDR_ERR_PROC(x) BIT((x) + 4)
0263 #define HC_MEM_ADDR_ERR_IO      BIT(2)
0264 #define HC_NCOR_MEM_ERR         BIT(1)
0265 #define HC_COR_MEM_ERR          BIT(0)
0266 
0267 /*
0268  * HEART has 64 interrupt vectors available to it, subdivided into five
0269  * priority levels.  They are numbered 0 to 63.
0270  */
0271 #define HEART_NUM_IRQS          64
0272 
0273 /*
0274  * These are the five interrupt priority levels and their corresponding
0275  * CPU IPx interrupt pins.
0276  *
0277  * Level 4 - Error Interrupts.
0278  * Level 3 - HEART timer interrupt.
0279  * Level 2 - CPU IPI, CPU debug, power putton, general device interrupts.
0280  * Level 1 - General device interrupts.
0281  * Level 0 - General device GFX flow control interrupts.
0282  */
0283 #define HEART_L4_INT_MASK       0xfff8000000000000ULL   /* IP6 */
0284 #define HEART_L3_INT_MASK       0x0004000000000000ULL   /* IP5 */
0285 #define HEART_L2_INT_MASK       0x0003ffff00000000ULL   /* IP4 */
0286 #define HEART_L1_INT_MASK       0x00000000ffff0000ULL   /* IP3 */
0287 #define HEART_L0_INT_MASK       0x000000000000ffffULL   /* IP2 */
0288 
0289 /* HEART L0 Interrupts (Low Priority) */
0290 #define HEART_L0_INT_GENERIC         0
0291 #define HEART_L0_INT_FLOW_CTRL_HWTR_0    1
0292 #define HEART_L0_INT_FLOW_CTRL_HWTR_1    2
0293 
0294 /* HEART L2 Interrupts (High Priority) */
0295 #define HEART_L2_INT_RESCHED_CPU_0  46
0296 #define HEART_L2_INT_RESCHED_CPU_1  47
0297 #define HEART_L2_INT_CALL_CPU_0     48
0298 #define HEART_L2_INT_CALL_CPU_1     49
0299 
0300 /* HEART L3 Interrupts (Compare/Counter Timer) */
0301 #define HEART_L3_INT_TIMER      50
0302 
0303 /* HEART L4 Interrupts (Errors) */
0304 #define HEART_L4_INT_XWID_ERR_9     51
0305 #define HEART_L4_INT_XWID_ERR_A     52
0306 #define HEART_L4_INT_XWID_ERR_B     53
0307 #define HEART_L4_INT_XWID_ERR_C     54
0308 #define HEART_L4_INT_XWID_ERR_D     55
0309 #define HEART_L4_INT_XWID_ERR_E     56
0310 #define HEART_L4_INT_XWID_ERR_F     57
0311 #define HEART_L4_INT_XWID_ERR_XBOW  58
0312 #define HEART_L4_INT_CPU_BUS_ERR_0  59
0313 #define HEART_L4_INT_CPU_BUS_ERR_1  60
0314 #define HEART_L4_INT_CPU_BUS_ERR_2  61
0315 #define HEART_L4_INT_CPU_BUS_ERR_3  62
0316 #define HEART_L4_INT_HEART_EXCP     63
0317 
0318 extern struct ip30_heart_regs __iomem *heart_regs;
0319 
0320 #define heart_read  ____raw_readq
0321 #define heart_write ____raw_writeq
0322 
0323 #endif /* __ASM_SGI_HEART_H */