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0009 #ifndef __ASM_SGI_HEART_H
0010 #define __ASM_SGI_HEART_H
0011
0012 #include <linux/types.h>
0013 #include <linux/time.h>
0014
0015
0016
0017
0018
0019 #define HEART_MEMORY_BANKS 4
0020
0021
0022 #define HEART_MAX_CPUS 4
0023
0024 #define HEART_XKPHYS_BASE ((void *)(IO_BASE | 0x000000000ff00000ULL))
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0079 struct ip30_heart_regs {
0080 u64 mode;
0081
0082 u64 sdram_mode;
0083 u64 mem_refresh;
0084 u64 mem_req_arb;
0085 union {
0086 u64 q[HEART_MEMORY_BANKS];
0087 u32 l[HEART_MEMORY_BANKS * 2];
0088 } mem_cfg;
0089
0090 u64 fc_mode;
0091 u64 fc_timer_limit;
0092 u64 fc_addr[2];
0093 u64 fc_credit_cnt[2];
0094 u64 fc_timer[2];
0095
0096 u64 status;
0097
0098 u64 bus_err_addr;
0099 u64 bus_err_misc;
0100
0101 u64 mem_err_addr;
0102 u64 mem_err_data;
0103
0104 u64 piur_acc_err;
0105 u64 mlan_clock_div;
0106 u64 mlan_ctrl;
0107 u64 __pad0[0x01e8];
0108
0109 u64 undefined;
0110 u64 __pad1[0x1dff];
0111
0112 u64 imr[HEART_MAX_CPUS];
0113 u64 set_isr;
0114 u64 clear_isr;
0115 u64 isr;
0116 u64 imsr;
0117 u64 cause;
0118 u64 __pad2[0x1ff7];
0119
0120 u64 count;
0121 u64 __pad3[0x1fff];
0122 u64 compare;
0123 u64 __pad4[0x1fff];
0124 u64 trigger;
0125 u64 __pad5[0x1fff];
0126
0127 u64 cpuid;
0128 u64 __pad6[0x1fff];
0129 u64 sync;
0130 };
0131
0132
0133
0134 #define HEART_NS_PER_CYCLE 80
0135 #define HEART_CYCLES_PER_SEC (NSEC_PER_SEC / HEART_NS_PER_CYCLE)
0136
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0144
0145 #define HEART_ATK_MASK 0x0007ffffffffffff
0146 #define HEART_ACK_ALL_MASK 0xffffffffffffffff
0147 #define HEART_CLR_ALL_MASK 0x0000000000000000
0148 #define HEART_BR_ERR_MASK 0x7ff8000000000000
0149 #define HEART_CPU0_ERR_MASK 0x8ff8000000000000
0150 #define HEART_CPU1_ERR_MASK 0x97f8000000000000
0151 #define HEART_CPU2_ERR_MASK 0xa7f8000000000000
0152 #define HEART_CPU3_ERR_MASK 0xc7f8000000000000
0153 #define HEART_ERR_MASK 0x1ff
0154 #define HEART_ERR_MASK_START 51
0155 #define HEART_ERR_MASK_END 63
0156
0157
0158 #define HM_PROC_DISABLE_SHFT 60
0159 #define HM_PROC_DISABLE_MSK (0xfUL << HM_PROC_DISABLE_SHFT)
0160 #define HM_PROC_DISABLE(x) (0x1UL << (x) + HM_PROC_DISABLE_SHFT)
0161 #define HM_MAX_PSR (0x7UL << 57)
0162 #define HM_MAX_IOSR (0x7UL << 54)
0163 #define HM_MAX_PEND_IOSR (0x7UL << 51)
0164 #define HM_TRIG_SRC_SEL_MSK (0x7UL << 48)
0165 #define HM_TRIG_HEART_EXC (0x0UL << 48)
0166 #define HM_TRIG_REG_BIT (0x1UL << 48)
0167 #define HM_TRIG_SYSCLK (0x2UL << 48)
0168 #define HM_TRIG_MEMCLK_2X (0x3UL << 48)
0169 #define HM_TRIG_MEMCLK (0x4UL << 48)
0170 #define HM_TRIG_IOCLK (0x5UL << 48)
0171 #define HM_PIU_TEST_MODE (0xfUL << 40)
0172 #define HM_GP_FLAG_MSK (0xfUL << 36)
0173 #define HM_GP_FLAG(x) BIT((x) + 36)
0174 #define HM_MAX_PROC_HYST (0xfUL << 32)
0175 #define HM_LLP_WRST_AFTER_RST BIT(28)
0176 #define HM_LLP_LINK_RST BIT(27)
0177 #define HM_LLP_WARM_RST BIT(26)
0178 #define HM_COR_ECC_LCK BIT(25)
0179 #define HM_REDUCED_PWR BIT(24)
0180 #define HM_COLD_RST BIT(23)
0181 #define HM_SW_RST BIT(22)
0182 #define HM_MEM_FORCE_WR BIT(21)
0183 #define HM_DB_ERR_GEN BIT(20)
0184 #define HM_SB_ERR_GEN BIT(19)
0185 #define HM_CACHED_PIO_EN BIT(18)
0186 #define HM_CACHED_PROM_EN BIT(17)
0187 #define HM_PE_SYS_COR_ERE BIT(16)
0188 #define HM_GLOBAL_ECC_EN BIT(15)
0189 #define HM_IO_COH_EN BIT(14)
0190 #define HM_INT_EN BIT(13)
0191 #define HM_DATA_CHK_EN BIT(12)
0192 #define HM_REF_EN BIT(11)
0193 #define HM_BAD_SYSWR_ERE BIT(10)
0194 #define HM_BAD_SYSRD_ERE BIT(9)
0195 #define HM_SYSSTATE_ERE BIT(8)
0196 #define HM_SYSCMD_ERE BIT(7)
0197 #define HM_NCOR_SYS_ERE BIT(6)
0198 #define HM_COR_SYS_ERE BIT(5)
0199 #define HM_DATA_ELMNT_ERE BIT(4)
0200 #define HM_MEM_ADDR_PROC_ERE BIT(3)
0201 #define HM_MEM_ADDR_IO_ERE BIT(2)
0202 #define HM_NCOR_MEM_ERE BIT(1)
0203 #define HM_COR_MEM_ERE BIT(0)
0204
0205
0206 #define HEART_MEMREF_REFS(x) ((0xfUL & (x)) << 16)
0207 #define HEART_MEMREF_PERIOD(x) ((0xffffUL & (x)))
0208 #define HEART_MEMREF_REFS_VAL HEART_MEMREF_REFS(8)
0209 #define HEART_MEMREF_PERIOD_VAL HEART_MEMREF_PERIOD(0x4000)
0210 #define HEART_MEMREF_VAL (HEART_MEMREF_REFS_VAL | \
0211 HEART_MEMREF_PERIOD_VAL)
0212
0213
0214 #define HEART_MEMARB_IODIS (1 << 20)
0215 #define HEART_MEMARB_MAXPMWRQS (15 << 16)
0216 #define HEART_MEMARB_MAXPMRRQS (15 << 12)
0217 #define HEART_MEMARB_MAXPMRQS (15 << 8)
0218 #define HEART_MEMARB_MAXRRRQS (15 << 4)
0219 #define HEART_MEMARB_MAXGBRRQS (15)
0220
0221
0222 #define HEART_MEMCFG_VALID 0x80000000
0223 #define HEART_MEMCFG_DENSITY 0x01c00000
0224 #define HEART_MEMCFG_SIZE_MASK 0x003f0000
0225 #define HEART_MEMCFG_ADDR_MASK 0x000001ff
0226 #define HEART_MEMCFG_SIZE_SHIFT 16
0227 #define HEART_MEMCFG_DENSITY_SHIFT 22
0228 #define HEART_MEMCFG_UNIT_SHIFT 25
0229
0230
0231 #define HEART_STAT_HSTL_SDRV BIT(14)
0232 #define HEART_STAT_FC_CR_OUT(x) BIT((x) + 12)
0233 #define HEART_STAT_DIR_CNNCT BIT(11)
0234 #define HEART_STAT_TRITON BIT(10)
0235 #define HEART_STAT_R4K BIT(9)
0236 #define HEART_STAT_BIG_ENDIAN BIT(8)
0237 #define HEART_STAT_PROC_SHFT 4
0238 #define HEART_STAT_PROC_MSK (0xfUL << HEART_STAT_PROC_SHFT)
0239 #define HEART_STAT_PROC_ACTIVE(x) (0x1UL << ((x) + HEART_STAT_PROC_SHFT))
0240 #define HEART_STAT_WIDGET_ID 0xf
0241
0242
0243 #define HC_PE_SYS_COR_ERR_MSK (0xfUL << 60)
0244 #define HC_PE_SYS_COR_ERR(x) BIT((x) + 60)
0245 #define HC_PIOWDB_OFLOW BIT(44)
0246 #define HC_PIORWRB_OFLOW BIT(43)
0247 #define HC_PIUR_ACC_ERR BIT(42)
0248 #define HC_BAD_SYSWR_ERR BIT(41)
0249 #define HC_BAD_SYSRD_ERR BIT(40)
0250 #define HC_SYSSTATE_ERR_MSK (0xfUL << 36)
0251 #define HC_SYSSTATE_ERR(x) BIT((x) + 36)
0252 #define HC_SYSCMD_ERR_MSK (0xfUL << 32)
0253 #define HC_SYSCMD_ERR(x) BIT((x) + 32)
0254 #define HC_NCOR_SYSAD_ERR_MSK (0xfUL << 28)
0255 #define HC_NCOR_SYSAD_ERR(x) BIT((x) + 28)
0256 #define HC_COR_SYSAD_ERR_MSK (0xfUL << 24)
0257 #define HC_COR_SYSAD_ERR(x) BIT((x) + 24)
0258 #define HC_DATA_ELMNT_ERR_MSK (0xfUL << 20)
0259 #define HC_DATA_ELMNT_ERR(x) BIT((x) + 20)
0260 #define HC_WIDGET_ERR BIT(16)
0261 #define HC_MEM_ADDR_ERR_PROC_MSK (0xfUL << 4)
0262 #define HC_MEM_ADDR_ERR_PROC(x) BIT((x) + 4)
0263 #define HC_MEM_ADDR_ERR_IO BIT(2)
0264 #define HC_NCOR_MEM_ERR BIT(1)
0265 #define HC_COR_MEM_ERR BIT(0)
0266
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0271 #define HEART_NUM_IRQS 64
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0283 #define HEART_L4_INT_MASK 0xfff8000000000000ULL
0284 #define HEART_L3_INT_MASK 0x0004000000000000ULL
0285 #define HEART_L2_INT_MASK 0x0003ffff00000000ULL
0286 #define HEART_L1_INT_MASK 0x00000000ffff0000ULL
0287 #define HEART_L0_INT_MASK 0x000000000000ffffULL
0288
0289
0290 #define HEART_L0_INT_GENERIC 0
0291 #define HEART_L0_INT_FLOW_CTRL_HWTR_0 1
0292 #define HEART_L0_INT_FLOW_CTRL_HWTR_1 2
0293
0294
0295 #define HEART_L2_INT_RESCHED_CPU_0 46
0296 #define HEART_L2_INT_RESCHED_CPU_1 47
0297 #define HEART_L2_INT_CALL_CPU_0 48
0298 #define HEART_L2_INT_CALL_CPU_1 49
0299
0300
0301 #define HEART_L3_INT_TIMER 50
0302
0303
0304 #define HEART_L4_INT_XWID_ERR_9 51
0305 #define HEART_L4_INT_XWID_ERR_A 52
0306 #define HEART_L4_INT_XWID_ERR_B 53
0307 #define HEART_L4_INT_XWID_ERR_C 54
0308 #define HEART_L4_INT_XWID_ERR_D 55
0309 #define HEART_L4_INT_XWID_ERR_E 56
0310 #define HEART_L4_INT_XWID_ERR_F 57
0311 #define HEART_L4_INT_XWID_ERR_XBOW 58
0312 #define HEART_L4_INT_CPU_BUS_ERR_0 59
0313 #define HEART_L4_INT_CPU_BUS_ERR_1 60
0314 #define HEART_L4_INT_CPU_BUS_ERR_2 61
0315 #define HEART_L4_INT_CPU_BUS_ERR_3 62
0316 #define HEART_L4_INT_HEART_EXCP 63
0317
0318 extern struct ip30_heart_regs __iomem *heart_regs;
0319
0320 #define heart_read ____raw_readq
0321 #define heart_write ____raw_writeq
0322
0323 #endif