include/asm/prefetch.h

0001 /*
0002  * This file is subject to the terms and conditions of the GNU General Public
0003  * License.  See the file "COPYING" in the main directory of this archive
0004  * for more details.
0005  *
0006  * Copyright (C) 2003 by Ralf Baechle
0007  */
0008 #ifndef __ASM_PREFETCH_H
0009 #define __ASM_PREFETCH_H
0010
0011
0012 /*
0013  * R5000 and RM5200 implements pref and prefx instructions but they're nops, so
0014  * rather than wasting time we pretend these processors don't support
0015  * prefetching at all.
0016  *
0017  * R5432 implements Load, Store, LoadStreamed, StoreStreamed, LoadRetained,
0018  * StoreRetained and WriteBackInvalidate but not Pref_PrepareForStore.
0019  *
0020  * Hell (and the book on my shelf I can't open ...) know what the R8000 does.
0021  *
0022  * RM7000 version 1.0 interprets all hints as Pref_Load; version 2.0 implements
0023  * Pref_PrepareForStore also.
0024  *
0025  * RM9000 is MIPS IV but implements prefetching like MIPS32/MIPS64; it's
0026  * Pref_WriteBackInvalidate is a nop and Pref_PrepareForStore is broken in
0027  * current versions due to erratum G105.
0028  *
0029  * VR5500 (including VR5701 and VR7701) only implement load prefetch.
0030  *
0031  * Finally MIPS32 and MIPS64 implement all of the following hints.
0032  */
0033
0034 #define Pref_Load           0
0035 #define Pref_Store          1
0036                         /* 2 and 3 are reserved */
0037 #define Pref_LoadStreamed       4
0038 #define Pref_StoreStreamed      5
0039 #define Pref_LoadRetained       6
0040 #define Pref_StoreRetained      7
0041                         /* 8 ... 24 are reserved */
0042 #define Pref_WriteBackInvalidate    25
0043 #define Pref_PrepareForStore        30
0044
0045 #ifdef __ASSEMBLY__
0046
0047     .macro  __pref hint addr
0048 #ifdef CONFIG_CPU_HAS_PREFETCH
0049     pref    \hint, \addr
0050 #endif
0051     .endm
0052
0053     .macro  pref_load addr
0054     __pref  Pref_Load, \addr
0055     .endm
0056
0057     .macro  pref_store addr
0058     __pref  Pref_Store, \addr
0059     .endm
0060
0061     .macro  pref_load_streamed addr
0062     __pref  Pref_LoadStreamed, \addr
0063     .endm
0064
0065     .macro  pref_store_streamed addr
0066     __pref  Pref_StoreStreamed, \addr
0067     .endm
0068
0069     .macro  pref_load_retained addr
0070     __pref  Pref_LoadRetained, \addr
0071     .endm
0072
0073     .macro  pref_store_retained addr
0074     __pref  Pref_StoreRetained, \addr
0075     .endm
0076
0077     .macro  pref_wback_inv addr
0078     __pref  Pref_WriteBackInvalidate, \addr
0079     .endm
0080
0081     .macro  pref_prepare_for_store addr
0082     __pref  Pref_PrepareForStore, \addr
0083     .endm
0084
0085 #endif
0086
0087 #endif /* __ASM_PREFETCH_H */